diff options
| author | Xianwei Zhao <xianwei.zhao@amlogic.com> | 2024-05-24 08:35:09 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-06-10 13:49:05 +0200 |
| commit | 022bd9c520d8f9dd51f29326eb369b8ec958f687 (patch) | |
| tree | 7004e001aa6f58018691c459cd466b0e188e5aa3 /drivers/spi | |
| parent | regmap: spi: Fix potential off-by-one when calculating reserved size (diff) | |
| download | linux-022bd9c520d8f9dd51f29326eb369b8ec958f687.tar.xz linux-022bd9c520d8f9dd51f29326eb369b8ec958f687.zip | |
spi: meson-spicc: set SPI clock flag CLK_SET_RATE_PARENT
Add SPI clock flag CLK_SET_RATE_PARENT for using pclk as parent clock.
This gives SPI more flexibility in frequency selection.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Link: https://lore.kernel.org/r/20240524-spi_pclk_setparent-v1-1-99e0ce70b66f@amlogic.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-meson-spicc.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index fc75492e50ff..8a4a8ba9dfed 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -644,11 +644,13 @@ static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc) snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); init.name = name; init.ops = &clk_fixed_factor_ops; - init.flags = 0; - if (spicc->data->has_pclk) + if (spicc->data->has_pclk) { + init.flags = CLK_SET_RATE_PARENT; parent_data[0].hw = __clk_get_hw(spicc->pclk); - else + } else { + init.flags = 0; parent_data[0].hw = __clk_get_hw(spicc->core); + } init.num_parents = 1; pow2_fixed_div->mult = 1, @@ -708,11 +710,13 @@ static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc) snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); init.name = name; init.ops = &clk_fixed_factor_ops; - init.flags = 0; - if (spicc->data->has_pclk) + if (spicc->data->has_pclk) { + init.flags = CLK_SET_RATE_PARENT; parent_data[0].hw = __clk_get_hw(spicc->pclk); - else + } else { + init.flags = 0; parent_data[0].hw = __clk_get_hw(spicc->core); + } init.num_parents = 1; enh_fixed_div->mult = 1, |