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| author | Krishna Yarlagadda <kyarlagadda@nvidia.com> | 2023-04-21 11:13:09 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-04-21 15:37:04 +0200 |
| commit | 967ca91a996f82219f2883e9e53d8e20df49025a (patch) | |
| tree | 01d8e559e14c2a67cbb876754119d69ea44872d0 /drivers/spi | |
| parent | spi: Add TPM HW flow flag (diff) | |
| download | linux-967ca91a996f82219f2883e9e53d8e20df49025a.tar.xz linux-967ca91a996f82219f2883e9e53d8e20df49025a.zip | |
spi: tegra210-quad: Enable TPM wait polling
Trusted Platform Module requires flow control. As defined in TPM
interface specification, client would drive MISO line at same cycle as
last address bit on MOSI.
Tegra234 and Tegra241 QSPI controllers have TPM wait state detection
feature which is enabled for TPM client devices reported in SPI device
mode bits.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Link: https://lore.kernel.org/r/20230421091309.2672-4-kyarlagadda@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-tegra210-quad.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index bea376acea1f..fbd14dd7be44 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -142,6 +142,7 @@ #define QSPI_GLOBAL_CONFIG 0X1a4 #define QSPI_CMB_SEQ_EN BIT(0) +#define QSPI_TPM_WAIT_POLL_EN BIT(1) #define QSPI_CMB_SEQ_ADDR 0x1a8 #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) @@ -164,6 +165,7 @@ struct tegra_qspi_soc_data { bool has_dma; bool cmb_xfer_capable; + bool supports_tpm; unsigned int cs_count; }; @@ -1065,6 +1067,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, /* Enable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); + if (spi->mode & SPI_TPM_HW_FLOW) { + if (tqspi->soc_data->supports_tpm) + val |= QSPI_TPM_WAIT_POLL_EN; + else + return -EIO; + } val |= QSPI_CMB_SEQ_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); /* Process individual transfer list */ @@ -1196,6 +1204,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, /* Disable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); val &= ~QSPI_CMB_SEQ_EN; + if (tqspi->soc_data->supports_tpm) + val &= ~QSPI_TPM_WAIT_POLL_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); list_for_each_entry(transfer, &msg->transfers, transfer_list) { struct spi_transfer *xfer = transfer; @@ -1454,24 +1464,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { .has_dma = true, .cmb_xfer_capable = false, + .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { .has_dma = true, .cmb_xfer_capable = true, + .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { .has_dma = false, .cmb_xfer_capable = true, + .supports_tpm = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { .has_dma = false, .cmb_xfer_capable = true, + .supports_tpm = true, .cs_count = 4, }; |