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authorMika Westerberg <mika.westerberg@linux.intel.com>2022-10-25 08:46:23 +0200
committerMark Brown <broonie@kernel.org>2022-11-25 20:34:06 +0100
commitec4a04aa6962fff3cfa63d70536537844f7446d2 (patch)
treec1ad5deaf4f835352fac4ff67084d2f4613b11b5 /drivers/spi
parentspi: intel: Take possible chip address into account in intel_spi_read/write_r... (diff)
downloadlinux-ec4a04aa6962fff3cfa63d70536537844f7446d2.tar.xz
linux-ec4a04aa6962fff3cfa63d70536537844f7446d2.zip
spi: intel: Add support for SFDP opcode
The Intel SPI-NOR controller supports SFDP (Serial Flash Discoverable Parameter) opcode so add it to the list of supported opcodes. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20221025064623.22808-5-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-intel.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c
index 4d8fda991e7b..71c36ad778fc 100644
--- a/drivers/spi/spi-intel.c
+++ b/drivers/spi/spi-intel.c
@@ -33,6 +33,7 @@
#define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
+#define HSFSTS_CTL_FCYCLE_RDSFDP (0x05 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
#define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
@@ -920,6 +921,11 @@ static const struct spi_controller_mem_ops intel_spi_mem_ops = {
INTEL_SPI_OP_DATA_OUT(1), \
intel_spi_write_reg, \
HSFSTS_CTL_FCYCLE_WRSR), \
+ INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSFDP, 1), \
+ INTEL_SPI_OP_ADDR(3), \
+ INTEL_SPI_OP_DATA_IN(1), \
+ intel_spi_read_reg, \
+ HSFSTS_CTL_FCYCLE_RDSFDP), \
/* Normal read */ \
INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
INTEL_SPI_OP_ADDR(3), \