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authorMika Westerberg <mika.westerberg@linux.intel.com>2023-05-17 09:45:53 +0200
committerMika Westerberg <mika.westerberg@linux.intel.com>2023-06-16 08:53:28 +0200
commitf2bfa944080dcbb8eb56259dfd2c07204cbee17e (patch)
tree25840613536fefc2dc29cd1a4121dc26046786d0 /drivers/thunderbolt/quirks.c
parentthunderbolt: Add Intel Barlow Ridge PCI ID (diff)
downloadlinux-f2bfa944080dcbb8eb56259dfd2c07204cbee17e.tar.xz
linux-f2bfa944080dcbb8eb56259dfd2c07204cbee17e.zip
thunderbolt: Limit Intel Barlow Ridge USB3 bandwidth
Intel Barlow Ridge discrete USB4 host router has the same limitation as the previous generations so make sure the USB3 bandwidth limitation quirk is applied to Barlow Ridge too. Signed-off-by: Gil Fine <gil.fine@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to '')
-rw-r--r--drivers/thunderbolt/quirks.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/thunderbolt/quirks.c b/drivers/thunderbolt/quirks.c
index 854d84148850..488138a28ae1 100644
--- a/drivers/thunderbolt/quirks.c
+++ b/drivers/thunderbolt/quirks.c
@@ -75,6 +75,14 @@ static const struct tb_quirk tb_quirks[] = {
quirk_usb3_maximum_bandwidth },
{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI1, 0x0000, 0x0000,
quirk_usb3_maximum_bandwidth },
+ { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI, 0x0000, 0x0000,
+ quirk_usb3_maximum_bandwidth },
+ { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI, 0x0000, 0x0000,
+ quirk_usb3_maximum_bandwidth },
+ { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE, 0x0000, 0x0000,
+ quirk_usb3_maximum_bandwidth },
+ { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE, 0x0000, 0x0000,
+ quirk_usb3_maximum_bandwidth },
/*
* CLx is not supported on AMD USB4 Yellow Carp and Pink Sardine platforms.
*/