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authorNitin Rawat <quic_nitirawa@quicinc.com>2023-09-05 07:23:56 +0200
committerMartin K. Petersen <martin.petersen@oracle.com>2023-09-14 03:15:40 +0200
commit07d2290fe80dc9b1b0d066dc2027b84770144e49 (patch)
tree6f3e9b364aef10fb7b8882dd995ae0c2ee97c486 /drivers/ufs/host/ufs-qcom.h
parentLinux 6.6-rc1 (diff)
downloadlinux-07d2290fe80dc9b1b0d066dc2027b84770144e49.tar.xz
linux-07d2290fe80dc9b1b0d066dc2027b84770144e49.zip
scsi: ufs: qcom: Update MAX_CORE_CLK_1US_CYCLES for UFS V4 and above
UFS Controller V4 and above, the register layout for DME_VS_CORE_CLK_CTRL register has changed. MAX_CORE_CLK_1US_CYCLES offset has changed from 0 to 0x10 and length of attrbute is changed from 8bit to 12bit. Add support to configure MAX_CORE_CLK_1US_CYCLES for UFS V4 and above as per new register layout. Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20230905052400.13935-2-quic_nitirawa@quicinc.com Reviewed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/ufs/host/ufs-qcom.h')
-rw-r--r--drivers/ufs/host/ufs-qcom.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index d6f8e74bd538..8a9d3dbec297 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -129,8 +129,9 @@ enum {
#define PA_VS_CONFIG_REG1 0x9000
#define DME_VS_CORE_CLK_CTRL 0xD002
/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
-#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
-#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
+#define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16)
+#define CLK_1US_CYCLES_MASK GENMASK(7, 0)
+#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
static inline void
ufs_qcom_get_controller_revision(struct ufs_hba *hba,