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| author | Sandeep Singh <sandeep.singh@amd.com> | 2020-10-28 21:31:23 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-10-29 08:29:16 +0100 |
| commit | 2a632815683d2d34df52b701a36fe5ac6654e719 (patch) | |
| tree | ffa82e8ca3b13109cda20c276b10c186bc64ce57 /drivers/usb/host/xhci.h | |
| parent | xhci: Fix sizeof() mismatch (diff) | |
| download | linux-2a632815683d2d34df52b701a36fe5ac6654e719.tar.xz linux-2a632815683d2d34df52b701a36fe5ac6654e719.zip | |
usb: xhci: Workaround for S3 issue on AMD SNPS 3.0 xHC
On some platform of AMD, S3 fails with HCE and SRE errors. To fix this,
need to disable a bit which is enable in sparse controller.
Cc: stable@vger.kernel.org #v4.19+
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sandeep Singh <sandeep.singh@amd.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20201028203124.375344-3-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/host/xhci.h')
| -rw-r--r-- | drivers/usb/host/xhci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 8be88379c0fb..ebb359ebb261 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1877,6 +1877,7 @@ struct xhci_hcd { #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) #define XHCI_SKIP_PHY_INIT BIT_ULL(37) +#define XHCI_DISABLE_SPARSE BIT_ULL(38) unsigned int num_active_eps; unsigned int limit_active_eps; |