diff options
| author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2017-10-13 11:10:46 +0200 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2017-10-19 09:38:13 +0200 |
| commit | 4da72e6d2afb24c9cd5707eef7947c2f22dd03fc (patch) | |
| tree | 059750fc27cd098350be497013f0cff167b6b02e /drivers/usb/mtu3 | |
| parent | usb: mtu3: set invalid dr_mode as dual-role mode (diff) | |
| download | linux-4da72e6d2afb24c9cd5707eef7947c2f22dd03fc.tar.xz linux-4da72e6d2afb24c9cd5707eef7947c2f22dd03fc.zip | |
usb: mtu3: set otg_sel for u2port only if works as dual-role mode
When set otg_sel(SSUSB_U2_PORT_OTG_SEL) for u2port which supports
dual-role mode, the controller will automatically switch mode
between host and device according to IDDIG signal. But if the
u2port only supports device mode, and no IDDIG pin is provided,
setting otg_sel may cause failure of detection by host.
So set it only for dual-role mode.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/mtu3')
| -rw-r--r-- | drivers/usb/mtu3/mtu3_core.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c index 67f7a309aba7..7c149a7da14e 100644 --- a/drivers/usb/mtu3/mtu3_core.c +++ b/drivers/usb/mtu3/mtu3_core.c @@ -115,7 +115,9 @@ static int mtu3_device_enable(struct mtu3 *mtu) mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_HOST_SEL)); - mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); + + if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) + mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); return ssusb_check_clocks(mtu->ssusb, check_clk); } @@ -130,7 +132,10 @@ static void mtu3_device_disable(struct mtu3 *mtu) mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN); - mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); + + if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) + mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); + mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); } |