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authorThinh Nguyen <Thinh.Nguyen@synopsys.com>2018-03-16 23:34:07 +0100
committerFelipe Balbi <felipe.balbi@linux.intel.com>2018-03-22 09:48:51 +0100
commit2fbc5bdc8fd1afa6d47223f6a4251f04c7d8fe7c (patch)
tree1399e8ec221878e7b58703b601d28b1e03a6720f /drivers/usb
parentusb: dwc3: Check IP revision for GTXFIFOSIZ (diff)
downloadlinux-2fbc5bdc8fd1afa6d47223f6a4251f04c7d8fe7c.tar.xz
linux-2fbc5bdc8fd1afa6d47223f6a4251f04c7d8fe7c.zip
usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields
Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+----------------------------------+ | BITS | Name | Description | +=======+==========================+==================================+ | 31:27 | reserved | | | 26 | UsbRxPktCntSel | Async ESS receive packet | | | | threshold enable | | 25:21 | UsbRxPktCnt | Async ESS receive packet | | | | threshold count | | 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size | | 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold enable | | 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold count | | 12:11 | reserved | | | 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet | | | | threshold enable | | 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet | | | | threshold count | | 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size | +-------+--------------------------+----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/dwc3/core.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 1ecdc062df58..8c3f28f3eff8 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -178,6 +178,16 @@
#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
+/* Global RX Threshold Configuration Register for DWC_usb31 only */
+#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
+#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
+#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
+#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
+#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
+#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
+#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
+#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
+
/* Global Configuration Register */
#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
#define DWC3_GCTL_U2RSTECN BIT(16)