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authorRaphael Assenat <raph@8d.com>2006-10-03 10:15:03 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-03 17:04:12 +0200
commit8bc218410d6c2b22a7581fac6f3dc2ac1f8fc99f (patch)
treee4b0ef3693052742df0233ab9c3a706382307ee3 /drivers/video/controlfb.c
parent[PATCH] atyfb: Possible cleanups (diff)
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[PATCH] mbxfb: Fix a chip bug? resulting in wrong pixclock
This is a workaround for what I think is a bug in the 2700G chip. The PLL output frequency is adustable using 3 values (M, N and P. See code for formula). The N value range is documented to be 1 to 7 but when it is set to 1, the output frequency is lower than it should be (divided by 2), giving unexpected results such as no sync on a CRT display. This patch prevents N=1 when searching for the best value for the requested pixclock. Signed-off-by: Raphael Assenat <raph@8d.com> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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