diff options
| author | Atish Patra <atish.patra@wdc.com> | 2020-04-03 03:46:09 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-04-17 09:59:28 +0200 |
| commit | d727be7bbf7b68ccc18a3278469325d8f486d75b (patch) | |
| tree | 351489f538a56d684e7f462da3026aee5a4c8710 /drivers | |
| parent | irqchip/ti-sci-inta: Fix processing of masked irqs (diff) | |
| download | linux-d727be7bbf7b68ccc18a3278469325d8f486d75b.tar.xz linux-d727be7bbf7b68ccc18a3278469325d8f486d75b.zip | |
irqchip/sifive-plic: Fix maximum priority threshold value
As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.
Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200403014609.71831-1-atish.patra@wdc.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/irqchip/irq-sifive-plic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index c34fb3ae0ff8..d0a71febdadc 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -56,7 +56,7 @@ #define CONTEXT_THRESHOLD 0x00 #define CONTEXT_CLAIM 0x04 -#define PLIC_DISABLE_THRESHOLD 0xf +#define PLIC_DISABLE_THRESHOLD 0x7 #define PLIC_ENABLE_THRESHOLD 0 struct plic_priv { |