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| author | arun.siluvery@linux.intel.com <arun.siluvery@linux.intel.com> | 2016-06-06 10:52:49 +0200 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-07-15 14:51:21 +0200 |
| commit | f98edb2b6f6baffe0d2be66ebe761b51486c6a40 (patch) | |
| tree | 4b3a372f8a7ac597f83ef57d671457c2b0b14671 /drivers | |
| parent | drm/i915/psr: Implement PSR2 w/a for gen9 (diff) | |
| download | linux-f98edb2b6f6baffe0d2be66ebe761b51486c6a40.tar.xz linux-f98edb2b6f6baffe0d2be66ebe761b51486c6a40.zip | |
drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
Kernel only need to add a register to HW whitelist, required for a
preemption related issue.
Reference: HSD#2131039
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465203169-16591-1-git-send-email-arun.siluvery@linux.intel.com
(cherry picked from commit 6bb6285582e0cf9b3a8440e0e714aae5f66d9ce2)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bb43bb1b953b..7b475047f01b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6070,6 +6070,7 @@ enum skl_disp_power_wells { #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) #define GEN8_CS_CHICKEN1 _MMIO(0x2580) /* GEN7 chicken */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 04402bb9d26b..d8125019e6d9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -992,6 +992,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ + ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); + if (ret) + return ret; + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); if (ret) |