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authormar.krzeminski <mar.krzeminski@gmail.com>2017-01-06 18:19:00 +0100
committerCyrille Pitchen <cyrille.pitchen@atmel.com>2017-03-22 21:52:53 +0100
commit2f5ad7f0f3e16772bafa692ad42b5af4dea292f6 (patch)
tree94bb4a3eca3012df38e0aa553afeeccc4d0e135e /drivers
parentmtd: spi-nor: Add support for ESMT F25L32QA and F25L64QA (diff)
downloadlinux-2f5ad7f0f3e16772bafa692ad42b5af4dea292f6.tar.xz
linux-2f5ad7f0f3e16772bafa692ad42b5af4dea292f6.zip
mtd: spi-nor: Fix whole chip erasing for stacked chips.
Currently it is possible to disable chip erase for spi-nor driver. Some modern stacked (multi die) flash chips do not support chip erase opcode at all but spi-nor framework needs to cope with them too. This commit extends existing functionality to allow disable chip erase for a single flash chip. Signed-off-by: Marcin Krzeminski <mar.krzeminski@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 561e46de8faa..c29a3516bf04 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -85,6 +85,7 @@ struct flash_info {
* Use dedicated 4byte address op codes
* to support memory size above 128Mib.
*/
+#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
};
#define JEDEC_MFR(info) ((info)->id[0])
@@ -1631,6 +1632,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)
nor->flags |= SNOR_F_HAS_SR_TB;
+ if (info->flags & NO_CHIP_ERASE)
+ nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
/* prefer "small sector" erase if possible */