diff options
| author | Matt Redfearn <matt.redfearn@mips.com> | 2017-10-19 13:55:35 +0200 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2017-10-19 23:51:31 +0200 |
| commit | f16ff2bdb135e2eb35488264006b575c476ea597 (patch) | |
| tree | a4962fe25de2b0c1c2a97a5355f4e64f8bbbab68 /drivers | |
| parent | clocksource/drivers/mips-gic-timer: Remove pointless irq_save,restore (diff) | |
| download | linux-f16ff2bdb135e2eb35488264006b575c476ea597.tar.xz linux-f16ff2bdb135e2eb35488264006b575c476ea597.zip | |
clocksource/drivers/mips-gic-timer: Add fastpath for local timer updates
Always accessing the compare register via the CM redirect region is
(relatively) slow. If the timer being updated is the current CPUs
then this can be shortcutted by writing to the CM VP local region.
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clocksource/mips-gic-timer.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 775dea04460d..a04808a21d4e 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -39,13 +39,18 @@ static u64 notrace gic_read_count(void) static int gic_next_event(unsigned long delta, struct clock_event_device *evt) { + int cpu = cpumask_first(evt->cpumask); u64 cnt; int res; cnt = gic_read_count(); cnt += (u64)delta; - write_gic_vl_other(mips_cm_vp_id(cpumask_first(evt->cpumask))); - write_gic_vo_compare(cnt); + if (cpu == raw_smp_processor_id()) { + write_gic_vl_compare(cnt); + } else { + write_gic_vl_other(mips_cm_vp_id(cpu)); + write_gic_vo_compare(cnt); + } res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; return res; } |