diff options
| author | yangbo lu <yangbo.lu@nxp.com> | 2017-08-15 04:17:03 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-08-30 15:03:36 +0200 |
| commit | 2f3110cc89c29a790c8b31c7983603d60b9ede49 (patch) | |
| tree | 808f654d49f64a5a0d1a45675d34668d9613e29e /drivers | |
| parent | mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling (diff) | |
| download | linux-2f3110cc89c29a790c8b31c7983603d60b9ede49.tar.xz linux-2f3110cc89c29a790c8b31c7983603d60b9ede49.zip | |
mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessing
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1
register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1)
for eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/host/sdhci-esdhc.h | 3 | ||||
| -rw-r--r-- | drivers/mmc/host/sdhci-of-esdhc.c | 23 |
2 files changed, 24 insertions, 2 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h index e7893f21b65e..dfa58f8b8dfa 100644 --- a/drivers/mmc/host/sdhci-esdhc.h +++ b/drivers/mmc/host/sdhci-esdhc.h @@ -54,6 +54,9 @@ #define ESDHC_CLOCK_HCKEN 0x00000002 #define ESDHC_CLOCK_IPGEN 0x00000001 +/* Host Controller Capabilities Register 2 */ +#define ESDHC_CAPABILITIES_1 0x114 + /* Tuning Block Control Register */ #define ESDHC_TBCTL 0x120 #define ESDHC_TB_EN 0x00000004 diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 44b016baa585..d96a057a7db8 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -86,6 +86,17 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host, return ret; } + /* + * DTS properties of mmc host are used to enable each speed mode + * according to soc and board capability. So clean up + * SDR50/SDR104/DDR50 support bits here. + */ + if (spec_reg == SDHCI_CAPABILITIES_1) { + ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | + SDHCI_SUPPORT_DDR50); + return ret; + } + ret = value; return ret; } @@ -249,7 +260,11 @@ static u32 esdhc_be_readl(struct sdhci_host *host, int reg) u32 ret; u32 value; - value = ioread32be(host->ioaddr + reg); + if (reg == SDHCI_CAPABILITIES_1) + value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); + else + value = ioread32be(host->ioaddr + reg); + ret = esdhc_readl_fixup(host, reg, value); return ret; @@ -260,7 +275,11 @@ static u32 esdhc_le_readl(struct sdhci_host *host, int reg) u32 ret; u32 value; - value = ioread32(host->ioaddr + reg); + if (reg == SDHCI_CAPABILITIES_1) + value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); + else + value = ioread32(host->ioaddr + reg); + ret = esdhc_readl_fixup(host, reg, value); return ret; |