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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-09-19 20:10:40 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-25 08:56:09 +0200 |
| commit | 9ef5e0370d3834a1ff11e22ae0a3220330890d36 (patch) | |
| tree | a2d7dda20acabcf086acc7ba1b708d2eed9f0a8c /drivers | |
| parent | clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment (diff) | |
| download | linux-9ef5e0370d3834a1ff11e22ae0a3220330890d36.tar.xz linux-9ef5e0370d3834a1ff11e22ae0a3220330890d36.zip | |
clk: renesas: r8a77970: Add TPU clock
The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
Matsushita, it was added in a later BSP version...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 7a85e1adcd94..71341ffa2016 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -127,6 +127,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = { DEF_MOD("cmt2", 301, R8A77970_CLK_R), DEF_MOD("cmt1", 302, R8A77970_CLK_R), DEF_MOD("cmt0", 303, R8A77970_CLK_R), + DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4), DEF_MOD("sd-if", 314, R8A77970_CLK_SD0), DEF_MOD("rwdt", 402, R8A77970_CLK_R), DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), |