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| author | Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> | 2023-08-24 01:43:05 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-09-12 00:24:30 +0200 |
| commit | 55b8ff06a0c70e9a6a1696c69f52c0240167d23f (patch) | |
| tree | 3ac434014c1593457d24cd85254f2ebf8d4e2087 /drivers | |
| parent | PCI/AER: Export pcie_aer_is_native() (diff) | |
| download | linux-55b8ff06a0c70e9a6a1696c69f52c0240167d23f.tar.xz linux-55b8ff06a0c70e9a6a1696c69f52c0240167d23f.zip | |
cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()
Use pcie_aer_is_native() to determine the native AER ownership as the
usage of host_bride->native_aer does not cover command line override of
AER ownership.
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20230823234305.27333-4-Smita.KoralahalliChannabasappa@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/cxl/pci.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 2323169b6e5f..44a21ab7add5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, static int cxl_pci_ras_unmask(struct pci_dev *pdev) { - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 orig_val, val, mask; @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) } /* BIOS has PCIe AER error control */ - if (!host_bridge->native_aer) + if (!pcie_aer_is_native(pdev)) return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); |