diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2023-10-09 15:09:33 +0200 |
|---|---|---|
| committer | Hans Verkuil <hverkuil-cisco@xs4all.nl> | 2023-10-12 09:22:28 +0200 |
| commit | 6f28a427a913370300bf116ad900c17bf3dbbf1c (patch) | |
| tree | 7992c75829c859a093287f4937c9988e2cfeecf1 /drivers | |
| parent | media: cadence: csi2rx: Configure DPHY using link freq (diff) | |
| download | linux-6f28a427a913370300bf116ad900c17bf3dbbf1c.tar.xz linux-6f28a427a913370300bf116ad900c17bf3dbbf1c.zip | |
media: cadence: csi2rx: Soft reset the streams before starting capture
This resets the stream state machines and FIFOs, giving them a clean
slate. On J721E if the streams are not reset before starting the
capture, the captured frame gets wrapped around vertically on every run
after the first.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Tested-by: Julien Massot <julien.massot@collabora.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/media/platform/cadence/cdns-csi2rx.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 77e2413c345a..913f84c341f4 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -40,6 +40,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -134,12 +135,23 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + unsigned int i; + + /* Reset module */ writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } - udelay(10); + usleep_range(10, 20); + /* Clear resets */ writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + for (i = 0; i < csi2rx->max_streams; i++) + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); } static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx) |