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| author | Jisheng Zhang <jszhang@marvell.com> | 2014-09-23 09:42:11 +0200 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2014-10-20 20:50:28 +0200 |
| commit | dfa07141e7a792aecf98a8a99dd40df0bf91bce2 (patch) | |
| tree | e968ed1a94cc71d8e97abe72914a2b4112ba0983 /drivers | |
| parent | devicetree: Add Cadence WDT devicetree bindings documentation (diff) | |
| download | linux-dfa07141e7a792aecf98a8a99dd40df0bf91bce2.tar.xz linux-dfa07141e7a792aecf98a8a99dd40df0bf91bce2.zip | |
watchdog: dw_wdt: initialise TOP_INIT in dw_wdt_set_top()
The TOP_INIT, ie bit 4-7 of the WDOG_TIMEOUT_RANGE_REG_OFFSET register
may be zero, so the timeout period may be very short after initialization
is done, thus the system may be reset soon after enabling. We fix this
problem by also initialising the TOP_INIT when setting TOP in function
dw_wdt_set_top().
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/watchdog/dw_wdt.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index 9f210299de24..449c88523364 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -40,6 +40,7 @@ #define WDOG_CONTROL_REG_OFFSET 0x00 #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 +#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 @@ -106,7 +107,8 @@ static int dw_wdt_set_top(unsigned top_s) } /* Set the new value in the watchdog. */ - writel(top_val, dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); + writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, + dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); dw_wdt_set_next_heartbeat(); |