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| author | Arnd Bergmann <arnd@arndb.de> | 2012-05-16 15:53:24 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-16 15:53:24 +0200 |
| commit | 6d49d53552b60be2caaa853c814662bc4e24428e (patch) | |
| tree | 0cb814af7646e30022d8024fcbf7d8cacdb98f5b /drivers | |
| parent | Merge branch 'samsung/cleanup-plat-s5p' into next/soc2 (diff) | |
| parent | ARM: EXYNOS: Add AUXDATA for i2c controllers (diff) | |
| download | linux-6d49d53552b60be2caaa853c814662bc4e24428e.tar.xz linux-6d49d53552b60be2caaa853c814662bc4e24428e.zip | |
Merge branch 'next/devel-exynos5250-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc2
* 'next/devel-exynos5250-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Add AUXDATA for i2c controllers
ARM: dts: Update device tree source files for EXYNOS5250
ARM: EXYNOS: Add device tree support for interrupt combiner
ARM: EXYNOS: Add irq_domain support for interrupt combiner
ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
ARM: EXYNOS: update irqs for EXYNOS5250 SoC
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
ARM: EXYNOS: add GPC4 bank instance
ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
ARM: EXYNOS: Modify the GIC physical address for static io-mapping
ARM: EXYNOS: Add watchdog timer clock instance
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/gpio-samsung.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index e991d9171961..f88bb9f919a8 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -2454,6 +2454,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = { }, }, { .chip = { + .base = EXYNOS5_GPC4(0), + .ngpio = EXYNOS5_GPIO_C4_NR, + .label = "GPC4", + }, + }, { + .chip = { .base = EXYNOS5_GPD0(0), .ngpio = EXYNOS5_GPIO_D0_NR, .label = "GPD0", @@ -2878,8 +2884,11 @@ static __init int samsung_gpiolib_init(void) goto err_ioremap1; } + /* need to set base address for gpc4 */ + exynos5_gpios_1[11].base = gpio_base1 + 0x2E0; + /* need to set base address for gpx */ - chip = &exynos5_gpios_1[20]; + chip = &exynos5_gpios_1[21]; gpx_base = gpio_base1 + 0xC00; for (i = 0; i < 4; i++, chip++, gpx_base += 0x20) chip->base = gpx_base; |