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authorQuinn Tran <qutran@marvell.com>2021-01-11 10:31:32 +0100
committerMartin K. Petersen <martin.petersen@oracle.com>2021-01-13 06:25:20 +0100
commit044c218b04503858ca4e17f61899c8baa0ae9ba1 (patch)
tree863a2f93194fe5254c08786b9a6bb8ae18e30139 /drivers
parentscsi: qla2xxx: Wait for ABTS response on I/O timeouts for NVMe (diff)
downloadlinux-044c218b04503858ca4e17f61899c8baa0ae9ba1.tar.xz
linux-044c218b04503858ca4e17f61899c8baa0ae9ba1.zip
scsi: qla2xxx: Fix mailbox Ch erroneous error
Mailbox Ch/dump ram extend expects mb register 10 to be set. If not set/clear, firmware can pick up garbage from previous invocation of this mailbox. Example: mctp dump can set mb10. On subsequent flash read which use mailbox cmd Ch, mb10 can retain previous value. Link: https://lore.kernel.org/r/20210111093134.1206-6-njavali@marvell.com Cc: stable@vger.kernel.org Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Quinn Tran <qutran@marvell.com> Signed-off-by: Nilesh Javali <njavali@marvell.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c1
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index bb7431912d41..144a893e7335 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -202,6 +202,7 @@ qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be32 *ram,
wrt_reg_word(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
wrt_reg_word(&reg->mailbox1, LSW(addr));
wrt_reg_word(&reg->mailbox8, MSW(addr));
+ wrt_reg_word(&reg->mailbox10, 0);
wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma)));
wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma)));
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index 629af6fe8c55..06c99963b2c9 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -4291,7 +4291,8 @@ qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
mcp->mb[8] = MSW(addr);
- mcp->out_mb = MBX_8|MBX_0;
+ mcp->mb[10] = 0;
+ mcp->out_mb = MBX_10|MBX_8|MBX_0;
} else {
mcp->mb[0] = MBC_DUMP_RISC_RAM;
mcp->out_mb = MBX_0;