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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-08-25 20:04:18 +0200 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-08-31 17:57:51 +0200 |
| commit | 0dec364ffeb6149aae572ded1e34d4b444c23be6 (patch) | |
| tree | 574c75c06166a8978967d3fd91d6ce608d2fc996 /drivers | |
| parent | dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible (diff) | |
| download | linux-0dec364ffeb6149aae572ded1e34d4b444c23be6.tar.xz linux-0dec364ffeb6149aae572ded1e34d4b444c23be6.zip | |
riscv: dts: microchip: use an mpfs specific l2 compatible
PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:
mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers')
0 files changed, 0 insertions, 0 deletions