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authorStephen Hemminger <shemminger@osdl.org>2005-07-23 01:26:09 +0200
committerJeff Garzik <jgarzik@pobox.com>2005-07-31 06:40:53 +0200
commit4cde06ed0fb58402ec1d6d117122d1058983a393 (patch)
treefcfff6af9aeb40600ef14930fb6f8651ff8b256e /drivers
parent[PATCH] skge: fifo control register access fix (diff)
downloadlinux-4cde06ed0fb58402ec1d6d117122d1058983a393.tar.xz
linux-4cde06ed0fb58402ec1d6d117122d1058983a393.zip
[PATCH] skge: ignore phy interrupts during negotiation
During autonegotiation set PHY interrupt mask to ignore bogus speed change interrupts. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/skge.c6
-rw-r--r--drivers/net/skge.h8
2 files changed, 8 insertions, 6 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index f50405b4fba2..43a275d97107 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -1660,9 +1660,9 @@ static void yukon_init(struct skge_hw *hw, int port)
/* Enable phy interrupt on autonegotiation complete (or link up) */
if (skge->autoneg == AUTONEG_ENABLE)
- gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
+ gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
else
- gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
+ gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
}
static void yukon_reset(struct skge_hw *hw, int port)
@@ -1891,7 +1891,7 @@ static void yukon_link_up(struct skge_port *skge)
reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
gma_write16(hw, port, GM_GP_CTRL, reg);
- gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
+ gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
skge_link_up(skge);
}
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index e2546950bf55..c37214692c07 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -1449,10 +1449,12 @@ enum {
PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
PHY_M_IS_JABBER = 1<<0, /* Jabber */
-};
-#define PHY_M_DEF_MSK ( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
- PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
+ PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
+ PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
+
+ PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
+};
/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
enum {