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| author | Bjorn Helgaas <bhelgaas@google.com> | 2012-12-05 21:51:19 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-12-07 20:10:50 +0100 |
| commit | a875621ec15318f0ba35907726ee2cb9e9e0c6b7 (patch) | |
| tree | 25c8ccf69d97b845bc534b5be498ee0affe429d5 /drivers | |
| parent | iwlwifi: Use standard #defines for PCIe Capability ASPM fields (diff) | |
| download | linux-a875621ec15318f0ba35907726ee2cb9e9e0c6b7.tar.xz linux-a875621ec15318f0ba35907726ee2cb9e9e0c6b7.zip | |
ath9k: Use standard #defines for PCIe Capability ASPM fields
Use the standard #defines for PCIe Capability ASPM fields.
Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but
these are defined for the Linux ASPM interfaces, e.g.,
pci_disable_link_state(), and only coincidentally match the actual register
bits. PCIE_LINK_STATE_CLKPM, also part of that interface, does not match
the register bit.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/pci.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index f088f4bf9a26..71d82078fc7f 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common) if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && (AR_SREV_9285(ah))) { - /* Bluetooth coexistance requires disabling ASPM. */ + /* Bluetooth coexistence requires disabling ASPM. */ pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, - PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); + PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); /* * Both upstream and downstream PCIe components should * have the same ASPM settings. */ pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, - PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); + PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); return; } pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); - if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { + if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { ah->aspm_enabled = true; /* Initialize PCIe PM and SERDES registers. */ ath9k_hw_configpcipowersave(ah, false); |