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| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2020-11-25 11:32:06 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-12-11 15:47:49 +0100 |
| commit | 550c1424acf0123ba0c17e22dfcac92d152b2f0e (patch) | |
| tree | 3cdf4df02fd93b933fd6a588d3a8f95308faf961 /drivers | |
| parent | irqchip/ocelot: Add support for Serval platforms (diff) | |
| download | linux-550c1424acf0123ba0c17e22dfcac92d152b2f0e.tar.xz linux-550c1424acf0123ba0c17e22dfcac92d152b2f0e.zip | |
irqchip/ocelot: Add support for Jaguar2 platforms
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Jaguar2.
Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20201125103206.136498-7-gregory.clement@bootlin.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/irqchip/irq-mscc-ocelot.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c index da5a0ad991a1..8235d98650c1 100644 --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -63,6 +63,17 @@ static struct chip_props luton_props = { .n_irq = 28, }; +static struct chip_props jaguar2_props = { + .flags = FLAGS_HAS_TRIGGER, + .reg_off_sticky = 0x10, + .reg_off_ena = 0x18, + .reg_off_ena_clr = 0x1c, + .reg_off_ena_set = 0x20, + .reg_off_ident = 0x38, + .reg_off_trigger = 0x5c, + .n_irq = 29, +}; + static void ocelot_irq_unmask(struct irq_data *data) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); @@ -197,3 +208,11 @@ static int __init luton_irq_init(struct device_node *node, } IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init); + +static int __init jaguar2_irq_init(struct device_node *node, + struct device_node *parent) +{ + return vcoreiii_irq_init(node, parent, &jaguar2_props); +} + +IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init); |