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| author | Stuart Menefy <stuart.menefy@mathembedded.com> | 2022-09-08 17:52:43 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2022-09-09 13:34:06 +0200 |
| commit | 6463d3930ba5b6addcfc8f80a4543976a2fc7656 (patch) | |
| tree | fd4031740ed857f2cc031b42e709ca5bb1867357 /drivers | |
| parent | drm/meson: Correct OSD1 global alpha value (diff) | |
| download | linux-6463d3930ba5b6addcfc8f80a4543976a2fc7656.tar.xz linux-6463d3930ba5b6addcfc8f80a4543976a2fc7656.zip | |
drm/meson: Fix OSD1 RGB to YCbCr coefficient
VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12,
not 16-28.
Without this the output tends to have a pink hue, changing it results
in better color accuracy.
The vendor kernel doesn't use this register. However the code which
sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. There is a slightly
different style of registers for configuring some of the other matrices,
which do use bits 16-28 for this coefficient, but those have names
ending in MATRIX_COEF22_30, and this is not one of those.
Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com>
Fixes: 728883948b0d ("drm/meson: Add G12A Support for VIU setup")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220908155243.687143-1-stuart.menefy@mathembedded.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_viu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index bb7e109534de..d4b907889a21 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -94,7 +94,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); - writel((m[11] & 0x1fff) << 16, + writel((m[11] & 0x1fff), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), |