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author | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-30 23:38:00 +0100 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-12-07 00:17:26 +0100 |
commit | e3f4358e234edeb8fa28226387026fce72e454c1 (patch) | |
tree | d478758a59ea046c21f4a738f8909cbacf9cf21b /fs/ceph/super.h | |
parent | clk: qcom: Put venus core0/1 gdscs to hw control mode (diff) | |
parent | clk: rockchip: add clock controller for rk1108 (diff) | |
download | linux-e3f4358e234edeb8fa28226387026fce72e454c1.tar.xz linux-e3f4358e234edeb8fa28226387026fce72e454c1.zip |
Merge tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP),
a fix making sure the cpuclk rate is actually valid, before trying to
set it and a copy-paste fix for the rk3399's testclk.
* tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add clock controller for rk1108
dt-bindings: add documentation for rk1108 cru
clk: rockchip: add dt-binding header for rk1108
clk: rockchip: fix copy-paste error in rk3399 testclk
clk: rockchip: validity should be checked prior to cpu clock rate change
Diffstat (limited to 'fs/ceph/super.h')
0 files changed, 0 insertions, 0 deletions