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authorAlan Douglas <adouglas@cadence.com>2018-10-11 18:15:54 +0200
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-10-12 13:09:29 +0200
commite81e36a96bb56f243b5ac1d114c37c086761595b (patch)
tree058ae1c4f9f2d2e7f37f5c27dde6f891edef32b7 /fs/direct-io.c
parentPCI: cadence: Use AXI region 0 to signal interrupts from EP (diff)
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PCI: cadence: Write MSI data with 32bits
According to the PCIe specification, although the MSI data is only 16bits, the upper 16bits should be written as 0. Use writel instead of writew when writing the MSI data to the host. Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller") Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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