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authorRay Jui <ray.jui@broadcom.com>2016-05-05 18:32:01 +0200
committerMarc Zyngier <marc.zyngier@arm.com>2016-05-11 11:12:40 +0200
commit74c967aaffeace8a85fc3d7be773fd165ebde3da (patch)
treefa5521306234946e8b36ed813743ead5575e2ce6 /fs/xfs/xfs_itable.c
parentirqchip/irq-alpine-msi: Don't use <asm-generic/msi.h> (diff)
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irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum
Alex Barba <alex.barba@broadcom.com> discovered Broadcom NS2 GICv2m implementation has an erratum where the MSI data needs to be the SPI number subtracted by an offset of 32, for the correct MSI interrupt to be triggered. Here we are adding the workaround based on readings from the MSI_IIDR register, which contains a value unique to Broadcom NS2 GICv2m Reported-by: Alex Barba <alex.barba@broadcom.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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