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| author | Jeff Garzik <jeff@garzik.org> | 2006-09-26 19:13:19 +0200 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-09-26 19:13:19 +0200 |
| commit | c226951b93f7cd7c3a10b17384535b617bd43fd0 (patch) | |
| tree | 07b8796a5c99fbbf587b8d0dbcbc173cfe5e381e /include/asm-avr32/arch-at32ap/at91rm9200_pdc.h | |
| parent | Merge branch 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/linv... (diff) | |
| parent | [PATCH] s390: fix cmm kernel thread handling (diff) | |
| download | linux-c226951b93f7cd7c3a10b17384535b617bd43fd0.tar.xz linux-c226951b93f7cd7c3a10b17384535b617bd43fd0.zip | |
Merge branch 'master' into upstream
Diffstat (limited to 'include/asm-avr32/arch-at32ap/at91rm9200_pdc.h')
| -rw-r--r-- | include/asm-avr32/arch-at32ap/at91rm9200_pdc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h b/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h new file mode 100644 index 000000000000..ce1150d4438d --- /dev/null +++ b/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h @@ -0,0 +1,36 @@ +/* + * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Peripheral Data Controller (PDC) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_PDC_H +#define AT91RM9200_PDC_H + +#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ +#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ +#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ +#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ +#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ +#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ +#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ +#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ + +#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ +#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ +#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ +#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ +#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ + +#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ + +#endif |