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authorBryan Wu <bryan.wu@analog.com>2007-10-10 18:30:56 +0200
committerBryan Wu <bryan.wu@analog.com>2007-10-10 18:30:56 +0200
commit1d487f468de75b8a5c664db60e106935f9dc753b (patch)
tree4b610ba2550b997893250ace494e94cc07f66e5d /include/asm-blackfin/mach-bf537
parentBlackfin arch: modify the insX/outsX and dma_insX/dma_outsX to be compatible ... (diff)
downloadlinux-1d487f468de75b8a5c664db60e106935f9dc753b.tar.xz
linux-1d487f468de75b8a5c664db60e106935f9dc753b.zip
Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index dce4c543a339..d0d80d3152ba 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -86,6 +86,7 @@
#define UART0_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -456,6 +457,7 @@
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define TWI0_REGBASE 0xFFC01400
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */