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| author | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-10-21 17:45:58 +0200 |
|---|---|---|
| committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-10-29 17:29:44 +0100 |
| commit | 556dcee7b829e5c350c3ffdbdb87a8b15aa3c5d3 (patch) | |
| tree | 26485b0d92eedcba6c0c96d4069469041aaf7106 /include/asm-cris | |
| parent | Merge branch 'for-next' of git://www.jni.nu/cris into cris_merge (diff) | |
| download | linux-556dcee7b829e5c350c3ffdbdb87a8b15aa3c5d3.tar.xz linux-556dcee7b829e5c350c3ffdbdb87a8b15aa3c5d3.zip | |
[CRIS] Move header files from include to arch/cris/include.
Change all users of header files to correct path.
Remove some unneeded headers for arch-v32.
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'include/asm-cris')
310 files changed, 0 insertions, 64047 deletions
diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild deleted file mode 100644 index d5b631935ec8..000000000000 --- a/include/asm-cris/Kbuild +++ /dev/null @@ -1,11 +0,0 @@ -include include/asm-generic/Kbuild.asm - -header-y += arch-v10/ -header-y += arch-v32/ - -header-y += ethernet.h -header-y += rtc.h -header-y += sync_serial.h - -unifdef-y += etraxgpio.h -unifdef-y += rs485.h diff --git a/include/asm-cris/arch-v10/Kbuild b/include/asm-cris/arch-v10/Kbuild deleted file mode 100644 index 7a192e1290b1..000000000000 --- a/include/asm-cris/arch-v10/Kbuild +++ /dev/null @@ -1,4 +0,0 @@ -header-y += user.h -header-y += svinto.h -header-y += sv_addr_ag.h -header-y += sv_addr.agh diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h deleted file mode 100644 index 6ef5e7d09024..000000000000 --- a/include/asm-cris/arch-v10/atomic.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_ATOMIC__ -#define __ASM_CRIS_ARCH_ATOMIC__ - -#define cris_atomic_save(addr, flags) local_irq_save(flags); -#define cris_atomic_restore(addr, flags) local_irq_restore(flags); - -#endif diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h deleted file mode 100644 index be85f6de25d3..000000000000 --- a/include/asm-cris/arch-v10/bitops.h +++ /dev/null @@ -1,73 +0,0 @@ -/* asm/arch/bitops.h for Linux/CRISv10 */ - -#ifndef _CRIS_ARCH_BITOPS_H -#define _CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions, wrapping the - * syntactically awkward asms. The asms compute the number of leading - * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped - * number. They differ in that the first function also inverts all bits - * in the input. - */ -static inline unsigned long cris_swapnwbrlz(unsigned long w) -{ - /* Let's just say we return the result in the same register as the - input. Saying we clobber the input but can return the result - in another register: - ! __asm__ ("swapnwbr %2\n\tlz %2,%0" - ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); - confuses gcc (sched.c, gcc from cris-dist-1.14). */ - - unsigned long res; - __asm__ ("swapnwbr %0 \n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - return res; -} - -static inline unsigned long cris_swapwbrlz(unsigned long w) -{ - unsigned res; - __asm__ ("swapwbr %0 \n\t" - "lz %0,%0" - : "=r" (res) - : "0" (w)); - return res; -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/** - * __ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline unsigned long __ffs(unsigned long word) -{ - return cris_swapnwbrlz(~word); -} - -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -static inline unsigned long kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif diff --git a/include/asm-cris/arch-v10/bug.h b/include/asm-cris/arch-v10/bug.h deleted file mode 100644 index 3485d6b34bb0..000000000000 --- a/include/asm-cris/arch-v10/bug.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __ASM_CRISv10_ARCH_BUG_H -#define __ASM_CRISv10_ARCH_BUG_H - -#include <linux/stringify.h> - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -/* The BUG() macro is used for marking obviously incorrect code paths. - * It will cause a message with the file name and line number to be printed, - * and then cause an oops. The message is actually printed by handle_BUG() - * in arch/cris/kernel/traps.c, and the reason we use this method of storing - * the file name and line number is that we do not want to affect the registers - * by calling printk() before causing the oops. - */ - -#define BUG_PREFIX 0x0D7F -#define BUG_MAGIC 0x00001234 - -struct bug_frame { - unsigned short prefix; - unsigned int magic; - unsigned short clear; - unsigned short movu; - unsigned short line; - unsigned short jump; - unsigned char *filename; -}; - -#if 0 -/* Unfortunately this version of the macro does not work due to a problem - * with the compiler (aka a bug) when compiling with -O2, which sometimes - * erroneously causes the second input to be stored in a register... - */ -#define BUG() \ - __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ - "movu.w %0,$r0\n\t" \ - "jump %1\n\t" \ - : : "i" (__LINE__), "i" (__FILE__)) -#else -/* This version will have to do for now, until the compiler is fixed. - * The drawbacks of this version are that the file name will appear multiple - * times in the .rodata section, and that __LINE__ and __FILE__ can probably - * not be used like this with newer versions of gcc. - */ -#define BUG() \ - __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ - "movu.w " __stringify(__LINE__) ",$r0\n\t"\ - "jump 0f\n\t" \ - ".section .rodata\n" \ - "0:\t.string \"" __FILE__ "\"\n\t" \ - ".previous") -#endif - -#else - -/* This just causes an oops. */ -#define BUG() (*(int *)0 = 0) - -#endif - -#define HAVE_ARCH_BUG -#endif - -#include <asm-generic/bug.h> - -#endif diff --git a/include/asm-cris/arch-v10/byteorder.h b/include/asm-cris/arch-v10/byteorder.h deleted file mode 100644 index 255b646b7fa8..000000000000 --- a/include/asm-cris/arch-v10/byteorder.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _CRIS_ARCH_BYTEORDER_H -#define _CRIS_ARCH_BYTEORDER_H - -#include <asm/types.h> -#include <linux/compiler.h> - -/* we just define these two (as we can do the swap in a single - * asm instruction in CRIS) and the arch-independent files will put - * them together into ntohl etc. - */ - -static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); - - return(x); -} - -static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - __asm__ ("swapb %0" : "=r" (x) : "0" (x)); - - return(x); -} - -#endif diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h deleted file mode 100644 index aea27184d2d2..000000000000 --- a/include/asm-cris/arch-v10/cache.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASM_ARCH_CACHE_H -#define _ASM_ARCH_CACHE_H - -/* Etrax 100LX have 32-byte cache-lines. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 - -#endif /* _ASM_ARCH_CACHE_H */ diff --git a/include/asm-cris/arch-v10/checksum.h b/include/asm-cris/arch-v10/checksum.h deleted file mode 100644 index b8000c5d7fe1..000000000000 --- a/include/asm-cris/arch-v10/checksum.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _CRIS_ARCH_CHECKSUM_H -#define _CRIS_ARCH_CHECKSUM_H - -/* Checksum some values used in TCP/UDP headers. - * - * The gain by doing this in asm is that C will not generate carry-additions - * for the 32-bit components of the checksum, so otherwise we would have had - * to split all of those into 16-bit components, then add. - */ - -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, - unsigned short proto, __wsum sum) -{ - __wsum res; - __asm__ ("add.d %2, %0\n\t" - "ax\n\t" - "add.d %3, %0\n\t" - "ax\n\t" - "add.d %4, %0\n\t" - "ax\n\t" - "addq 0, %0\n" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8)); - - return res; -} - -#endif diff --git a/include/asm-cris/arch-v10/delay.h b/include/asm-cris/arch-v10/delay.h deleted file mode 100644 index 39481f6e0c30..000000000000 --- a/include/asm-cris/arch-v10/delay.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _CRIS_ARCH_DELAY_H -#define _CRIS_ARCH_DELAY_H - -static inline void __delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0,$r9\n\t" - "beq 2f\n\t" - "subq 1,$r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1,$r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* defined(_CRIS_ARCH_DELAY_H) */ - - - diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h deleted file mode 100644 index ecb9dba6fa4f..000000000000 --- a/include/asm-cris/arch-v10/dma.h +++ /dev/null @@ -1,74 +0,0 @@ -/* Defines for using and allocating dma channels. */ - -#ifndef _ASM_ARCH_DMA_H -#define _ASM_ARCH_DMA_H - -#define MAX_DMA_CHANNELS 10 - -/* dma0 and dma1 used for network (ethernet) */ -#define NETWORK_TX_DMA_NBR 0 -#define NETWORK_RX_DMA_NBR 1 - -/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ -#define PAR0_TX_DMA_NBR 2 -#define PAR0_RX_DMA_NBR 3 -#define SCSI0_TX_DMA_NBR 2 -#define SCSI0_RX_DMA_NBR 3 -#define SER2_TX_DMA_NBR 2 -#define SER2_RX_DMA_NBR 3 -#define ATA_TX_DMA_NBR 2 -#define ATA_RX_DMA_NBR 3 - -/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ -#define PAR1_TX_DMA_NBR 4 -#define PAR1_RX_DMA_NBR 5 -#define SCSI1_TX_DMA_NBR 4 -#define SCSI1_RX_DMA_NBR 5 -#define SER3_TX_DMA_NBR 4 -#define SER3_RX_DMA_NBR 5 -#define EXTDMA0_TX_DMA_NBR 4 -#define EXTDMA0_RX_DMA_NBR 5 - -/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ -#define SER0_TX_DMA_NBR 6 -#define SER0_RX_DMA_NBR 7 -#define EXTDMA1_TX_DMA_NBR 6 -#define EXTDMA1_RX_DMA_NBR 7 -#define MEM2MEM_TX_DMA_NBR 6 -#define MEM2MEM_RX_DMA_NBR 7 - -/* dma8 and dma9 shared by ser1 and usb */ -#define SER1_TX_DMA_NBR 8 -#define SER1_RX_DMA_NBR 9 -#define USB_TX_DMA_NBR 8 -#define USB_RX_DMA_NBR 9 - -#endif - -enum dma_owner -{ - dma_eth, - dma_ser0, - dma_ser1, /* Async and sync */ - dma_ser2, - dma_ser3, /* Async and sync */ - dma_ata, - dma_par0, - dma_par1, - dma_ext0, - dma_ext1, - dma_int6, - dma_int7, - dma_usb, - dma_scsi0, - dma_scsi1 -}; - -/* Masks used by cris_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR (1<<0) -#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) - -int cris_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, enum dma_owner owner); - -void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h deleted file mode 100644 index 1c38ee728b17..000000000000 --- a/include/asm-cris/arch-v10/elf.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef __ASMCRIS_ARCH_ELF_H -#define __ASMCRIS_ARCH_ELF_H - -#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* - * ELF register definitions.. - */ - -#include <asm/ptrace.h> - -/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program - starts (a register; assume first param register for CRIS) - contains a pointer to a function which might be - registered using `atexit'. This provides a mean for the - dynamic linker to call DT_FINI functions for shared libraries - that have been loaded before the code runs. - - A value of 0 tells we have no such handler. */ - -/* Explicitly set registers to 0 to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ -} while (0) - -/* The additional layer below is because the stack pointer is missing in - the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, - and should be filled in according to the layout of the user_regs_struct - struct; regs is a pt_regs struct. We dump all registers, though several are - obviously unnecessary. That way there's less need for intelligence at - the receiving end (i.e. gdb). */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* sp */ \ - pr_reg[15] = regs->irp; /* pc */ \ - pr_reg[16] = 0; /* p0 */ \ - pr_reg[17] = rdvr(); /* vr */ \ - pr_reg[18] = 0; /* p2 */ \ - pr_reg[19] = 0; /* p3 */ \ - pr_reg[20] = 0; /* p4 */ \ - pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ - pr_reg[22] = 0; /* p6 */ \ - pr_reg[23] = regs->mof; /* mof */ \ - pr_reg[24] = 0; /* p8 */ \ - pr_reg[25] = 0; /* ibr */ \ - pr_reg[26] = 0; /* irp */ \ - pr_reg[27] = regs->srp; /* srp */ \ - pr_reg[28] = 0; /* bar */ \ - pr_reg[29] = regs->dccr; /* dccr */ \ - pr_reg[30] = 0; /* brp */ \ - pr_reg[31] = rdusp(); /* usp */ \ - pr_reg[32] = 0; /* csrinstr */ \ - pr_reg[33] = 0; /* csraddr */ \ - pr_reg[34] = 0; /* csrdata */ - - -#endif diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h deleted file mode 100644 index c08c24265299..000000000000 --- a/include/asm-cris/arch-v10/io.h +++ /dev/null @@ -1,199 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_IO_H -#define _ASM_ARCH_CRIS_IO_H - -#include <asm/arch/svinto.h> - -/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ - -extern unsigned long gen_config_ii_shadow; -extern unsigned long port_g_data_shadow; -extern unsigned char port_pa_dir_shadow; -extern unsigned char port_pa_data_shadow; -extern unsigned char port_pb_i2c_shadow; -extern unsigned char port_pb_config_shadow; -extern unsigned char port_pb_dir_shadow; -extern unsigned char port_pb_data_shadow; -extern unsigned long r_timer_ctrl_shadow; - -extern unsigned long port_cse1_shadow; -extern unsigned long port_csp0_shadow; -extern unsigned long port_csp4_shadow; - -extern volatile unsigned long *port_cse1_addr; -extern volatile unsigned long *port_csp0_addr; -extern volatile unsigned long *port_csp4_addr; - -/* macro for setting regs through a shadow - - * r = register name (like R_PORT_PA_DATA) - * s = shadow name (like port_pa_data_shadow) - * b = bit number - * v = value (0 or 1) - */ - -#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) - -/* The LED's on various Etrax-based products are set differently. */ - -#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM) -#undef CONFIG_ETRAX_PA_LEDS -#undef CONFIG_ETRAX_PB_LEDS -#undef CONFIG_ETRAX_CSP0_LEDS -#define CRIS_LED_NETWORK_SET_G(x) -#define CRIS_LED_NETWORK_SET_R(x) -#define CRIS_LED_ACTIVE_SET_G(x) -#define CRIS_LED_ACTIVE_SET_R(x) -#define CRIS_LED_DISK_WRITE(x) -#define CRIS_LED_DISK_READ(x) -#endif - -#if !defined(CONFIG_ETRAX_CSP0_LEDS) -#define CRIS_LED_BIT_SET(x) -#define CRIS_LED_BIT_CLR(x) -#endif - -#define CRIS_LED_OFF 0x00 -#define CRIS_LED_GREEN 0x01 -#define CRIS_LED_RED 0x02 -#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) - -#if defined(CONFIG_ETRAX_NO_LEDS) -#define CRIS_LED_NETWORK_SET(x) -#else -#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R -#define CRIS_LED_NETWORK_SET(x) \ - do { \ - CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ - } while (0) -#else -#define CRIS_LED_NETWORK_SET(x) \ - do { \ - CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#endif -#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - } while (0) -#else -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#endif -#endif - -#ifdef CONFIG_ETRAX_PA_LEDS -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ - CONFIG_ETRAX_LED3G, !(x)) -#endif - -#ifdef CONFIG_ETRAX_PB_LEDS -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ - CONFIG_ETRAX_LED3G, !(x)) -#endif - -#ifdef CONFIG_ETRAX_CSP0_LEDS -#define CONFIGURABLE_LEDS\ - ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ - (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ - (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ - (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ - (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ - (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ - (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ - (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ - (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ - (1 << CONFIG_ETRAX_LED12R )) - -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) -#define CRIS_LED_BIT_SET(x)\ - do{\ - if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ - }while(0) -#define CRIS_LED_BIT_CLR(x)\ - do{\ - if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ - }while(0) -#endif - -# -#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN -#define SOFT_SHUTDOWN() \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) -#else -#define SOFT_SHUTDOWN() -#endif - -/* Console I/O for simulated etrax100. Use #ifdef so erroneous - use will be evident. */ -#ifdef CONFIG_SVINTO_SIM - /* Let's use the ucsim interface since it lets us do write(2, ...) */ -#define SIMCOUT(s,len) \ - asm ("moveq 4,$r9 \n\t" \ - "moveq 2,$r10 \n\t" \ - "move.d %0,$r11 \n\t" \ - "move.d %1,$r12 \n\t" \ - "push $irp \n\t" \ - "move 0f,$irp \n\t" \ - "jump -6809 \n" \ - "0: \n\t" \ - "pop $irp" \ - : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory") -#define TRACE_ON() __extension__ \ - ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \ - (255)); _Foofoo; }) - -#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0) -#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0) -#define CRIS_CYCLES() __extension__ \ - ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;}) -#endif /* ! defined CONFIG_SVINTO_SIM */ - -#endif diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h deleted file mode 100644 index d92500080883..000000000000 --- a/include/asm-cris/arch-v10/io_interface_mux.h +++ /dev/null @@ -1,75 +0,0 @@ -/* IO interface mux allocator for ETRAX100LX. - * Copyright 2004, Axis Communications AB - * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ - */ - - -#ifndef _IO_INTERFACE_MUX_H -#define _IO_INTERFACE_MUX_H - - -/* C.f. ETRAX100LX Designer's Reference 20.9 */ - -/* The order in enum must match the order of interfaces[] in - * io_interface_mux.c */ -enum cris_io_interface { - /* Begin Non-multiplexed interfaces */ - if_eth = 0, - if_serial_0, - /* End Non-multiplexed interfaces */ - if_serial_1, - if_serial_2, - if_serial_3, - if_sync_serial_1, - if_sync_serial_3, - if_shared_ram, - if_shared_ram_w, - if_par_0, - if_par_1, - if_par_w, - if_scsi8_0, - if_scsi8_1, - if_scsi_w, - if_ata, - if_csp, - if_i2c, - if_usb_1, - if_usb_2, - /* GPIO pins */ - if_gpio_grp_a, - if_gpio_grp_b, - if_gpio_grp_c, - if_gpio_grp_d, - if_gpio_grp_e, - if_gpio_grp_f, - if_max_interfaces, - if_unclaimed -}; - -int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); - -void cris_free_io_interface(enum cris_io_interface ioif); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_free_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -#endif /* _IO_INTERFACE_MUX_H */ diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h deleted file mode 100644 index b1128a9984ae..000000000000 --- a/include/asm-cris/arch-v10/irq.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Interrupt handling assembler and defines for Linux/CRISv10 - */ - -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include <asm/arch/sv_addr_ag.h> - -#define NR_IRQS 32 - -/* The first vector number used for IRQs in v10 is really 0x20 */ -/* but all the code and constants are offseted to make 0 the first */ -#define FIRST_IRQ 0 - -#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ -#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ -#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ -#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ -/* mio, ata, par0, scsi0 on 4 */ -/* par1, scsi1 on 5 */ -#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ - -#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ -#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ -/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ -#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) -#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) - -/* dma0-9 is irq 16..25 */ -/* 16,17: network */ -#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) -#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) -#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR -#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR - -/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ -#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) -#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) -#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR -#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR - -/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ -#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) -#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) -#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR -#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR - -/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ -#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) -#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) -#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR -#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR -#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR -#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR - -/* 24,25: dma8 and dma9 shared by ser1 and usb */ -#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) -#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) -#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR -#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR -#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR -#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR - -/* usb: controller at irq 31 + uses DMA8 and DMA9 */ -#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) - -/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ - -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; -void set_int_vector(int n, irqvectptr addr); -void set_break_vector(int n, irqvectptr addr); - -#define __STR(x) #x -#define STR(x) __STR(x) - -/* SAVE_ALL saves registers so they match pt_regs */ - -#define SAVE_ALL \ - "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ - "push $srp\n\t" /* push subroutine return pointer */ \ - "push $dccr\n\t" /* push condition codes */ \ - "push $mof\n\t" /* push multiply overflow reg */ \ - "di\n\t" /* need to disable irq's at this point */\ - "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ - "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ - "push $r10\n\t" /* push orig_r10 */ \ - "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ - - /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */ - -#define BLOCK_IRQ(mask,nr) \ - "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000d8]\n\t" - -#define UNBLOCK_IRQ(mask) \ - "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000dc]\n\t" - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) -#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) -#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) - - /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls - * do_IRQ (with irq disabled still). after that it unblocks and jumps to - * ret_from_intr (entry.S) - * - * The reason the IRQ is blocked is to allow an sti() before the handler which - * will acknowledge the interrupt is run. - */ - -#define BUILD_IRQ(nr,mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ - "moveq "#nr",$r10\n\t" \ - "move.d $sp,$r11\n\t" \ - "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ - UNBLOCK_IRQ(mask) \ - "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); - -/* This is subtle. The timer interrupt is crucial and it should not be disabled for - * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would - * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. - * If the softirq's take too much time to run, the timer irq won't run and the - * watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq - * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed - * it here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt is - * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not - * be an sti() before the timer irq handler is run to acknowledge the interrupt. - */ - -#define BUILD_TIMER_IRQ(nr,mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - "moveq "#nr",$r10\n\t" \ - "move.d $sp,$r11\n\t" \ - "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ - "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); - -#endif diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h deleted file mode 100644 index 13f3b971407f..000000000000 --- a/include/asm-cris/arch-v10/memmap.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h deleted file mode 100644 index df84f1716e6b..000000000000 --- a/include/asm-cris/arch-v10/mmu.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * CRIS MMU constants and PTE layout - */ - -#ifndef _CRIS_ARCH_MMU_H -#define _CRIS_ARCH_MMU_H - -/* type used in struct mm to couple an MMU context to an active mm */ - -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* kernel memory segments */ - -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* CRIS PTE bits (see R_TLB_LO in the register description) - * - * Bit: 31-13 12-------4 3 2 1 0 - * ________________________________________________ - * | pfn | reserved | global | valid | kernel | we | - * |_____|__________|________|_______|________|_____| - * - * (pfn = physical frame number) - */ - -/* Real HW-based PTE bits. We use some synonym names so that - * things become less confusing in combination with the SW-based - * bits further below. - * - */ - -#define _PAGE_WE (1<<0) /* page is write-enabled */ -#define _PAGE_SILENT_WRITE (1<<0) /* synonym */ -#define _PAGE_KERNEL (1<<1) /* page is kernel only */ -#define _PAGE_VALID (1<<2) /* page is valid */ -#define _PAGE_SILENT_READ (1<<2) /* synonym */ -#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ - -/* Bits the HW doesn't care about but the kernel uses them in SW */ - -#define _PAGE_PRESENT (1<<4) /* page present in memory */ -#define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */ -#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ -#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ -#define _PAGE_READ (1<<7) /* read-enabled */ -#define _PAGE_WRITE (1<<8) /* write-enabled */ - -/* Define some higher level generic page attributes. */ - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* - * CRIS can't do page protection for execute, and considers read the same. - * Also, write permissions imply read permissions. This is the closest we can - * get.. - */ - -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED - -#define PTE_FILE_MAX_BITS 26 - -#endif diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h deleted file mode 100644 index 675b51d85639..000000000000 --- a/include/asm-cris/arch-v10/offset.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 8 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 12 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 16 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 20 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 24 /* offsetof(struct pt_regs, r9) */ -#define PT_mof 64 /* offsetof(struct pt_regs, mof) */ -#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ -#define PT_srp 72 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ - -#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h deleted file mode 100644 index ffafc99c3472..000000000000 --- a/include/asm-cris/arch-v10/page.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _CRIS_ARCH_PAGE_H -#define _CRIS_ARCH_PAGE_H - - -#ifdef __KERNEL__ - -/* This handles the memory map.. */ -#ifdef CONFIG_CRIS_LOW_MAP -#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ -#else -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ -#endif - -/* macros to convert between really physical and virtual addresses - * by stripping a selected bit, we can convert between KSEG_x and - * 0x40000000 where the DRAM really resides - */ - -#ifdef CONFIG_CRIS_LOW_MAP -/* we have DRAM virtually at 0x6 */ -#define __pa(x) ((unsigned long)(x) & 0xdfffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) -#else -/* we have DRAM virtually at 0xc */ -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) -#endif - -#endif -#endif diff --git a/include/asm-cris/arch-v10/pgtable.h b/include/asm-cris/arch-v10/pgtable.h deleted file mode 100644 index 2a2576d1fc97..000000000000 --- a/include/asm-cris/arch-v10/pgtable.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _CRIS_ARCH_PGTABLE_H -#define _CRIS_ARCH_PGTABLE_H - -/* - * Kernels own virtual memory area. - */ - -#ifdef CONFIG_CRIS_LOW_MAP -#define VMALLOC_START KSEG_7 -#define VMALLOC_END KSEG_8 -#else -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#endif - -#endif - diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h deleted file mode 100644 index cc692c7a0660..000000000000 --- a/include/asm-cris/arch-v10/processor.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_PROCESSOR_H -#define __ASM_CRIS_ARCH_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) - -/* CRIS has no problems with write protection */ -#define wp_works_ok 1 - -/* CRIS thread_struct. this really has nothing to do with the processor itself, since - * CRIS does not do any hardware task-switching, but it's here for legacy reasons. - * The thread_struct here is used when task-switching using _resume defined in entry.S. - * The offsets here are hardcoded into _resume - if you change this struct, you need to - * change them as well!!! -*/ - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned long dccr; /* saved flag register */ -}; - -/* - * User space process size. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ - -#ifdef CONFIG_CRIS_LOW_MAP -#define TASK_SIZE (0x50000000UL) /* 1.25 GB */ -#else -#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ -#endif - -#define INIT_THREAD { \ - 0, 0, 0x20 } /* ccr = int enable, nothing else */ - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)task_pt_regs(tsk); \ - if (regs > PAGE_SIZE && \ - virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->irp; \ - eip; \ -}) - -/* give the thread a program location - * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) - * switch user-stackpointer - */ - -#define start_thread(regs, ip, usp) do { \ - set_fs(USER_DS); \ - regs->irp = ip; \ - regs->dccr |= 1 << U_DCCR_BITNR; \ - wrusp(usp); \ -} while(0) - -/* Called when handling a kernel bus fault fixup. - * - * After a fixup we do not want to return by restoring the CPU-state - * anymore, so switch frame-types (see ptrace.h) - */ -#define arch_fixup(regs) \ - regs->frametype = CRIS_FRAME_NORMAL; - -#endif diff --git a/include/asm-cris/arch-v10/ptrace.h b/include/asm-cris/arch-v10/ptrace.h deleted file mode 100644 index 2f464eab3a51..000000000000 --- a/include/asm-cris/arch-v10/ptrace.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Frame types */ - -#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ -#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return - path */ - -/* Register numbers in the ptrace system call interface */ - -#define PT_FRAMETYPE 0 -#define PT_ORIG_R10 1 -#define PT_R13 2 -#define PT_R12 3 -#define PT_R11 4 -#define PT_R10 5 -#define PT_R9 6 -#define PT_R8 7 -#define PT_R7 8 -#define PT_R6 9 -#define PT_R5 10 -#define PT_R4 11 -#define PT_R3 12 -#define PT_R2 13 -#define PT_R1 14 -#define PT_R0 15 -#define PT_MOF 16 -#define PT_DCCR 17 -#define PT_SRP 18 -#define PT_IRP 19 /* This is actually the debugged process' PC */ -#define PT_CSRINSTR 20 /* CPU Status record remnants - - valid if frametype == busfault */ -#define PT_CSRADDR 21 -#define PT_CSRDATA 22 -#define PT_USP 23 /* special case - USP is not in the pt_regs */ -#define PT_MAX 23 - -/* Condition code bit numbers. The same numbers apply to CCR of course, - but we use DCCR everywhere else, so let's try and be consistent. */ -#define C_DCCR_BITNR 0 -#define V_DCCR_BITNR 1 -#define Z_DCCR_BITNR 2 -#define N_DCCR_BITNR 3 -#define X_DCCR_BITNR 4 -#define I_DCCR_BITNR 5 -#define B_DCCR_BITNR 6 -#define M_DCCR_BITNR 7 -#define U_DCCR_BITNR 8 -#define P_DCCR_BITNR 9 -#define F_DCCR_BITNR 10 - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long frametype; /* type of stackframe */ - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ - unsigned long r13; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long mof; - unsigned long dccr; - unsigned long srp; - unsigned long irp; /* This is actually the debugged process' PC */ - unsigned long csrinstr; - unsigned long csraddr; - unsigned long csrdata; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -/* bit 8 is user-mode flag */ -#define user_mode(regs) (((regs)->dccr & 0x100) != 0) -#define instruction_pointer(regs) ((regs)->irp) -#define profile_pc(regs) instruction_pointer(regs) -extern void show_regs(struct pt_regs *); - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/arch-v10/sv_addr.agh b/include/asm-cris/arch-v10/sv_addr.agh deleted file mode 100644 index 6ac3a7bc9760..000000000000 --- a/include/asm-cris/arch-v10/sv_addr.agh +++ /dev/null @@ -1,7306 +0,0 @@ -/* -!* This file was automatically generated by /n/asic/bin/reg_macro_gen -!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. -!* Editing within this file is thus not recommended, -!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. -!*/ - - -/* -!* Bus interface configuration registers -!*/ - -#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_zw__WIDTH 2 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_ew__WIDTH 2 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__sram_lw__WIDTH 4 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_zw__WIDTH 2 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_ew__WIDTH 2 -#define R_WAITSTATES__flash_lw__BITNR 0 -#define R_WAITSTATES__flash_lw__WIDTH 4 - -#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__sram_type__WIDTH 1 -#define R_BUS_CONFIG__sram_type__cwe 1 -#define R_BUS_CONFIG__sram_type__bwe 0 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__dma_burst__WIDTH 1 -#define R_BUS_CONFIG__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__sram_wr__WIDTH 1 -#define R_BUS_CONFIG__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__flash_wr__WIDTH 1 -#define R_BUS_CONFIG__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__sram_bw__WIDTH 1 -#define R_BUS_CONFIG__sram_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__BITNR 0 -#define R_BUS_CONFIG__flash_bw__WIDTH 1 -#define R_BUS_CONFIG__flash_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__bw16 0 - -#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 -#define R_BUS_STATUS__pll_lock_tm__expired 0 -#define R_BUS_STATUS__pll_lock_tm__counting 1 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__both_faults__WIDTH 1 -#define R_BUS_STATUS__both_faults__no 0 -#define R_BUS_STATUS__both_faults__yes 1 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__bsen___WIDTH 1 -#define R_BUS_STATUS__bsen___enable 0 -#define R_BUS_STATUS__bsen___disable 1 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__boot__WIDTH 2 -#define R_BUS_STATUS__boot__uncached 0 -#define R_BUS_STATUS__boot__serial 1 -#define R_BUS_STATUS__boot__network 2 -#define R_BUS_STATUS__boot__parallel 3 -#define R_BUS_STATUS__flashw__BITNR 0 -#define R_BUS_STATUS__flashw__WIDTH 1 -#define R_BUS_STATUS__flashw__bw32 1 -#define R_BUS_STATUS__flashw__bw16 0 - -#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__sdram__WIDTH 1 -#define R_DRAM_TIMING__sdram__enable 1 -#define R_DRAM_TIMING__sdram__disable 0 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__ref__WIDTH 2 -#define R_DRAM_TIMING__ref__e52us 0 -#define R_DRAM_TIMING__ref__e13us 1 -#define R_DRAM_TIMING__ref__e8700ns 2 -#define R_DRAM_TIMING__ref__disable 3 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rp__WIDTH 2 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rs__WIDTH 2 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__rh__WIDTH 2 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__w__WIDTH 1 -#define R_DRAM_TIMING__w__norm 0 -#define R_DRAM_TIMING__w__ext 1 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__c__WIDTH 1 -#define R_DRAM_TIMING__c__norm 0 -#define R_DRAM_TIMING__c__ext 1 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cz__WIDTH 2 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cp__WIDTH 2 -#define R_DRAM_TIMING__cw__BITNR 0 -#define R_DRAM_TIMING__cw__WIDTH 2 - -#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__sdram__WIDTH 1 -#define R_SDRAM_TIMING__sdram__enable 1 -#define R_SDRAM_TIMING__sdram__disable 0 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__mrs_data__WIDTH 15 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ref__WIDTH 2 -#define R_SDRAM_TIMING__ref__e52us 0 -#define R_SDRAM_TIMING__ref__e13us 1 -#define R_SDRAM_TIMING__ref__e6500ns 2 -#define R_SDRAM_TIMING__ref__disable 3 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__ddr__WIDTH 1 -#define R_SDRAM_TIMING__ddr__on 1 -#define R_SDRAM_TIMING__ddr__off 0 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__clk100__WIDTH 1 -#define R_SDRAM_TIMING__clk100__on 1 -#define R_SDRAM_TIMING__clk100__off 0 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__ps__WIDTH 1 -#define R_SDRAM_TIMING__ps__on 1 -#define R_SDRAM_TIMING__ps__off 0 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__cmd__WIDTH 2 -#define R_SDRAM_TIMING__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__ref 2 -#define R_SDRAM_TIMING__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__nop 0 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__pde__WIDTH 1 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rc__WIDTH 2 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rp__WIDTH 2 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__rcd__WIDTH 2 -#define R_SDRAM_TIMING__cl__BITNR 0 -#define R_SDRAM_TIMING__cl__WIDTH 2 - -#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm1__WIDTH 1 -#define R_DRAM_CONFIG__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__wmm0__WIDTH 1 -#define R_DRAM_CONFIG__wmm0__wmm 1 -#define R_DRAM_CONFIG__wmm0__norm 0 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh1__WIDTH 3 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__sh0__WIDTH 3 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__w__WIDTH 1 -#define R_DRAM_CONFIG__w__bw16 0 -#define R_DRAM_CONFIG__w__bw32 1 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__c__WIDTH 1 -#define R_DRAM_CONFIG__c__byte 0 -#define R_DRAM_CONFIG__c__bank 1 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__e__WIDTH 1 -#define R_DRAM_CONFIG__e__fast 0 -#define R_DRAM_CONFIG__e__edo 1 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__group_sel__WIDTH 5 -#define R_DRAM_CONFIG__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__grp1 1 -#define R_DRAM_CONFIG__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__bit29 29 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__ca1__WIDTH 3 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__bank23sel__WIDTH 5 -#define R_DRAM_CONFIG__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bit29 29 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__ca0__WIDTH 3 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 -#define R_DRAM_CONFIG__bank01sel__WIDTH 5 -#define R_DRAM_CONFIG__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bit29 29 - -#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm1__WIDTH 1 -#define R_SDRAM_CONFIG__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__wmm0__WIDTH 1 -#define R_SDRAM_CONFIG__wmm0__wmm 1 -#define R_SDRAM_CONFIG__wmm0__norm 0 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh1__WIDTH 3 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__sh0__WIDTH 3 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__w__WIDTH 1 -#define R_SDRAM_CONFIG__w__bw16 0 -#define R_SDRAM_CONFIG__w__bw32 1 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type1__WIDTH 1 -#define R_SDRAM_CONFIG__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__type0__WIDTH 1 -#define R_SDRAM_CONFIG__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__group_sel__WIDTH 5 -#define R_SDRAM_CONFIG__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__grp1 1 -#define R_SDRAM_CONFIG__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__bit29 29 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__ca1__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__ca0__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 -#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel0__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bit29 29 - -/* -!* External DMA registers -!*/ - -#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_0_CMD__cnt__enable 1 -#define R_EXT_DMA_0_CMD__cnt__disable 0 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__apol__WIDTH 1 -#define R_EXT_DMA_0_CMD__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_0_CMD__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__wid__WIDTH 2 -#define R_EXT_DMA_0_CMD__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__word 1 -#define R_EXT_DMA_0_CMD__wid__dword 2 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__dir__WIDTH 1 -#define R_EXT_DMA_0_CMD__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__output 1 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__run__WIDTH 1 -#define R_EXT_DMA_0_CMD__run__start 1 -#define R_EXT_DMA_0_CMD__run__stop 0 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__run__WIDTH 1 -#define R_EXT_DMA_0_STAT__run__start 1 -#define R_EXT_DMA_0_STAT__run__stop 0 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 - -#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_1_CMD__cnt__enable 1 -#define R_EXT_DMA_1_CMD__cnt__disable 0 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__apol__WIDTH 1 -#define R_EXT_DMA_1_CMD__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_1_CMD__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__wid__WIDTH 2 -#define R_EXT_DMA_1_CMD__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__word 1 -#define R_EXT_DMA_1_CMD__wid__dword 2 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__dir__WIDTH 1 -#define R_EXT_DMA_1_CMD__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__output 1 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__run__WIDTH 1 -#define R_EXT_DMA_1_CMD__run__start 1 -#define R_EXT_DMA_1_CMD__run__stop 0 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__run__WIDTH 1 -#define R_EXT_DMA_1_STAT__run__start 1 -#define R_EXT_DMA_1_STAT__run__stop 0 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 - -/* -!* Timer registers -!*/ - -#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv1__WIDTH 8 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__timerdiv0__WIDTH 8 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__presc_timer1__WIDTH 1 -#define R_TIMER_CTRL__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__i1__WIDTH 1 -#define R_TIMER_CTRL__i1__clr 1 -#define R_TIMER_CTRL__i1__nop 0 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__tm1__WIDTH 2 -#define R_TIMER_CTRL__tm1__stop_ld 0 -#define R_TIMER_CTRL__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__run 2 -#define R_TIMER_CTRL__tm1__reserved 3 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__clksel1__WIDTH 4 -#define R_TIMER_CTRL__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__presc_ext__WIDTH 1 -#define R_TIMER_CTRL__presc_ext__prescale 0 -#define R_TIMER_CTRL__presc_ext__external 1 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__i0__WIDTH 1 -#define R_TIMER_CTRL__i0__clr 1 -#define R_TIMER_CTRL__i0__nop 0 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__tm0__WIDTH 2 -#define R_TIMER_CTRL__tm0__stop_ld 0 -#define R_TIMER_CTRL__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__run 2 -#define R_TIMER_CTRL__tm0__reserved 3 -#define R_TIMER_CTRL__clksel0__BITNR 0 -#define R_TIMER_CTRL__clksel0__WIDTH 4 -#define R_TIMER_CTRL__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__flexible 15 - -#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer1__WIDTH 8 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__timer0__WIDTH 8 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_high__WIDTH 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 -#define R_TIMER_DATA__clkdiv_low__WIDTH 8 - -#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) -#define R_TIMER01_DATA__count__BITNR 0 -#define R_TIMER01_DATA__count__WIDTH 16 - -#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) -#define R_TIMER0_DATA__count__BITNR 0 -#define R_TIMER0_DATA__count__WIDTH 8 - -#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) -#define R_TIMER1_DATA__count__BITNR 0 -#define R_TIMER1_DATA__count__WIDTH 8 - -#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__key__WIDTH 3 -#define R_WATCHDOG__enable__BITNR 0 -#define R_WATCHDOG__enable__WIDTH 1 -#define R_WATCHDOG__enable__stop 0 -#define R_WATCHDOG__enable__start 1 - -#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 -#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 - -#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 -#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 - -#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 -#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 - -#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__ser_status__WIDTH 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 -#define R_PRESCALE_STATUS__tim_status__WIDTH 16 - -#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 -#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 - -#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 -#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 - -#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 - -/* -!* Shared RAM interface registers -!*/ - -#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__width__WIDTH 1 -#define R_SHARED_RAM_CONFIG__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 -#define R_SHARED_RAM_CONFIG__enable__yes 1 -#define R_SHARED_RAM_CONFIG__enable__no 0 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 -#define R_SHARED_RAM_CONFIG__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 -#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 -#define R_SHARED_RAM_CONFIG__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__nop 0 - -#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 -#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 - -/* -!* General config registers -!*/ - -#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__par_w__WIDTH 1 -#define R_GEN_CONFIG__par_w__select 1 -#define R_GEN_CONFIG__par_w__disable 0 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb2__WIDTH 1 -#define R_GEN_CONFIG__usb2__select 1 -#define R_GEN_CONFIG__usb2__disable 0 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__usb1__WIDTH 1 -#define R_GEN_CONFIG__usb1__select 1 -#define R_GEN_CONFIG__usb1__disable 0 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g24dir__WIDTH 1 -#define R_GEN_CONFIG__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_23dir__WIDTH 1 -#define R_GEN_CONFIG__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__out 1 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g8_15dir__WIDTH 1 -#define R_GEN_CONFIG__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__g0dir__WIDTH 1 -#define R_GEN_CONFIG__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__out 1 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma9__WIDTH 1 -#define R_GEN_CONFIG__dma9__usb 0 -#define R_GEN_CONFIG__dma9__serial1 1 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma8__WIDTH 1 -#define R_GEN_CONFIG__dma8__usb 0 -#define R_GEN_CONFIG__dma8__serial1 1 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma7__WIDTH 2 -#define R_GEN_CONFIG__dma7__unused 0 -#define R_GEN_CONFIG__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__intdma6 3 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma6__WIDTH 2 -#define R_GEN_CONFIG__dma6__unused 0 -#define R_GEN_CONFIG__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__intdma7 3 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma5__WIDTH 2 -#define R_GEN_CONFIG__dma5__par1 0 -#define R_GEN_CONFIG__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__serial3 2 -#define R_GEN_CONFIG__dma5__extdma0 3 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma4__WIDTH 2 -#define R_GEN_CONFIG__dma4__par1 0 -#define R_GEN_CONFIG__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__serial3 2 -#define R_GEN_CONFIG__dma4__extdma0 3 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma3__WIDTH 2 -#define R_GEN_CONFIG__dma3__par0 0 -#define R_GEN_CONFIG__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__serial2 2 -#define R_GEN_CONFIG__dma3__ata 3 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__dma2__WIDTH 2 -#define R_GEN_CONFIG__dma2__par0 0 -#define R_GEN_CONFIG__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__serial2 2 -#define R_GEN_CONFIG__dma2__ata 3 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__mio_w__WIDTH 1 -#define R_GEN_CONFIG__mio_w__select 1 -#define R_GEN_CONFIG__mio_w__disable 0 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__ser3__WIDTH 1 -#define R_GEN_CONFIG__ser3__select 1 -#define R_GEN_CONFIG__ser3__disable 0 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__par1__WIDTH 1 -#define R_GEN_CONFIG__par1__select 1 -#define R_GEN_CONFIG__par1__disable 0 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi0w__WIDTH 1 -#define R_GEN_CONFIG__scsi0w__select 1 -#define R_GEN_CONFIG__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__scsi1__WIDTH 1 -#define R_GEN_CONFIG__scsi1__select 1 -#define R_GEN_CONFIG__scsi1__disable 0 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__mio__WIDTH 1 -#define R_GEN_CONFIG__mio__select 1 -#define R_GEN_CONFIG__mio__disable 0 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__ser2__WIDTH 1 -#define R_GEN_CONFIG__ser2__select 1 -#define R_GEN_CONFIG__ser2__disable 0 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__par0__WIDTH 1 -#define R_GEN_CONFIG__par0__select 1 -#define R_GEN_CONFIG__par0__disable 0 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__ata__WIDTH 1 -#define R_GEN_CONFIG__ata__select 1 -#define R_GEN_CONFIG__ata__disable 0 -#define R_GEN_CONFIG__scsi0__BITNR 0 -#define R_GEN_CONFIG__scsi0__WIDTH 1 -#define R_GEN_CONFIG__scsi0__select 1 -#define R_GEN_CONFIG__scsi0__disable 0 - -#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode3__WIDTH 1 -#define R_GEN_CONFIG_II__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__sermode1__WIDTH 1 -#define R_GEN_CONFIG_II__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 -#define R_GEN_CONFIG_II__ext_clk__select 1 -#define R_GEN_CONFIG_II__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ser2__BITNR 1 -#define R_GEN_CONFIG_II__ser2__WIDTH 1 -#define R_GEN_CONFIG_II__ser2__select 1 -#define R_GEN_CONFIG_II__ser2__disable 0 -#define R_GEN_CONFIG_II__ser3__BITNR 0 -#define R_GEN_CONFIG_II__ser3__WIDTH 1 -#define R_GEN_CONFIG_II__ser3__select 1 -#define R_GEN_CONFIG_II__ser3__disable 0 - -#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__data__BITNR 0 -#define R_PORT_G_DATA__data__WIDTH 32 - -/* -!* General port configuration registers -!*/ - -#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir7__WIDTH 1 -#define R_PORT_PA_SET__dir7__input 0 -#define R_PORT_PA_SET__dir7__output 1 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir6__WIDTH 1 -#define R_PORT_PA_SET__dir6__input 0 -#define R_PORT_PA_SET__dir6__output 1 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir5__WIDTH 1 -#define R_PORT_PA_SET__dir5__input 0 -#define R_PORT_PA_SET__dir5__output 1 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir4__WIDTH 1 -#define R_PORT_PA_SET__dir4__input 0 -#define R_PORT_PA_SET__dir4__output 1 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir3__WIDTH 1 -#define R_PORT_PA_SET__dir3__input 0 -#define R_PORT_PA_SET__dir3__output 1 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir2__WIDTH 1 -#define R_PORT_PA_SET__dir2__input 0 -#define R_PORT_PA_SET__dir2__output 1 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir1__WIDTH 1 -#define R_PORT_PA_SET__dir1__input 0 -#define R_PORT_PA_SET__dir1__output 1 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__dir0__WIDTH 1 -#define R_PORT_PA_SET__dir0__input 0 -#define R_PORT_PA_SET__dir0__output 1 -#define R_PORT_PA_SET__data_out__BITNR 0 -#define R_PORT_PA_SET__data_out__WIDTH 8 - -#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) -#define R_PORT_PA_DATA__data_out__BITNR 0 -#define R_PORT_PA_DATA__data_out__WIDTH 8 - -#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir7__WIDTH 1 -#define R_PORT_PA_DIR__dir7__input 0 -#define R_PORT_PA_DIR__dir7__output 1 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir6__WIDTH 1 -#define R_PORT_PA_DIR__dir6__input 0 -#define R_PORT_PA_DIR__dir6__output 1 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir5__WIDTH 1 -#define R_PORT_PA_DIR__dir5__input 0 -#define R_PORT_PA_DIR__dir5__output 1 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir4__WIDTH 1 -#define R_PORT_PA_DIR__dir4__input 0 -#define R_PORT_PA_DIR__dir4__output 1 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir3__WIDTH 1 -#define R_PORT_PA_DIR__dir3__input 0 -#define R_PORT_PA_DIR__dir3__output 1 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir2__WIDTH 1 -#define R_PORT_PA_DIR__dir2__input 0 -#define R_PORT_PA_DIR__dir2__output 1 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir1__WIDTH 1 -#define R_PORT_PA_DIR__dir1__input 0 -#define R_PORT_PA_DIR__dir1__output 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 -#define R_PORT_PA_DIR__dir0__WIDTH 1 -#define R_PORT_PA_DIR__dir0__input 0 -#define R_PORT_PA_DIR__dir0__output 1 - -#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) -#define R_PORT_PA_READ__data_in__BITNR 0 -#define R_PORT_PA_READ__data_in__WIDTH 8 - -#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser3__WIDTH 1 -#define R_PORT_PB_SET__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__syncser1__WIDTH 1 -#define R_PORT_PB_SET__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_en__WIDTH 1 -#define R_PORT_PB_SET__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_d__WIDTH 1 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_clk__WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__i2c_oe___WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___enable 0 -#define R_PORT_PB_SET__i2c_oe___disable 1 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs7__WIDTH 1 -#define R_PORT_PB_SET__cs7__port 0 -#define R_PORT_PB_SET__cs7__cs 1 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs6__WIDTH 1 -#define R_PORT_PB_SET__cs6__port 0 -#define R_PORT_PB_SET__cs6__cs 1 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs5__WIDTH 1 -#define R_PORT_PB_SET__cs5__port 0 -#define R_PORT_PB_SET__cs5__cs 1 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs4__WIDTH 1 -#define R_PORT_PB_SET__cs4__port 0 -#define R_PORT_PB_SET__cs4__cs 1 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs3__WIDTH 1 -#define R_PORT_PB_SET__cs3__port 0 -#define R_PORT_PB_SET__cs3__cs 1 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__cs2__WIDTH 1 -#define R_PORT_PB_SET__cs2__port 0 -#define R_PORT_PB_SET__cs2__cs 1 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi1__WIDTH 1 -#define R_PORT_PB_SET__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi1__enph 1 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__scsi0__WIDTH 1 -#define R_PORT_PB_SET__scsi0__port_cs 0 -#define R_PORT_PB_SET__scsi0__enph 1 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir7__WIDTH 1 -#define R_PORT_PB_SET__dir7__input 0 -#define R_PORT_PB_SET__dir7__output 1 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir6__WIDTH 1 -#define R_PORT_PB_SET__dir6__input 0 -#define R_PORT_PB_SET__dir6__output 1 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir5__WIDTH 1 -#define R_PORT_PB_SET__dir5__input 0 -#define R_PORT_PB_SET__dir5__output 1 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir4__WIDTH 1 -#define R_PORT_PB_SET__dir4__input 0 -#define R_PORT_PB_SET__dir4__output 1 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir3__WIDTH 1 -#define R_PORT_PB_SET__dir3__input 0 -#define R_PORT_PB_SET__dir3__output 1 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir2__WIDTH 1 -#define R_PORT_PB_SET__dir2__input 0 -#define R_PORT_PB_SET__dir2__output 1 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir1__WIDTH 1 -#define R_PORT_PB_SET__dir1__input 0 -#define R_PORT_PB_SET__dir1__output 1 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__dir0__WIDTH 1 -#define R_PORT_PB_SET__dir0__input 0 -#define R_PORT_PB_SET__dir0__output 1 -#define R_PORT_PB_SET__data_out__BITNR 0 -#define R_PORT_PB_SET__data_out__WIDTH 8 - -#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) -#define R_PORT_PB_DATA__data_out__BITNR 0 -#define R_PORT_PB_DATA__data_out__WIDTH 8 - -#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir7__WIDTH 1 -#define R_PORT_PB_DIR__dir7__input 0 -#define R_PORT_PB_DIR__dir7__output 1 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir6__WIDTH 1 -#define R_PORT_PB_DIR__dir6__input 0 -#define R_PORT_PB_DIR__dir6__output 1 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir5__WIDTH 1 -#define R_PORT_PB_DIR__dir5__input 0 -#define R_PORT_PB_DIR__dir5__output 1 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir4__WIDTH 1 -#define R_PORT_PB_DIR__dir4__input 0 -#define R_PORT_PB_DIR__dir4__output 1 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir3__WIDTH 1 -#define R_PORT_PB_DIR__dir3__input 0 -#define R_PORT_PB_DIR__dir3__output 1 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir2__WIDTH 1 -#define R_PORT_PB_DIR__dir2__input 0 -#define R_PORT_PB_DIR__dir2__output 1 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir1__WIDTH 1 -#define R_PORT_PB_DIR__dir1__input 0 -#define R_PORT_PB_DIR__dir1__output 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 -#define R_PORT_PB_DIR__dir0__WIDTH 1 -#define R_PORT_PB_DIR__dir0__input 0 -#define R_PORT_PB_DIR__dir0__output 1 - -#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs7__WIDTH 1 -#define R_PORT_PB_CONFIG__cs7__port 0 -#define R_PORT_PB_CONFIG__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs6__WIDTH 1 -#define R_PORT_PB_CONFIG__cs6__port 0 -#define R_PORT_PB_CONFIG__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs5__WIDTH 1 -#define R_PORT_PB_CONFIG__cs5__port 0 -#define R_PORT_PB_CONFIG__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs4__WIDTH 1 -#define R_PORT_PB_CONFIG__cs4__port 0 -#define R_PORT_PB_CONFIG__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs3__WIDTH 1 -#define R_PORT_PB_CONFIG__cs3__port 0 -#define R_PORT_PB_CONFIG__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__cs2__WIDTH 1 -#define R_PORT_PB_CONFIG__cs2__port 0 -#define R_PORT_PB_CONFIG__cs2__cs 1 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 -#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi0__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__enph 1 - -#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser3__WIDTH 1 -#define R_PORT_PB_I2C__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__syncser1__WIDTH 1 -#define R_PORT_PB_I2C__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_en__WIDTH 1 -#define R_PORT_PB_I2C__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_d__WIDTH 1 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 -#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___enable 0 -#define R_PORT_PB_I2C__i2c_oe___disable 1 - -#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) -#define R_PORT_PB_READ__data_in__BITNR 0 -#define R_PORT_PB_READ__data_in__WIDTH 8 - -/* -!* Serial port registers -!*/ - -#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__reserved 15 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__reserved 15 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_CTRL__dma_err__stop 0 -#define R_SERIAL0_CTRL__dma_err__ignore 1 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_CTRL__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__rts___WIDTH 1 -#define R_SERIAL0_CTRL__rts___active 0 -#define R_SERIAL0_CTRL__rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_CTRL__sampling__middle 0 -#define R_SERIAL0_CTRL__sampling__majority 1 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__txd__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__auto_cts__active 1 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__data_out__BITNR 0 -#define R_SERIAL0_CTRL__data_out__WIDTH 8 - -#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__reserved 15 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 -#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__reserved 15 - -#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_REC_CTRL__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL0_REC_CTRL__rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_REC_CTRL__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 -#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__xoff_detect__WIDTH 1 -#define R_SERIAL0_READ__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__cts___WIDTH 1 -#define R_SERIAL0_READ__cts___active 0 -#define R_SERIAL0_READ__cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__tr_ready__WIDTH 1 -#define R_SERIAL0_READ__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__ready 1 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__rxd__WIDTH 1 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__overrun__WIDTH 1 -#define R_SERIAL0_READ__overrun__no 0 -#define R_SERIAL0_READ__overrun__yes 1 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__par_err__WIDTH 1 -#define R_SERIAL0_READ__par_err__no 0 -#define R_SERIAL0_READ__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__framing_err__WIDTH 1 -#define R_SERIAL0_READ__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_avail__WIDTH 1 -#define R_SERIAL0_READ__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__yes 1 -#define R_SERIAL0_READ__data_in__BITNR 0 -#define R_SERIAL0_READ__data_in__WIDTH 8 - -#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__cts___WIDTH 1 -#define R_SERIAL0_STATUS__cts___active 0 -#define R_SERIAL0_STATUS__cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL0_STATUS__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__ready 1 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__rxd__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__overrun__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__par_err__WIDTH 1 -#define R_SERIAL0_STATUS__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__framing_err__WIDTH 1 -#define R_SERIAL0_STATUS__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 -#define R_SERIAL0_STATUS__data_avail__WIDTH 1 -#define R_SERIAL0_STATUS__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__yes 1 - -#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 -#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL0_XOFF__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL0_XOFF__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__enable 1 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 -#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__reserved 15 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_CTRL__dma_err__stop 0 -#define R_SERIAL1_CTRL__dma_err__ignore 1 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__rts___WIDTH 1 -#define R_SERIAL1_CTRL__rts___active 0 -#define R_SERIAL1_CTRL__rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_CTRL__sampling__middle 0 -#define R_SERIAL1_CTRL__sampling__majority 1 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__txd__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__auto_cts__active 1 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__data_out__BITNR 0 -#define R_SERIAL1_CTRL__data_out__WIDTH 8 - -#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__reserved 15 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 -#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__reserved 15 - -#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_REC_CTRL__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL1_REC_CTRL__rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_REC_CTRL__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__xoff_detect__WIDTH 1 -#define R_SERIAL1_READ__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__cts___WIDTH 1 -#define R_SERIAL1_READ__cts___active 0 -#define R_SERIAL1_READ__cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__tr_ready__WIDTH 1 -#define R_SERIAL1_READ__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__ready 1 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__rxd__WIDTH 1 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__overrun__WIDTH 1 -#define R_SERIAL1_READ__overrun__no 0 -#define R_SERIAL1_READ__overrun__yes 1 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__par_err__WIDTH 1 -#define R_SERIAL1_READ__par_err__no 0 -#define R_SERIAL1_READ__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__framing_err__WIDTH 1 -#define R_SERIAL1_READ__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_avail__WIDTH 1 -#define R_SERIAL1_READ__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__yes 1 -#define R_SERIAL1_READ__data_in__BITNR 0 -#define R_SERIAL1_READ__data_in__WIDTH 8 - -#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__cts___WIDTH 1 -#define R_SERIAL1_STATUS__cts___active 0 -#define R_SERIAL1_STATUS__cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL1_STATUS__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__rxd__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__par_err__WIDTH 1 -#define R_SERIAL1_STATUS__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__framing_err__WIDTH 1 -#define R_SERIAL1_STATUS__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 -#define R_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SERIAL1_STATUS__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__yes 1 - -#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL1_XOFF__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL1_XOFF__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__enable 1 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 -#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__reserved 15 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__reserved 15 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_CTRL__dma_err__stop 0 -#define R_SERIAL2_CTRL__dma_err__ignore 1 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_CTRL__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__rts___WIDTH 1 -#define R_SERIAL2_CTRL__rts___active 0 -#define R_SERIAL2_CTRL__rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_CTRL__sampling__middle 0 -#define R_SERIAL2_CTRL__sampling__majority 1 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__txd__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__auto_cts__active 1 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__data_out__BITNR 0 -#define R_SERIAL2_CTRL__data_out__WIDTH 8 - -#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__reserved 15 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 -#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__reserved 15 - -#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_REC_CTRL__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL2_REC_CTRL__rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_REC_CTRL__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 -#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__xoff_detect__WIDTH 1 -#define R_SERIAL2_READ__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__cts___WIDTH 1 -#define R_SERIAL2_READ__cts___active 0 -#define R_SERIAL2_READ__cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__tr_ready__WIDTH 1 -#define R_SERIAL2_READ__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__ready 1 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__rxd__WIDTH 1 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__overrun__WIDTH 1 -#define R_SERIAL2_READ__overrun__no 0 -#define R_SERIAL2_READ__overrun__yes 1 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__par_err__WIDTH 1 -#define R_SERIAL2_READ__par_err__no 0 -#define R_SERIAL2_READ__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__framing_err__WIDTH 1 -#define R_SERIAL2_READ__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_avail__WIDTH 1 -#define R_SERIAL2_READ__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__yes 1 -#define R_SERIAL2_READ__data_in__BITNR 0 -#define R_SERIAL2_READ__data_in__WIDTH 8 - -#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__cts___WIDTH 1 -#define R_SERIAL2_STATUS__cts___active 0 -#define R_SERIAL2_STATUS__cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL2_STATUS__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__ready 1 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__rxd__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__overrun__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__par_err__WIDTH 1 -#define R_SERIAL2_STATUS__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__framing_err__WIDTH 1 -#define R_SERIAL2_STATUS__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 -#define R_SERIAL2_STATUS__data_avail__WIDTH 1 -#define R_SERIAL2_STATUS__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__yes 1 - -#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 -#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL2_XOFF__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL2_XOFF__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__enable 1 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 -#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__reserved 15 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_CTRL__dma_err__stop 0 -#define R_SERIAL3_CTRL__dma_err__ignore 1 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__rts___WIDTH 1 -#define R_SERIAL3_CTRL__rts___active 0 -#define R_SERIAL3_CTRL__rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_CTRL__sampling__middle 0 -#define R_SERIAL3_CTRL__sampling__majority 1 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__txd__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__auto_cts__active 1 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__data_out__BITNR 0 -#define R_SERIAL3_CTRL__data_out__WIDTH 8 - -#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__reserved 15 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 -#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__reserved 15 - -#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_REC_CTRL__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL3_REC_CTRL__rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_REC_CTRL__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__xoff_detect__WIDTH 1 -#define R_SERIAL3_READ__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__cts___WIDTH 1 -#define R_SERIAL3_READ__cts___active 0 -#define R_SERIAL3_READ__cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__tr_ready__WIDTH 1 -#define R_SERIAL3_READ__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__ready 1 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__rxd__WIDTH 1 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__overrun__WIDTH 1 -#define R_SERIAL3_READ__overrun__no 0 -#define R_SERIAL3_READ__overrun__yes 1 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__par_err__WIDTH 1 -#define R_SERIAL3_READ__par_err__no 0 -#define R_SERIAL3_READ__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__framing_err__WIDTH 1 -#define R_SERIAL3_READ__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_avail__WIDTH 1 -#define R_SERIAL3_READ__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__yes 1 -#define R_SERIAL3_READ__data_in__BITNR 0 -#define R_SERIAL3_READ__data_in__WIDTH 8 - -#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__cts___WIDTH 1 -#define R_SERIAL3_STATUS__cts___active 0 -#define R_SERIAL3_STATUS__cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL3_STATUS__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__rxd__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__par_err__WIDTH 1 -#define R_SERIAL3_STATUS__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__framing_err__WIDTH 1 -#define R_SERIAL3_STATUS__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 -#define R_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SERIAL3_STATUS__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__yes 1 - -#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL3_XOFF__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL3_XOFF__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__enable 1 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 -#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 - -#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 - -/* -!* Network interface registers -!*/ - -#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) -#define R_NETWORK_SA_0__ma0_low__BITNR 0 -#define R_NETWORK_SA_0__ma0_low__WIDTH 32 - -#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma1_low__WIDTH 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 -#define R_NETWORK_SA_1__ma0_high__WIDTH 16 - -#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) -#define R_NETWORK_SA_2__ma1_high__BITNR 0 -#define R_NETWORK_SA_2__ma1_high__WIDTH 32 - -#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) -#define R_NETWORK_GA_0__ga_low__BITNR 0 -#define R_NETWORK_GA_0__ga_low__WIDTH 32 - -#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) -#define R_NETWORK_GA_1__ga_high__BITNR 0 -#define R_NETWORK_GA_1__ga_high__WIDTH 32 - -#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 -#define R_NETWORK_REC_CONFIG__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 -#define R_NETWORK_REC_CONFIG__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 -#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 -#define R_NETWORK_REC_CONFIG__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 -#define R_NETWORK_REC_CONFIG__individual__receive 1 -#define R_NETWORK_REC_CONFIG__individual__discard 0 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 -#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma0__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__disable 0 - -#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__vg__on 1 -#define R_NETWORK_GEN_CONFIG__vg__off 0 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 -#define R_NETWORK_GEN_CONFIG__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 -#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__enable__on 1 -#define R_NETWORK_GEN_CONFIG__enable__off 0 - -#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 -#define R_NETWORK_TR_CTRL__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__delay__WIDTH 1 -#define R_NETWORK_TR_CTRL__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 -#define R_NETWORK_TR_CTRL__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__cd__WIDTH 1 -#define R_NETWORK_TR_CTRL__cd__enable 0 -#define R_NETWORK_TR_CTRL__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__retry__WIDTH 1 -#define R_NETWORK_TR_CTRL__retry__enable 0 -#define R_NETWORK_TR_CTRL__retry__disable 1 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__pad__WIDTH 1 -#define R_NETWORK_TR_CTRL__pad__enable 1 -#define R_NETWORK_TR_CTRL__pad__disable 0 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 -#define R_NETWORK_TR_CTRL__crc__WIDTH 1 -#define R_NETWORK_TR_CTRL__crc__enable 0 -#define R_NETWORK_TR_CTRL__crc__disable 1 - -#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__enable 1 -#define R_NETWORK_MGM_CTRL__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 -#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 - -#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxd_pins__WIDTH 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__rxer__WIDTH 1 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__underrun__WIDTH 1 -#define R_NETWORK_STAT__underrun__yes 1 -#define R_NETWORK_STAT__underrun__no 0 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__exc_col__WIDTH 1 -#define R_NETWORK_STAT__exc_col__yes 1 -#define R_NETWORK_STAT__exc_col__no 0 -#define R_NETWORK_STAT__mdio__BITNR 0 -#define R_NETWORK_STAT__mdio__WIDTH 1 - -#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__congestion__WIDTH 8 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__oversize__WIDTH 8 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__alignment_error__WIDTH 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 -#define R_REC_COUNTERS__crc_error__WIDTH 8 - -#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__deferred__WIDTH 8 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__late_col__WIDTH 8 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__multiple_col__WIDTH 8 -#define R_TR_COUNTERS__single_col__BITNR 0 -#define R_TR_COUNTERS__single_col__WIDTH 8 - -#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 -#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 - -/* -!* Parallel printer port registers -!*/ - -#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR0_CTRL_DATA__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__oe__WIDTH 1 -#define R_PAR0_CTRL_DATA__oe__enable 1 -#define R_PAR0_CTRL_DATA__oe__disable 0 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__seli__WIDTH 1 -#define R_PAR0_CTRL_DATA__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR0_CTRL_DATA__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__strb__WIDTH 1 -#define R_PAR0_CTRL_DATA__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__init__WIDTH 1 -#define R_PAR0_CTRL_DATA__init__active 1 -#define R_PAR0_CTRL_DATA__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR0_CTRL_DATA__data__BITNR 0 -#define R_PAR0_CTRL_DATA__data__WIDTH 8 - -#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) -#define R_PAR0_CTRL__ctrl__BITNR 0 -#define R_PAR0_CTRL__ctrl__WIDTH 5 - -#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__mode__WIDTH 3 -#define R_PAR0_STATUS_DATA__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__off 7 -#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__perr__WIDTH 1 -#define R_PAR0_STATUS_DATA__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__ack__WIDTH 1 -#define R_PAR0_STATUS_DATA__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__busy__WIDTH 1 -#define R_PAR0_STATUS_DATA__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__fault__WIDTH 1 -#define R_PAR0_STATUS_DATA__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__sel__WIDTH 1 -#define R_PAR0_STATUS_DATA__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR0_STATUS_DATA__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__dav__WIDTH 1 -#define R_PAR0_STATUS_DATA__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR0_STATUS_DATA__data__BITNR 0 -#define R_PAR0_STATUS_DATA__data__WIDTH 8 - -#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__mode__WIDTH 3 -#define R_PAR0_STATUS__mode__manual 0 -#define R_PAR0_STATUS__mode__centronics 1 -#define R_PAR0_STATUS__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__nibble 3 -#define R_PAR0_STATUS__mode__byte 4 -#define R_PAR0_STATUS__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__off 7 -#define R_PAR0_STATUS__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__epp_rd 0 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__perr__WIDTH 1 -#define R_PAR0_STATUS__perr__active 1 -#define R_PAR0_STATUS__perr__inactive 0 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__ack__WIDTH 1 -#define R_PAR0_STATUS__ack__active 0 -#define R_PAR0_STATUS__ack__inactive 1 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__busy__WIDTH 1 -#define R_PAR0_STATUS__busy__active 1 -#define R_PAR0_STATUS__busy__inactive 0 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__fault__WIDTH 1 -#define R_PAR0_STATUS__fault__active 0 -#define R_PAR0_STATUS__fault__inactive 1 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__sel__WIDTH 1 -#define R_PAR0_STATUS__sel__active 1 -#define R_PAR0_STATUS__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ext_mode__WIDTH 1 -#define R_PAR0_STATUS__ext_mode__enable 1 -#define R_PAR0_STATUS__ext_mode__disable 0 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__ecp_16__WIDTH 1 -#define R_PAR0_STATUS__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS__tr_rdy__ready 1 -#define R_PAR0_STATUS__tr_rdy__busy 0 -#define R_PAR0_STATUS__dav__BITNR 0 -#define R_PAR0_STATUS__dav__WIDTH 1 -#define R_PAR0_STATUS__dav__data 1 -#define R_PAR0_STATUS__dav__nodata 0 - -#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__data__BITNR 0 -#define R_PAR_ECP16_DATA__data__WIDTH 16 - -#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__ioe__WIDTH 1 -#define R_PAR0_CONFIG__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iseli__WIDTH 1 -#define R_PAR0_CONFIG__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__iautofd__WIDTH 1 -#define R_PAR0_CONFIG__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__istrb__WIDTH 1 -#define R_PAR0_CONFIG__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iinit__WIDTH 1 -#define R_PAR0_CONFIG__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iperr__WIDTH 1 -#define R_PAR0_CONFIG__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__iack__WIDTH 1 -#define R_PAR0_CONFIG__iack__inv 1 -#define R_PAR0_CONFIG__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ibusy__WIDTH 1 -#define R_PAR0_CONFIG__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__ifault__WIDTH 1 -#define R_PAR0_CONFIG__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__isel__WIDTH 1 -#define R_PAR0_CONFIG__isel__inv 1 -#define R_PAR0_CONFIG__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__ext_mode__WIDTH 1 -#define R_PAR0_CONFIG__ext_mode__enable 1 -#define R_PAR0_CONFIG__ext_mode__disable 0 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__wide__WIDTH 1 -#define R_PAR0_CONFIG__wide__enable 1 -#define R_PAR0_CONFIG__wide__disable 0 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__dma__WIDTH 1 -#define R_PAR0_CONFIG__dma__enable 1 -#define R_PAR0_CONFIG__dma__disable 0 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_in__WIDTH 1 -#define R_PAR0_CONFIG__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__rle_out__WIDTH 1 -#define R_PAR0_CONFIG__rle_out__enable 1 -#define R_PAR0_CONFIG__rle_out__disable 0 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__enable__WIDTH 1 -#define R_PAR0_CONFIG__enable__on 1 -#define R_PAR0_CONFIG__enable__reset 0 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__force__WIDTH 1 -#define R_PAR0_CONFIG__force__on 1 -#define R_PAR0_CONFIG__force__off 0 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__ign_ack__WIDTH 1 -#define R_PAR0_CONFIG__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__oe_ack__WIDTH 1 -#define R_PAR0_CONFIG__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__mode__BITNR 0 -#define R_PAR0_CONFIG__mode__WIDTH 3 -#define R_PAR0_CONFIG__mode__manual 0 -#define R_PAR0_CONFIG__mode__centronics 1 -#define R_PAR0_CONFIG__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__nibble 3 -#define R_PAR0_CONFIG__mode__byte 4 -#define R_PAR0_CONFIG__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__off 7 -#define R_PAR0_CONFIG__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__epp_rd 0 - -#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__fine_hold__WIDTH 3 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__hold__WIDTH 5 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__fine_strb__WIDTH 3 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__strobe__WIDTH 5 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__fine_setup__WIDTH 3 -#define R_PAR0_DELAY__setup__BITNR 0 -#define R_PAR0_DELAY__setup__WIDTH 5 - -#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR1_CTRL_DATA__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__oe__WIDTH 1 -#define R_PAR1_CTRL_DATA__oe__enable 1 -#define R_PAR1_CTRL_DATA__oe__disable 0 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__seli__WIDTH 1 -#define R_PAR1_CTRL_DATA__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR1_CTRL_DATA__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__strb__WIDTH 1 -#define R_PAR1_CTRL_DATA__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__init__WIDTH 1 -#define R_PAR1_CTRL_DATA__init__active 1 -#define R_PAR1_CTRL_DATA__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR1_CTRL_DATA__data__BITNR 0 -#define R_PAR1_CTRL_DATA__data__WIDTH 8 - -#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) -#define R_PAR1_CTRL__ctrl__BITNR 0 -#define R_PAR1_CTRL__ctrl__WIDTH 5 - -#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__mode__WIDTH 3 -#define R_PAR1_STATUS_DATA__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__off 7 -#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__perr__WIDTH 1 -#define R_PAR1_STATUS_DATA__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__ack__WIDTH 1 -#define R_PAR1_STATUS_DATA__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__busy__WIDTH 1 -#define R_PAR1_STATUS_DATA__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__fault__WIDTH 1 -#define R_PAR1_STATUS_DATA__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__sel__WIDTH 1 -#define R_PAR1_STATUS_DATA__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR1_STATUS_DATA__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__dav__WIDTH 1 -#define R_PAR1_STATUS_DATA__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR1_STATUS_DATA__data__BITNR 0 -#define R_PAR1_STATUS_DATA__data__WIDTH 8 - -#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__mode__WIDTH 3 -#define R_PAR1_STATUS__mode__manual 0 -#define R_PAR1_STATUS__mode__centronics 1 -#define R_PAR1_STATUS__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__nibble 3 -#define R_PAR1_STATUS__mode__byte 4 -#define R_PAR1_STATUS__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__off 7 -#define R_PAR1_STATUS__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__epp_rd 0 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__perr__WIDTH 1 -#define R_PAR1_STATUS__perr__active 1 -#define R_PAR1_STATUS__perr__inactive 0 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__ack__WIDTH 1 -#define R_PAR1_STATUS__ack__active 0 -#define R_PAR1_STATUS__ack__inactive 1 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__busy__WIDTH 1 -#define R_PAR1_STATUS__busy__active 1 -#define R_PAR1_STATUS__busy__inactive 0 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__fault__WIDTH 1 -#define R_PAR1_STATUS__fault__active 0 -#define R_PAR1_STATUS__fault__inactive 1 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__sel__WIDTH 1 -#define R_PAR1_STATUS__sel__active 1 -#define R_PAR1_STATUS__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__ext_mode__WIDTH 1 -#define R_PAR1_STATUS__ext_mode__enable 1 -#define R_PAR1_STATUS__ext_mode__disable 0 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS__tr_rdy__ready 1 -#define R_PAR1_STATUS__tr_rdy__busy 0 -#define R_PAR1_STATUS__dav__BITNR 0 -#define R_PAR1_STATUS__dav__WIDTH 1 -#define R_PAR1_STATUS__dav__data 1 -#define R_PAR1_STATUS__dav__nodata 0 - -#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__ioe__WIDTH 1 -#define R_PAR1_CONFIG__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iseli__WIDTH 1 -#define R_PAR1_CONFIG__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__iautofd__WIDTH 1 -#define R_PAR1_CONFIG__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__istrb__WIDTH 1 -#define R_PAR1_CONFIG__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iinit__WIDTH 1 -#define R_PAR1_CONFIG__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iperr__WIDTH 1 -#define R_PAR1_CONFIG__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__iack__WIDTH 1 -#define R_PAR1_CONFIG__iack__inv 1 -#define R_PAR1_CONFIG__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ibusy__WIDTH 1 -#define R_PAR1_CONFIG__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__ifault__WIDTH 1 -#define R_PAR1_CONFIG__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__isel__WIDTH 1 -#define R_PAR1_CONFIG__isel__inv 1 -#define R_PAR1_CONFIG__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__ext_mode__WIDTH 1 -#define R_PAR1_CONFIG__ext_mode__enable 1 -#define R_PAR1_CONFIG__ext_mode__disable 0 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__dma__WIDTH 1 -#define R_PAR1_CONFIG__dma__enable 1 -#define R_PAR1_CONFIG__dma__disable 0 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_in__WIDTH 1 -#define R_PAR1_CONFIG__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__rle_out__WIDTH 1 -#define R_PAR1_CONFIG__rle_out__enable 1 -#define R_PAR1_CONFIG__rle_out__disable 0 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__enable__WIDTH 1 -#define R_PAR1_CONFIG__enable__on 1 -#define R_PAR1_CONFIG__enable__reset 0 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__force__WIDTH 1 -#define R_PAR1_CONFIG__force__on 1 -#define R_PAR1_CONFIG__force__off 0 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__ign_ack__WIDTH 1 -#define R_PAR1_CONFIG__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__oe_ack__WIDTH 1 -#define R_PAR1_CONFIG__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__mode__BITNR 0 -#define R_PAR1_CONFIG__mode__WIDTH 3 -#define R_PAR1_CONFIG__mode__manual 0 -#define R_PAR1_CONFIG__mode__centronics 1 -#define R_PAR1_CONFIG__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__nibble 3 -#define R_PAR1_CONFIG__mode__byte 4 -#define R_PAR1_CONFIG__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__off 7 -#define R_PAR1_CONFIG__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__epp_rd 0 - -#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__fine_hold__WIDTH 3 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__hold__WIDTH 5 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__fine_strb__WIDTH 3 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__strobe__WIDTH 5 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__fine_setup__WIDTH 3 -#define R_PAR1_DELAY__setup__BITNR 0 -#define R_PAR1_DELAY__setup__WIDTH 5 - -/* -!* ATA interface registers -!*/ - -#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__sel__WIDTH 2 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs1__WIDTH 1 -#define R_ATA_CTRL_DATA__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__cs0__WIDTH 1 -#define R_ATA_CTRL_DATA__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__inactive 0 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__addr__WIDTH 3 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__rw__WIDTH 1 -#define R_ATA_CTRL_DATA__rw__read 1 -#define R_ATA_CTRL_DATA__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 -#define R_ATA_CTRL_DATA__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__handsh__WIDTH 1 -#define R_ATA_CTRL_DATA__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__multi__WIDTH 1 -#define R_ATA_CTRL_DATA__multi__on 1 -#define R_ATA_CTRL_DATA__multi__off 0 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 -#define R_ATA_CTRL_DATA__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__word 0 -#define R_ATA_CTRL_DATA__data__BITNR 0 -#define R_ATA_CTRL_DATA__data__WIDTH 16 - -#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__busy__WIDTH 1 -#define R_ATA_STATUS_DATA__busy__yes 1 -#define R_ATA_STATUS_DATA__busy__no 0 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_ATA_STATUS_DATA__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__dav__WIDTH 1 -#define R_ATA_STATUS_DATA__dav__data 1 -#define R_ATA_STATUS_DATA__dav__nodata 0 -#define R_ATA_STATUS_DATA__data__BITNR 0 -#define R_ATA_STATUS_DATA__data__WIDTH 16 - -#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__enable__WIDTH 1 -#define R_ATA_CONFIG__enable__on 1 -#define R_ATA_CONFIG__enable__off 0 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_strobe__WIDTH 5 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__dma_hold__WIDTH 5 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_setup__WIDTH 5 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_strobe__WIDTH 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 -#define R_ATA_CONFIG__pio_hold__WIDTH 5 - -#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__count__BITNR 0 -#define R_ATA_TRANSFER_CNT__count__WIDTH 17 - -/* -!* SCSI registers -!*/ - -#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__id_type__WIDTH 1 -#define R_SCSI0_CTRL__id_type__software 1 -#define R_SCSI0_CTRL__id_type__hardware 0 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__synch_per__WIDTH 8 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__rst__WIDTH 1 -#define R_SCSI0_CTRL__rst__yes 1 -#define R_SCSI0_CTRL__rst__no 0 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__atn__WIDTH 1 -#define R_SCSI0_CTRL__atn__yes 1 -#define R_SCSI0_CTRL__atn__no 0 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__my_id__WIDTH 4 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__target_id__WIDTH 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__fast_20__WIDTH 1 -#define R_SCSI0_CTRL__fast_20__yes 1 -#define R_SCSI0_CTRL__fast_20__no 0 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__bus_width__WIDTH 1 -#define R_SCSI0_CTRL__bus_width__wide 1 -#define R_SCSI0_CTRL__bus_width__narrow 0 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__synch__WIDTH 1 -#define R_SCSI0_CTRL__synch__synch 1 -#define R_SCSI0_CTRL__synch__asynch 0 -#define R_SCSI0_CTRL__enable__BITNR 0 -#define R_SCSI0_CTRL__enable__WIDTH 1 -#define R_SCSI0_CTRL__enable__on 1 -#define R_SCSI0_CTRL__enable__off 0 - -#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI0_CMD_DATA__parity_in__on 0 -#define R_SCSI0_CMD_DATA__parity_in__off 1 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__skip__WIDTH 1 -#define R_SCSI0_CMD_DATA__skip__on 1 -#define R_SCSI0_CMD_DATA__skip__off 0 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI0_CMD_DATA__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__command__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__resel_stat 5 -#define R_SCSI0_CMD_DATA__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__man_rat 13 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 -#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA__data_out__BITNR 0 -#define R_SCSI0_DATA__data_out__WIDTH 16 - -#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD__command__BITNR 0 -#define R_SCSI0_CMD__command__WIDTH 4 -#define R_SCSI0_CMD__command__full_din_1 0 -#define R_SCSI0_CMD__command__full_dout_1 1 -#define R_SCSI0_CMD__command__full_stat_1 2 -#define R_SCSI0_CMD__command__resel_din 3 -#define R_SCSI0_CMD__command__resel_dout 4 -#define R_SCSI0_CMD__command__resel_stat 5 -#define R_SCSI0_CMD__command__arb_only 6 -#define R_SCSI0_CMD__command__full_din_3 8 -#define R_SCSI0_CMD__command__full_dout_3 9 -#define R_SCSI0_CMD__command__full_stat_3 10 -#define R_SCSI0_CMD__command__man_data_in 11 -#define R_SCSI0_CMD__command__man_data_out 12 -#define R_SCSI0_CMD__command__man_rat 13 - -#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__skip__on 1 -#define R_SCSI0_STATUS_CTRL__skip__off 0 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__tst_resel__WIDTH 1 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__parity_error__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__bus_reset__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__yes 1 -#define R_SCSI0_STATUS__bus_reset__no 0 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel_target__WIDTH 4 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__resel__WIDTH 1 -#define R_SCSI0_STATUS__resel__yes 1 -#define R_SCSI0_STATUS__resel__no 0 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__curr_phase__WIDTH 3 -#define R_SCSI0_STATUS__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__valid_status__WIDTH 1 -#define R_SCSI0_STATUS__valid_status__yes 1 -#define R_SCSI0_STATUS__valid_status__no 0 -#define R_SCSI0_STATUS__seq_status__BITNR 0 -#define R_SCSI0_STATUS__seq_status__WIDTH 5 -#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__data_in__BITNR 0 -#define R_SCSI0_DATA_IN__data_in__WIDTH 16 - -#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__id_type__WIDTH 1 -#define R_SCSI1_CTRL__id_type__software 1 -#define R_SCSI1_CTRL__id_type__hardware 0 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__synch_per__WIDTH 8 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__rst__WIDTH 1 -#define R_SCSI1_CTRL__rst__yes 1 -#define R_SCSI1_CTRL__rst__no 0 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__atn__WIDTH 1 -#define R_SCSI1_CTRL__atn__yes 1 -#define R_SCSI1_CTRL__atn__no 0 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__my_id__WIDTH 4 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__target_id__WIDTH 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__fast_20__WIDTH 1 -#define R_SCSI1_CTRL__fast_20__yes 1 -#define R_SCSI1_CTRL__fast_20__no 0 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__bus_width__WIDTH 1 -#define R_SCSI1_CTRL__bus_width__wide 1 -#define R_SCSI1_CTRL__bus_width__narrow 0 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__synch__WIDTH 1 -#define R_SCSI1_CTRL__synch__synch 1 -#define R_SCSI1_CTRL__synch__asynch 0 -#define R_SCSI1_CTRL__enable__BITNR 0 -#define R_SCSI1_CTRL__enable__WIDTH 1 -#define R_SCSI1_CTRL__enable__on 1 -#define R_SCSI1_CTRL__enable__off 0 - -#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI1_CMD_DATA__parity_in__on 0 -#define R_SCSI1_CMD_DATA__parity_in__off 1 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__skip__WIDTH 1 -#define R_SCSI1_CMD_DATA__skip__on 1 -#define R_SCSI1_CMD_DATA__skip__off 0 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI1_CMD_DATA__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__command__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__resel_stat 5 -#define R_SCSI1_CMD_DATA__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__man_rat 13 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 -#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA__data_out__BITNR 0 -#define R_SCSI1_DATA__data_out__WIDTH 16 - -#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD__command__BITNR 0 -#define R_SCSI1_CMD__command__WIDTH 4 -#define R_SCSI1_CMD__command__full_din_1 0 -#define R_SCSI1_CMD__command__full_dout_1 1 -#define R_SCSI1_CMD__command__full_stat_1 2 -#define R_SCSI1_CMD__command__resel_din 3 -#define R_SCSI1_CMD__command__resel_dout 4 -#define R_SCSI1_CMD__command__resel_stat 5 -#define R_SCSI1_CMD__command__arb_only 6 -#define R_SCSI1_CMD__command__full_din_3 8 -#define R_SCSI1_CMD__command__full_dout_3 9 -#define R_SCSI1_CMD__command__full_stat_3 10 -#define R_SCSI1_CMD__command__man_data_in 11 -#define R_SCSI1_CMD__command__man_data_out 12 -#define R_SCSI1_CMD__command__man_rat 13 - -#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__skip__on 1 -#define R_SCSI1_STATUS_CTRL__skip__off 0 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__tst_resel__WIDTH 1 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__parity_error__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__bus_reset__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__yes 1 -#define R_SCSI1_STATUS__bus_reset__no 0 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel_target__WIDTH 4 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__resel__WIDTH 1 -#define R_SCSI1_STATUS__resel__yes 1 -#define R_SCSI1_STATUS__resel__no 0 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__curr_phase__WIDTH 3 -#define R_SCSI1_STATUS__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__valid_status__WIDTH 1 -#define R_SCSI1_STATUS__valid_status__yes 1 -#define R_SCSI1_STATUS__valid_status__no 0 -#define R_SCSI1_STATUS__seq_status__BITNR 0 -#define R_SCSI1_STATUS__seq_status__WIDTH 5 -#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__data_in__BITNR 0 -#define R_SCSI1_DATA_IN__data_in__WIDTH 16 - -/* -!* Interrupt mask and status registers -!*/ - -#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_RD__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_RD__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_RD__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__deferred__WIDTH 1 -#define R_IRQ_MASK0_RD__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__late_col__WIDTH 1 -#define R_IRQ_MASK0_RD__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_RD__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__single_col__WIDTH 1 -#define R_IRQ_MASK0_RD__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__congestion__WIDTH 1 -#define R_IRQ_MASK0_RD__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__oversize__WIDTH 1 -#define R_IRQ_MASK0_RD__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_RD__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 -#define R_IRQ_MASK0_RD__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__overrun__WIDTH 1 -#define R_IRQ_MASK0_RD__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__underrun__WIDTH 1 -#define R_IRQ_MASK0_RD__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_RD__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__mdio__WIDTH 1 -#define R_IRQ_MASK0_RD__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__mio__WIDTH 1 -#define R_IRQ_MASK0_RD__mio__active 1 -#define R_IRQ_MASK0_RD__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 -#define R_IRQ_MASK0_RD__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer1__WIDTH 1 -#define R_IRQ_MASK0_RD__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 -#define R_IRQ_MASK0_RD__timer0__WIDTH 1 -#define R_IRQ_MASK0_RD__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__inactive 0 - -#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 -#define R_IRQ_MASK0_CLR__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 -#define R_IRQ_MASK0_CLR__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 -#define R_IRQ_MASK0_CLR__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 -#define R_IRQ_MASK0_CLR__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 -#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__nop 0 - -#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__nmi_pin__WIDTH 1 -#define R_IRQ_READ0__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 -#define R_IRQ_READ0__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__sqe_test_error__WIDTH 1 -#define R_IRQ_READ0__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__carrier_loss__WIDTH 1 -#define R_IRQ_READ0__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__deferred__WIDTH 1 -#define R_IRQ_READ0__deferred__active 1 -#define R_IRQ_READ0__deferred__inactive 0 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__late_col__WIDTH 1 -#define R_IRQ_READ0__late_col__active 1 -#define R_IRQ_READ0__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__multiple_col__WIDTH 1 -#define R_IRQ_READ0__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__single_col__WIDTH 1 -#define R_IRQ_READ0__single_col__active 1 -#define R_IRQ_READ0__single_col__inactive 0 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__congestion__WIDTH 1 -#define R_IRQ_READ0__congestion__active 1 -#define R_IRQ_READ0__congestion__inactive 0 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__oversize__WIDTH 1 -#define R_IRQ_READ0__oversize__active 1 -#define R_IRQ_READ0__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__alignment_error__WIDTH 1 -#define R_IRQ_READ0__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__crc_error__WIDTH 1 -#define R_IRQ_READ0__crc_error__active 1 -#define R_IRQ_READ0__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__overrun__WIDTH 1 -#define R_IRQ_READ0__overrun__active 1 -#define R_IRQ_READ0__overrun__inactive 0 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__underrun__WIDTH 1 -#define R_IRQ_READ0__underrun__active 1 -#define R_IRQ_READ0__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__excessive_col__WIDTH 1 -#define R_IRQ_READ0__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__mdio__WIDTH 1 -#define R_IRQ_READ0__mdio__active 1 -#define R_IRQ_READ0__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq3__WIDTH 1 -#define R_IRQ_READ0__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq2__WIDTH 1 -#define R_IRQ_READ0__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq1__WIDTH 1 -#define R_IRQ_READ0__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__ata_drq0__WIDTH 1 -#define R_IRQ_READ0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_READ0__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__ata_irq3__WIDTH 1 -#define R_IRQ_READ0__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__par0_peri__WIDTH 1 -#define R_IRQ_READ0__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__ata_irq2__WIDTH 1 -#define R_IRQ_READ0__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__par0_data__WIDTH 1 -#define R_IRQ_READ0__par0_data__active 1 -#define R_IRQ_READ0__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__ata_irq1__WIDTH 1 -#define R_IRQ_READ0__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__par0_ready__WIDTH 1 -#define R_IRQ_READ0__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__ata_irq0__WIDTH 1 -#define R_IRQ_READ0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__mio__WIDTH 1 -#define R_IRQ_READ0__mio__active 1 -#define R_IRQ_READ0__mio__inactive 0 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__scsi0__WIDTH 1 -#define R_IRQ_READ0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__ata_dmaend__WIDTH 1 -#define R_IRQ_READ0__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma1__WIDTH 1 -#define R_IRQ_READ0__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__ext_dma0__WIDTH 1 -#define R_IRQ_READ0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer1__WIDTH 1 -#define R_IRQ_READ0__timer1__active 1 -#define R_IRQ_READ0__timer1__inactive 0 -#define R_IRQ_READ0__timer0__BITNR 0 -#define R_IRQ_READ0__timer0__WIDTH 1 -#define R_IRQ_READ0__timer0__active 1 -#define R_IRQ_READ0__timer0__inactive 0 - -#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_SET__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_SET__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_SET__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__deferred__WIDTH 1 -#define R_IRQ_MASK0_SET__deferred__set 1 -#define R_IRQ_MASK0_SET__deferred__nop 0 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__late_col__WIDTH 1 -#define R_IRQ_MASK0_SET__late_col__set 1 -#define R_IRQ_MASK0_SET__late_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_SET__multiple_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__single_col__WIDTH 1 -#define R_IRQ_MASK0_SET__single_col__set 1 -#define R_IRQ_MASK0_SET__single_col__nop 0 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__congestion__WIDTH 1 -#define R_IRQ_MASK0_SET__congestion__set 1 -#define R_IRQ_MASK0_SET__congestion__nop 0 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__oversize__WIDTH 1 -#define R_IRQ_MASK0_SET__oversize__set 1 -#define R_IRQ_MASK0_SET__oversize__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_SET__alignment_error__set 1 -#define R_IRQ_MASK0_SET__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 -#define R_IRQ_MASK0_SET__crc_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__nop 0 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__overrun__WIDTH 1 -#define R_IRQ_MASK0_SET__overrun__set 1 -#define R_IRQ_MASK0_SET__overrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__underrun__WIDTH 1 -#define R_IRQ_MASK0_SET__underrun__set 1 -#define R_IRQ_MASK0_SET__underrun__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_SET__excessive_col__set 1 -#define R_IRQ_MASK0_SET__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__mdio__WIDTH 1 -#define R_IRQ_MASK0_SET__mdio__set 1 -#define R_IRQ_MASK0_SET__mdio__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_peri__set 1 -#define R_IRQ_MASK0_SET__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_data__set 1 -#define R_IRQ_MASK0_SET__par0_data__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ready__set 1 -#define R_IRQ_MASK0_SET__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__mio__WIDTH 1 -#define R_IRQ_MASK0_SET__mio__set 1 -#define R_IRQ_MASK0_SET__mio__nop 0 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 -#define R_IRQ_MASK0_SET__scsi0__set 1 -#define R_IRQ_MASK0_SET__scsi0__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer1__WIDTH 1 -#define R_IRQ_MASK0_SET__timer1__set 1 -#define R_IRQ_MASK0_SET__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 -#define R_IRQ_MASK0_SET__timer0__WIDTH 1 -#define R_IRQ_MASK0_SET__timer0__set 1 -#define R_IRQ_MASK0_SET__timer0__nop 0 - -#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 -#define R_IRQ_MASK1_RD__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa7__WIDTH 1 -#define R_IRQ_MASK1_RD__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa6__WIDTH 1 -#define R_IRQ_MASK1_RD__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa5__WIDTH 1 -#define R_IRQ_MASK1_RD__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa4__WIDTH 1 -#define R_IRQ_MASK1_RD__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa3__WIDTH 1 -#define R_IRQ_MASK1_RD__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa2__WIDTH 1 -#define R_IRQ_MASK1_RD__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa1__WIDTH 1 -#define R_IRQ_MASK1_RD__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 -#define R_IRQ_MASK1_RD__pa0__WIDTH 1 -#define R_IRQ_MASK1_RD__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__inactive 0 - -#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 -#define R_IRQ_MASK1_CLR__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 -#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__nop 0 - -#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int7__WIDTH 1 -#define R_IRQ_READ1__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int6__WIDTH 1 -#define R_IRQ_READ1__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int5__WIDTH 1 -#define R_IRQ_READ1__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int4__WIDTH 1 -#define R_IRQ_READ1__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int3__WIDTH 1 -#define R_IRQ_READ1__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int2__WIDTH 1 -#define R_IRQ_READ1__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int1__WIDTH 1 -#define R_IRQ_READ1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__sw_int0__WIDTH 1 -#define R_IRQ_READ1__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_READ1__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_peri__WIDTH 1 -#define R_IRQ_READ1__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_data__WIDTH 1 -#define R_IRQ_READ1__par1_data__active 1 -#define R_IRQ_READ1__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__par1_ready__WIDTH 1 -#define R_IRQ_READ1__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__scsi1__WIDTH 1 -#define R_IRQ_READ1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_ready__WIDTH 1 -#define R_IRQ_READ1__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser3_data__WIDTH 1 -#define R_IRQ_READ1__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_ready__WIDTH 1 -#define R_IRQ_READ1__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser2_data__WIDTH 1 -#define R_IRQ_READ1__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_ready__WIDTH 1 -#define R_IRQ_READ1__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser1_data__WIDTH 1 -#define R_IRQ_READ1__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_ready__WIDTH 1 -#define R_IRQ_READ1__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__ser0_data__WIDTH 1 -#define R_IRQ_READ1__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa7__WIDTH 1 -#define R_IRQ_READ1__pa7__active 1 -#define R_IRQ_READ1__pa7__inactive 0 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa6__WIDTH 1 -#define R_IRQ_READ1__pa6__active 1 -#define R_IRQ_READ1__pa6__inactive 0 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa5__WIDTH 1 -#define R_IRQ_READ1__pa5__active 1 -#define R_IRQ_READ1__pa5__inactive 0 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa4__WIDTH 1 -#define R_IRQ_READ1__pa4__active 1 -#define R_IRQ_READ1__pa4__inactive 0 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa3__WIDTH 1 -#define R_IRQ_READ1__pa3__active 1 -#define R_IRQ_READ1__pa3__inactive 0 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa2__WIDTH 1 -#define R_IRQ_READ1__pa2__active 1 -#define R_IRQ_READ1__pa2__inactive 0 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa1__WIDTH 1 -#define R_IRQ_READ1__pa1__active 1 -#define R_IRQ_READ1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__BITNR 0 -#define R_IRQ_READ1__pa0__WIDTH 1 -#define R_IRQ_READ1__pa0__active 1 -#define R_IRQ_READ1__pa0__inactive 0 - -#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int0__set 1 -#define R_IRQ_MASK1_SET__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ready__set 1 -#define R_IRQ_MASK1_SET__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 -#define R_IRQ_MASK1_SET__scsi1__set 1 -#define R_IRQ_MASK1_SET__scsi1__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_data__set 1 -#define R_IRQ_MASK1_SET__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa7__WIDTH 1 -#define R_IRQ_MASK1_SET__pa7__set 1 -#define R_IRQ_MASK1_SET__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa6__WIDTH 1 -#define R_IRQ_MASK1_SET__pa6__set 1 -#define R_IRQ_MASK1_SET__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa5__WIDTH 1 -#define R_IRQ_MASK1_SET__pa5__set 1 -#define R_IRQ_MASK1_SET__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa4__WIDTH 1 -#define R_IRQ_MASK1_SET__pa4__set 1 -#define R_IRQ_MASK1_SET__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa3__WIDTH 1 -#define R_IRQ_MASK1_SET__pa3__set 1 -#define R_IRQ_MASK1_SET__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa2__WIDTH 1 -#define R_IRQ_MASK1_SET__pa2__set 1 -#define R_IRQ_MASK1_SET__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa1__WIDTH 1 -#define R_IRQ_MASK1_SET__pa1__set 1 -#define R_IRQ_MASK1_SET__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 -#define R_IRQ_MASK1_SET__pa0__WIDTH 1 -#define R_IRQ_MASK1_SET__pa0__set 1 -#define R_IRQ_MASK1_SET__pa0__nop 0 - -#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 - -#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_eop__WIDTH 1 -#define R_IRQ_READ2__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma9_descr__WIDTH 1 -#define R_IRQ_READ2__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_eop__WIDTH 1 -#define R_IRQ_READ2__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma8_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_eop__WIDTH 1 -#define R_IRQ_READ2__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma7_descr__WIDTH 1 -#define R_IRQ_READ2__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_eop__WIDTH 1 -#define R_IRQ_READ2__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma6_descr__WIDTH 1 -#define R_IRQ_READ2__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_eop__WIDTH 1 -#define R_IRQ_READ2__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma5_descr__WIDTH 1 -#define R_IRQ_READ2__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_eop__WIDTH 1 -#define R_IRQ_READ2__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma4_descr__WIDTH 1 -#define R_IRQ_READ2__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_eop__WIDTH 1 -#define R_IRQ_READ2__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma3_descr__WIDTH 1 -#define R_IRQ_READ2__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_eop__WIDTH 1 -#define R_IRQ_READ2__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma2_descr__WIDTH 1 -#define R_IRQ_READ2__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_eop__WIDTH 1 -#define R_IRQ_READ2__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma1_descr__WIDTH 1 -#define R_IRQ_READ2__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_eop__WIDTH 1 -#define R_IRQ_READ2__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__BITNR 0 -#define R_IRQ_READ2__dma0_descr__WIDTH 1 -#define R_IRQ_READ2__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__nop 0 - -#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__usb__WIDTH 1 -#define R_VECT_MASK_RD__usb__active 1 -#define R_VECT_MASK_RD__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma9__WIDTH 1 -#define R_VECT_MASK_RD__dma9__active 1 -#define R_VECT_MASK_RD__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma8__WIDTH 1 -#define R_VECT_MASK_RD__dma8__active 1 -#define R_VECT_MASK_RD__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma7__WIDTH 1 -#define R_VECT_MASK_RD__dma7__active 1 -#define R_VECT_MASK_RD__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma6__WIDTH 1 -#define R_VECT_MASK_RD__dma6__active 1 -#define R_VECT_MASK_RD__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma5__WIDTH 1 -#define R_VECT_MASK_RD__dma5__active 1 -#define R_VECT_MASK_RD__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma4__WIDTH 1 -#define R_VECT_MASK_RD__dma4__active 1 -#define R_VECT_MASK_RD__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma3__WIDTH 1 -#define R_VECT_MASK_RD__dma3__active 1 -#define R_VECT_MASK_RD__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma2__WIDTH 1 -#define R_VECT_MASK_RD__dma2__active 1 -#define R_VECT_MASK_RD__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma1__WIDTH 1 -#define R_VECT_MASK_RD__dma1__active 1 -#define R_VECT_MASK_RD__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__dma0__WIDTH 1 -#define R_VECT_MASK_RD__dma0__active 1 -#define R_VECT_MASK_RD__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__pa__WIDTH 1 -#define R_VECT_MASK_RD__pa__active 1 -#define R_VECT_MASK_RD__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 -#define R_VECT_MASK_RD__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__sw__WIDTH 1 -#define R_VECT_MASK_RD__sw__active 1 -#define R_VECT_MASK_RD__sw__inactive 0 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__serial__WIDTH 1 -#define R_VECT_MASK_RD__serial__active 1 -#define R_VECT_MASK_RD__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__snmp__WIDTH 1 -#define R_VECT_MASK_RD__snmp__active 1 -#define R_VECT_MASK_RD__snmp__inactive 0 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__network__WIDTH 1 -#define R_VECT_MASK_RD__network__active 1 -#define R_VECT_MASK_RD__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__scsi1__WIDTH 1 -#define R_VECT_MASK_RD__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__par1__WIDTH 1 -#define R_VECT_MASK_RD__par1__active 1 -#define R_VECT_MASK_RD__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__scsi0__WIDTH 1 -#define R_VECT_MASK_RD__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__par0__WIDTH 1 -#define R_VECT_MASK_RD__par0__active 1 -#define R_VECT_MASK_RD__par0__inactive 0 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__ata__WIDTH 1 -#define R_VECT_MASK_RD__ata__active 1 -#define R_VECT_MASK_RD__ata__inactive 0 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__mio__WIDTH 1 -#define R_VECT_MASK_RD__mio__active 1 -#define R_VECT_MASK_RD__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer1__WIDTH 1 -#define R_VECT_MASK_RD__timer1__active 1 -#define R_VECT_MASK_RD__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__timer0__WIDTH 1 -#define R_VECT_MASK_RD__timer0__active 1 -#define R_VECT_MASK_RD__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__nmi__WIDTH 1 -#define R_VECT_MASK_RD__nmi__active 1 -#define R_VECT_MASK_RD__nmi__inactive 0 -#define R_VECT_MASK_RD__some__BITNR 0 -#define R_VECT_MASK_RD__some__WIDTH 1 -#define R_VECT_MASK_RD__some__active 1 -#define R_VECT_MASK_RD__some__inactive 0 - -#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__usb__WIDTH 1 -#define R_VECT_MASK_CLR__usb__clr 1 -#define R_VECT_MASK_CLR__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma9__WIDTH 1 -#define R_VECT_MASK_CLR__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma8__WIDTH 1 -#define R_VECT_MASK_CLR__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma7__WIDTH 1 -#define R_VECT_MASK_CLR__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma6__WIDTH 1 -#define R_VECT_MASK_CLR__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma5__WIDTH 1 -#define R_VECT_MASK_CLR__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma4__WIDTH 1 -#define R_VECT_MASK_CLR__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma3__WIDTH 1 -#define R_VECT_MASK_CLR__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma2__WIDTH 1 -#define R_VECT_MASK_CLR__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma1__WIDTH 1 -#define R_VECT_MASK_CLR__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__dma0__WIDTH 1 -#define R_VECT_MASK_CLR__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__pa__WIDTH 1 -#define R_VECT_MASK_CLR__pa__clr 1 -#define R_VECT_MASK_CLR__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 -#define R_VECT_MASK_CLR__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__sw__WIDTH 1 -#define R_VECT_MASK_CLR__sw__clr 1 -#define R_VECT_MASK_CLR__sw__nop 0 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__serial__WIDTH 1 -#define R_VECT_MASK_CLR__serial__clr 1 -#define R_VECT_MASK_CLR__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__snmp__WIDTH 1 -#define R_VECT_MASK_CLR__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__nop 0 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__network__WIDTH 1 -#define R_VECT_MASK_CLR__network__clr 1 -#define R_VECT_MASK_CLR__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__scsi1__WIDTH 1 -#define R_VECT_MASK_CLR__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__par1__WIDTH 1 -#define R_VECT_MASK_CLR__par1__clr 1 -#define R_VECT_MASK_CLR__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__scsi0__WIDTH 1 -#define R_VECT_MASK_CLR__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__par0__WIDTH 1 -#define R_VECT_MASK_CLR__par0__clr 1 -#define R_VECT_MASK_CLR__par0__nop 0 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__ata__WIDTH 1 -#define R_VECT_MASK_CLR__ata__clr 1 -#define R_VECT_MASK_CLR__ata__nop 0 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__mio__WIDTH 1 -#define R_VECT_MASK_CLR__mio__clr 1 -#define R_VECT_MASK_CLR__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer1__WIDTH 1 -#define R_VECT_MASK_CLR__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__timer0__WIDTH 1 -#define R_VECT_MASK_CLR__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__nmi__WIDTH 1 -#define R_VECT_MASK_CLR__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nop 0 -#define R_VECT_MASK_CLR__some__BITNR 0 -#define R_VECT_MASK_CLR__some__WIDTH 1 -#define R_VECT_MASK_CLR__some__clr 1 -#define R_VECT_MASK_CLR__some__nop 0 - -#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__usb__WIDTH 1 -#define R_VECT_READ__usb__active 1 -#define R_VECT_READ__usb__inactive 0 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma9__WIDTH 1 -#define R_VECT_READ__dma9__active 1 -#define R_VECT_READ__dma9__inactive 0 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma8__WIDTH 1 -#define R_VECT_READ__dma8__active 1 -#define R_VECT_READ__dma8__inactive 0 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma7__WIDTH 1 -#define R_VECT_READ__dma7__active 1 -#define R_VECT_READ__dma7__inactive 0 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma6__WIDTH 1 -#define R_VECT_READ__dma6__active 1 -#define R_VECT_READ__dma6__inactive 0 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma5__WIDTH 1 -#define R_VECT_READ__dma5__active 1 -#define R_VECT_READ__dma5__inactive 0 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma4__WIDTH 1 -#define R_VECT_READ__dma4__active 1 -#define R_VECT_READ__dma4__inactive 0 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma3__WIDTH 1 -#define R_VECT_READ__dma3__active 1 -#define R_VECT_READ__dma3__inactive 0 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma2__WIDTH 1 -#define R_VECT_READ__dma2__active 1 -#define R_VECT_READ__dma2__inactive 0 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma1__WIDTH 1 -#define R_VECT_READ__dma1__active 1 -#define R_VECT_READ__dma1__inactive 0 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__dma0__WIDTH 1 -#define R_VECT_READ__dma0__active 1 -#define R_VECT_READ__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma1__WIDTH 1 -#define R_VECT_READ__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__ext_dma0__WIDTH 1 -#define R_VECT_READ__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__inactive 0 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__pa__WIDTH 1 -#define R_VECT_READ__pa__active 1 -#define R_VECT_READ__pa__inactive 0 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__irq_intnr__WIDTH 1 -#define R_VECT_READ__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__inactive 0 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__sw__WIDTH 1 -#define R_VECT_READ__sw__active 1 -#define R_VECT_READ__sw__inactive 0 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__serial__WIDTH 1 -#define R_VECT_READ__serial__active 1 -#define R_VECT_READ__serial__inactive 0 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__snmp__WIDTH 1 -#define R_VECT_READ__snmp__active 1 -#define R_VECT_READ__snmp__inactive 0 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__network__WIDTH 1 -#define R_VECT_READ__network__active 1 -#define R_VECT_READ__network__inactive 0 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__scsi1__WIDTH 1 -#define R_VECT_READ__scsi1__active 1 -#define R_VECT_READ__scsi1__inactive 0 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__par1__WIDTH 1 -#define R_VECT_READ__par1__active 1 -#define R_VECT_READ__par1__inactive 0 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__scsi0__WIDTH 1 -#define R_VECT_READ__scsi0__active 1 -#define R_VECT_READ__scsi0__inactive 0 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__par0__WIDTH 1 -#define R_VECT_READ__par0__active 1 -#define R_VECT_READ__par0__inactive 0 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__ata__WIDTH 1 -#define R_VECT_READ__ata__active 1 -#define R_VECT_READ__ata__inactive 0 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__mio__WIDTH 1 -#define R_VECT_READ__mio__active 1 -#define R_VECT_READ__mio__inactive 0 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer1__WIDTH 1 -#define R_VECT_READ__timer1__active 1 -#define R_VECT_READ__timer1__inactive 0 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__timer0__WIDTH 1 -#define R_VECT_READ__timer0__active 1 -#define R_VECT_READ__timer0__inactive 0 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__nmi__WIDTH 1 -#define R_VECT_READ__nmi__active 1 -#define R_VECT_READ__nmi__inactive 0 -#define R_VECT_READ__some__BITNR 0 -#define R_VECT_READ__some__WIDTH 1 -#define R_VECT_READ__some__active 1 -#define R_VECT_READ__some__inactive 0 - -#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__usb__WIDTH 1 -#define R_VECT_MASK_SET__usb__set 1 -#define R_VECT_MASK_SET__usb__nop 0 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma9__WIDTH 1 -#define R_VECT_MASK_SET__dma9__set 1 -#define R_VECT_MASK_SET__dma9__nop 0 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma8__WIDTH 1 -#define R_VECT_MASK_SET__dma8__set 1 -#define R_VECT_MASK_SET__dma8__nop 0 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma7__WIDTH 1 -#define R_VECT_MASK_SET__dma7__set 1 -#define R_VECT_MASK_SET__dma7__nop 0 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma6__WIDTH 1 -#define R_VECT_MASK_SET__dma6__set 1 -#define R_VECT_MASK_SET__dma6__nop 0 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma5__WIDTH 1 -#define R_VECT_MASK_SET__dma5__set 1 -#define R_VECT_MASK_SET__dma5__nop 0 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma4__WIDTH 1 -#define R_VECT_MASK_SET__dma4__set 1 -#define R_VECT_MASK_SET__dma4__nop 0 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma3__WIDTH 1 -#define R_VECT_MASK_SET__dma3__set 1 -#define R_VECT_MASK_SET__dma3__nop 0 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma2__WIDTH 1 -#define R_VECT_MASK_SET__dma2__set 1 -#define R_VECT_MASK_SET__dma2__nop 0 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma1__WIDTH 1 -#define R_VECT_MASK_SET__dma1__set 1 -#define R_VECT_MASK_SET__dma1__nop 0 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__dma0__WIDTH 1 -#define R_VECT_MASK_SET__dma0__set 1 -#define R_VECT_MASK_SET__dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma0__set 1 -#define R_VECT_MASK_SET__ext_dma0__nop 0 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__pa__WIDTH 1 -#define R_VECT_MASK_SET__pa__set 1 -#define R_VECT_MASK_SET__pa__nop 0 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 -#define R_VECT_MASK_SET__irq_intnr__set 1 -#define R_VECT_MASK_SET__irq_intnr__nop 0 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__sw__WIDTH 1 -#define R_VECT_MASK_SET__sw__set 1 -#define R_VECT_MASK_SET__sw__nop 0 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__serial__WIDTH 1 -#define R_VECT_MASK_SET__serial__set 1 -#define R_VECT_MASK_SET__serial__nop 0 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__snmp__WIDTH 1 -#define R_VECT_MASK_SET__snmp__set 1 -#define R_VECT_MASK_SET__snmp__nop 0 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__network__WIDTH 1 -#define R_VECT_MASK_SET__network__set 1 -#define R_VECT_MASK_SET__network__nop 0 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__scsi1__WIDTH 1 -#define R_VECT_MASK_SET__scsi1__set 1 -#define R_VECT_MASK_SET__scsi1__nop 0 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__par1__WIDTH 1 -#define R_VECT_MASK_SET__par1__set 1 -#define R_VECT_MASK_SET__par1__nop 0 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__scsi0__WIDTH 1 -#define R_VECT_MASK_SET__scsi0__set 1 -#define R_VECT_MASK_SET__scsi0__nop 0 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__par0__WIDTH 1 -#define R_VECT_MASK_SET__par0__set 1 -#define R_VECT_MASK_SET__par0__nop 0 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__ata__WIDTH 1 -#define R_VECT_MASK_SET__ata__set 1 -#define R_VECT_MASK_SET__ata__nop 0 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__mio__WIDTH 1 -#define R_VECT_MASK_SET__mio__set 1 -#define R_VECT_MASK_SET__mio__nop 0 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer1__WIDTH 1 -#define R_VECT_MASK_SET__timer1__set 1 -#define R_VECT_MASK_SET__timer1__nop 0 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__timer0__WIDTH 1 -#define R_VECT_MASK_SET__timer0__set 1 -#define R_VECT_MASK_SET__timer0__nop 0 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__nmi__WIDTH 1 -#define R_VECT_MASK_SET__nmi__set 1 -#define R_VECT_MASK_SET__nmi__nop 0 -#define R_VECT_MASK_SET__some__BITNR 0 -#define R_VECT_MASK_SET__some__WIDTH 1 -#define R_VECT_MASK_SET__some__set 1 -#define R_VECT_MASK_SET__some__nop 0 - -/* -!* DMA registers -!*/ - -#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch9_eop__WIDTH 1 -#define R_SET_EOP__ch9_eop__set 1 -#define R_SET_EOP__ch9_eop__nop 0 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch7_eop__WIDTH 1 -#define R_SET_EOP__ch7_eop__set 1 -#define R_SET_EOP__ch7_eop__nop 0 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch5_eop__WIDTH 1 -#define R_SET_EOP__ch5_eop__set 1 -#define R_SET_EOP__ch5_eop__nop 0 -#define R_SET_EOP__ch3_eop__BITNR 0 -#define R_SET_EOP__ch3_eop__WIDTH 1 -#define R_SET_EOP__ch3_eop__set 1 -#define R_SET_EOP__ch3_eop__nop 0 - -#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__hw__WIDTH 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 -#define R_DMA_CH0_HWSW__sw__WIDTH 16 - -#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__descr__BITNR 0 -#define R_DMA_CH0_DESCR__descr__WIDTH 32 - -#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__next__BITNR 0 -#define R_DMA_CH0_NEXT__next__WIDTH 32 - -#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__buf__BITNR 0 -#define R_DMA_CH0_BUF__buf__WIDTH 32 - -#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__first__BITNR 0 -#define R_DMA_CH0_FIRST__first__WIDTH 32 - -#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__cmd__BITNR 0 -#define R_DMA_CH0_CMD__cmd__WIDTH 3 -#define R_DMA_CH0_CMD__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__start 1 -#define R_DMA_CH0_CMD__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__reset 4 - -#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__avail__BITNR 0 -#define R_DMA_CH0_STATUS__avail__WIDTH 7 - -#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__hw__WIDTH 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 -#define R_DMA_CH1_HWSW__sw__WIDTH 16 - -#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__descr__BITNR 0 -#define R_DMA_CH1_DESCR__descr__WIDTH 32 - -#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__next__BITNR 0 -#define R_DMA_CH1_NEXT__next__WIDTH 32 - -#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__buf__BITNR 0 -#define R_DMA_CH1_BUF__buf__WIDTH 32 - -#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__first__BITNR 0 -#define R_DMA_CH1_FIRST__first__WIDTH 32 - -#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__cmd__BITNR 0 -#define R_DMA_CH1_CMD__cmd__WIDTH 3 -#define R_DMA_CH1_CMD__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__start 1 -#define R_DMA_CH1_CMD__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__reset 4 - -#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__avail__BITNR 0 -#define R_DMA_CH1_STATUS__avail__WIDTH 7 - -#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__hw__WIDTH 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 -#define R_DMA_CH2_HWSW__sw__WIDTH 16 - -#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__descr__BITNR 0 -#define R_DMA_CH2_DESCR__descr__WIDTH 32 - -#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__next__BITNR 0 -#define R_DMA_CH2_NEXT__next__WIDTH 32 - -#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__buf__BITNR 0 -#define R_DMA_CH2_BUF__buf__WIDTH 32 - -#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__first__BITNR 0 -#define R_DMA_CH2_FIRST__first__WIDTH 32 - -#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__cmd__BITNR 0 -#define R_DMA_CH2_CMD__cmd__WIDTH 3 -#define R_DMA_CH2_CMD__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__start 1 -#define R_DMA_CH2_CMD__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__reset 4 - -#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__avail__BITNR 0 -#define R_DMA_CH2_STATUS__avail__WIDTH 7 - -#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__hw__WIDTH 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 -#define R_DMA_CH3_HWSW__sw__WIDTH 16 - -#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__descr__BITNR 0 -#define R_DMA_CH3_DESCR__descr__WIDTH 32 - -#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__next__BITNR 0 -#define R_DMA_CH3_NEXT__next__WIDTH 32 - -#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__buf__BITNR 0 -#define R_DMA_CH3_BUF__buf__WIDTH 32 - -#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__first__BITNR 0 -#define R_DMA_CH3_FIRST__first__WIDTH 32 - -#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__cmd__BITNR 0 -#define R_DMA_CH3_CMD__cmd__WIDTH 3 -#define R_DMA_CH3_CMD__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__start 1 -#define R_DMA_CH3_CMD__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__reset 4 - -#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__avail__BITNR 0 -#define R_DMA_CH3_STATUS__avail__WIDTH 7 - -#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__hw__WIDTH 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 -#define R_DMA_CH4_HWSW__sw__WIDTH 16 - -#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__descr__BITNR 0 -#define R_DMA_CH4_DESCR__descr__WIDTH 32 - -#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__next__BITNR 0 -#define R_DMA_CH4_NEXT__next__WIDTH 32 - -#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__buf__BITNR 0 -#define R_DMA_CH4_BUF__buf__WIDTH 32 - -#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__first__BITNR 0 -#define R_DMA_CH4_FIRST__first__WIDTH 32 - -#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__cmd__BITNR 0 -#define R_DMA_CH4_CMD__cmd__WIDTH 3 -#define R_DMA_CH4_CMD__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__start 1 -#define R_DMA_CH4_CMD__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__reset 4 - -#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__avail__BITNR 0 -#define R_DMA_CH4_STATUS__avail__WIDTH 7 - -#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__hw__WIDTH 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 -#define R_DMA_CH5_HWSW__sw__WIDTH 16 - -#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__descr__BITNR 0 -#define R_DMA_CH5_DESCR__descr__WIDTH 32 - -#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__next__BITNR 0 -#define R_DMA_CH5_NEXT__next__WIDTH 32 - -#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__buf__BITNR 0 -#define R_DMA_CH5_BUF__buf__WIDTH 32 - -#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__first__BITNR 0 -#define R_DMA_CH5_FIRST__first__WIDTH 32 - -#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__cmd__BITNR 0 -#define R_DMA_CH5_CMD__cmd__WIDTH 3 -#define R_DMA_CH5_CMD__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__start 1 -#define R_DMA_CH5_CMD__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__reset 4 - -#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__avail__BITNR 0 -#define R_DMA_CH5_STATUS__avail__WIDTH 7 - -#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__hw__WIDTH 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 -#define R_DMA_CH6_HWSW__sw__WIDTH 16 - -#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__descr__BITNR 0 -#define R_DMA_CH6_DESCR__descr__WIDTH 32 - -#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__next__BITNR 0 -#define R_DMA_CH6_NEXT__next__WIDTH 32 - -#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__buf__BITNR 0 -#define R_DMA_CH6_BUF__buf__WIDTH 32 - -#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__first__BITNR 0 -#define R_DMA_CH6_FIRST__first__WIDTH 32 - -#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__cmd__BITNR 0 -#define R_DMA_CH6_CMD__cmd__WIDTH 3 -#define R_DMA_CH6_CMD__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__start 1 -#define R_DMA_CH6_CMD__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__reset 4 - -#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__avail__BITNR 0 -#define R_DMA_CH6_STATUS__avail__WIDTH 7 - -#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__hw__WIDTH 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 -#define R_DMA_CH7_HWSW__sw__WIDTH 16 - -#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__descr__BITNR 0 -#define R_DMA_CH7_DESCR__descr__WIDTH 32 - -#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__next__BITNR 0 -#define R_DMA_CH7_NEXT__next__WIDTH 32 - -#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__buf__BITNR 0 -#define R_DMA_CH7_BUF__buf__WIDTH 32 - -#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__first__BITNR 0 -#define R_DMA_CH7_FIRST__first__WIDTH 32 - -#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__cmd__BITNR 0 -#define R_DMA_CH7_CMD__cmd__WIDTH 3 -#define R_DMA_CH7_CMD__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__start 1 -#define R_DMA_CH7_CMD__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__reset 4 - -#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__avail__BITNR 0 -#define R_DMA_CH7_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__hw__WIDTH 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 -#define R_DMA_CH8_HWSW__sw__WIDTH 16 - -#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__descr__BITNR 0 -#define R_DMA_CH8_DESCR__descr__WIDTH 32 - -#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__next__BITNR 0 -#define R_DMA_CH8_NEXT__next__WIDTH 32 - -#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__buf__BITNR 0 -#define R_DMA_CH8_BUF__buf__WIDTH 32 - -#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__first__BITNR 0 -#define R_DMA_CH8_FIRST__first__WIDTH 32 - -#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__cmd__BITNR 0 -#define R_DMA_CH8_CMD__cmd__WIDTH 3 -#define R_DMA_CH8_CMD__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__start 1 -#define R_DMA_CH8_CMD__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__reset 4 - -#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__avail__BITNR 0 -#define R_DMA_CH8_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__sub__BITNR 0 -#define R_DMA_CH8_SUB__sub__WIDTH 32 - -#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__nep__BITNR 0 -#define R_DMA_CH8_NEP__nep__WIDTH 32 - -#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB0_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB1_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB2_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB3_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__hw__WIDTH 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 -#define R_DMA_CH9_HWSW__sw__WIDTH 16 - -#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__descr__BITNR 0 -#define R_DMA_CH9_DESCR__descr__WIDTH 32 - -#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__next__BITNR 0 -#define R_DMA_CH9_NEXT__next__WIDTH 32 - -#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__buf__BITNR 0 -#define R_DMA_CH9_BUF__buf__WIDTH 32 - -#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__first__BITNR 0 -#define R_DMA_CH9_FIRST__first__WIDTH 32 - -#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__cmd__BITNR 0 -#define R_DMA_CH9_CMD__cmd__WIDTH 3 -#define R_DMA_CH9_CMD__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__start 1 -#define R_DMA_CH9_CMD__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__reset 4 - -#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__avail__BITNR 0 -#define R_DMA_CH9_STATUS__avail__WIDTH 7 - -/* -!* Test mode registers -!*/ - -#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__single_step__WIDTH 1 -#define R_TEST_MODE__single_step__on 1 -#define R_TEST_MODE__single_step__off 0 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_wr__WIDTH 1 -#define R_TEST_MODE__step_wr__on 1 -#define R_TEST_MODE__step_wr__off 0 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_rd__WIDTH 1 -#define R_TEST_MODE__step_rd__on 1 -#define R_TEST_MODE__step_rd__off 0 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__step_fetch__WIDTH 1 -#define R_TEST_MODE__step_fetch__on 1 -#define R_TEST_MODE__step_fetch__off 0 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__mmu_test__WIDTH 1 -#define R_TEST_MODE__mmu_test__on 1 -#define R_TEST_MODE__mmu_test__off 0 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__usb_test__WIDTH 1 -#define R_TEST_MODE__usb_test__on 1 -#define R_TEST_MODE__usb_test__off 0 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__scsi_timer_test__WIDTH 1 -#define R_TEST_MODE__scsi_timer_test__on 1 -#define R_TEST_MODE__scsi_timer_test__off 0 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__backoff__WIDTH 1 -#define R_TEST_MODE__backoff__on 1 -#define R_TEST_MODE__backoff__off 0 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_test__WIDTH 1 -#define R_TEST_MODE__snmp_test__on 1 -#define R_TEST_MODE__snmp_test__off 0 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__snmp_inc__WIDTH 1 -#define R_TEST_MODE__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__ser_loop__WIDTH 1 -#define R_TEST_MODE__ser_loop__on 1 -#define R_TEST_MODE__ser_loop__off 0 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__baudrate__WIDTH 1 -#define R_TEST_MODE__baudrate__on 1 -#define R_TEST_MODE__baudrate__off 0 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__timer__WIDTH 2 -#define R_TEST_MODE__timer__off 0 -#define R_TEST_MODE__timer__even 1 -#define R_TEST_MODE__timer__odd 2 -#define R_TEST_MODE__timer__all 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__cache_test__WIDTH 1 -#define R_TEST_MODE__cache_test__normal 0 -#define R_TEST_MODE__cache_test__test 1 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__tag_test__WIDTH 1 -#define R_TEST_MODE__tag_test__normal 0 -#define R_TEST_MODE__tag_test__test 1 -#define R_TEST_MODE__cache_enable__BITNR 0 -#define R_TEST_MODE__cache_enable__WIDTH 1 -#define R_TEST_MODE__cache_enable__enable 1 -#define R_TEST_MODE__cache_enable__disable 0 - -#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__single_step__WIDTH 1 -#define R_SINGLE_STEP__single_step__on 1 -#define R_SINGLE_STEP__single_step__off 0 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_wr__WIDTH 1 -#define R_SINGLE_STEP__step_wr__on 1 -#define R_SINGLE_STEP__step_wr__off 0 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_rd__WIDTH 1 -#define R_SINGLE_STEP__step_rd__on 1 -#define R_SINGLE_STEP__step_rd__off 0 -#define R_SINGLE_STEP__step_fetch__BITNR 0 -#define R_SINGLE_STEP__step_fetch__WIDTH 1 -#define R_SINGLE_STEP__step_fetch__on 1 -#define R_SINGLE_STEP__step_fetch__off 0 - -/* -!* USB interface control registers -!*/ - -#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__major__WIDTH 4 -#define R_USB_REVISION__minor__BITNR 0 -#define R_USB_REVISION__minor__WIDTH 4 - -#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_sel__WIDTH 2 -#define R_USB_COMMAND__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port2 2 -#define R_USB_COMMAND__port_sel__both 3 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__port_cmd__WIDTH 2 -#define R_USB_COMMAND__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__suspend 2 -#define R_USB_COMMAND__port_cmd__resume 3 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__busy__WIDTH 1 -#define R_USB_COMMAND__busy__no 0 -#define R_USB_COMMAND__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__reset 1 -#define R_USB_COMMAND__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__host_stop 7 - -#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 -#define R_USB_COMMAND_DEV__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 -#define R_USB_COMMAND_DEV__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__busy__WIDTH 1 -#define R_USB_COMMAND_DEV__busy__no 0 -#define R_USB_COMMAND_DEV__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 - -#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__ourun__WIDTH 1 -#define R_USB_STATUS__ourun__no 0 -#define R_USB_STATUS__ourun__yes 1 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__perror__WIDTH 1 -#define R_USB_STATUS__perror__no 0 -#define R_USB_STATUS__perror__yes 1 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__device_mode__WIDTH 1 -#define R_USB_STATUS__device_mode__no 0 -#define R_USB_STATUS__device_mode__yes 1 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__host_mode__WIDTH 1 -#define R_USB_STATUS__host_mode__no 0 -#define R_USB_STATUS__host_mode__yes 1 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__started__WIDTH 1 -#define R_USB_STATUS__started__no 0 -#define R_USB_STATUS__started__yes 1 -#define R_USB_STATUS__running__BITNR 0 -#define R_USB_STATUS__running__WIDTH 1 -#define R_USB_STATUS__running__no 0 -#define R_USB_STATUS__running__yes 1 - -#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 - -#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__sof__WIDTH 1 -#define R_USB_IRQ_READ__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__pend 1 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__port_status__WIDTH 1 -#define R_USB_IRQ_READ__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 - -#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 - -#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__value__BITNR 0 -#define R_USB_FM_NUMBER__value__WIDTH 32 - -#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__fixed__WIDTH 8 -#define R_USB_FM_INTERVAL__adj__BITNR 0 -#define R_USB_FM_INTERVAL__adj__WIDTH 6 - -#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__value__BITNR 0 -#define R_USB_FM_REMAINING__value__WIDTH 14 - -#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__value__BITNR 0 -#define R_USB_FM_PSTART__value__WIDTH 14 - -#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble2__WIDTH 1 -#define R_USB_RH_STATUS__babble2__no 0 -#define R_USB_RH_STATUS__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__babble1__WIDTH 1 -#define R_USB_RH_STATUS__babble1__no 0 -#define R_USB_RH_STATUS__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus1__WIDTH 2 -#define R_USB_RH_STATUS__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__bus2__WIDTH 2 -#define R_USB_RH_STATUS__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__SE1 3 -#define R_USB_RH_STATUS__nports__BITNR 0 -#define R_USB_RH_STATUS__nports__WIDTH 2 - -#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__yes 1 - -#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__yes 1 - -#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__value__BITNR 0 -#define R_USB_EPT_INDEX__value__WIDTH 5 - -#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__valid__WIDTH 1 -#define R_USB_EPT_DATA__valid__no 0 -#define R_USB_EPT_DATA__valid__yes 1 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__hold__WIDTH 1 -#define R_USB_EPT_DATA__hold__no 0 -#define R_USB_EPT_DATA__hold__yes 1 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__error_count_in__WIDTH 2 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__t_in__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__low_speed__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__yes 1 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__port__WIDTH 2 -#define R_USB_EPT_DATA__port__any 0 -#define R_USB_EPT_DATA__port__p1 1 -#define R_USB_EPT_DATA__port__p2 2 -#define R_USB_EPT_DATA__port__undef 3 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__error_code__WIDTH 2 -#define R_USB_EPT_DATA__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__stall 1 -#define R_USB_EPT_DATA__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__buffer_error 3 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__t_out__WIDTH 1 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__error_count_out__WIDTH 2 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__max_len__WIDTH 7 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__ep__WIDTH 4 -#define R_USB_EPT_DATA__dev__BITNR 0 -#define R_USB_EPT_DATA__dev__WIDTH 7 - -#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 -#define R_USB_EPT_DATA_ISO__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__port__WIDTH 2 -#define R_USB_EPT_DATA_ISO__port__any 0 -#define R_USB_EPT_DATA_ISO__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 -#define R_USB_EPT_DATA_ISO__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__stall 1 -#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 -#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 - -#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 -#define R_USB_EPT_DATA_DEV__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 -#define R_USB_EPT_DATA_DEV__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 -#define R_USB_EPT_DATA_DEV__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 -#define R_USB_EPT_DATA_DEV__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__yes 1 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__port__WIDTH 2 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__t__WIDTH 1 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 -#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 - -#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__value__BITNR 0 -#define R_USB_SNMP_TERROR__value__WIDTH 32 - -#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__value__BITNR 0 -#define R_USB_EPID_ATTN__value__WIDTH 32 - -#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) -#define R_USB_PORT1_DISABLE__disable__BITNR 0 -#define R_USB_PORT1_DISABLE__disable__WIDTH 1 -#define R_USB_PORT1_DISABLE__disable__yes 0 -#define R_USB_PORT1_DISABLE__disable__no 1 - -#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) -#define R_USB_PORT2_DISABLE__disable__BITNR 0 -#define R_USB_PORT2_DISABLE__disable__WIDTH 1 -#define R_USB_PORT2_DISABLE__disable__yes 0 -#define R_USB_PORT2_DISABLE__disable__no 1 - -/* -!* MMU registers -!*/ - -#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__mmu_enable__WIDTH 1 -#define R_MMU_CONFIG__mmu_enable__enable 1 -#define R_MMU_CONFIG__mmu_enable__disable 0 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__inv_excp__WIDTH 1 -#define R_MMU_CONFIG__inv_excp__enable 1 -#define R_MMU_CONFIG__inv_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__acc_excp__WIDTH 1 -#define R_MMU_CONFIG__acc_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__disable 0 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__we_excp__WIDTH 1 -#define R_MMU_CONFIG__we_excp__enable 1 -#define R_MMU_CONFIG__we_excp__disable 0 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_f__WIDTH 1 -#define R_MMU_CONFIG__seg_f__seg 1 -#define R_MMU_CONFIG__seg_f__page 0 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_e__WIDTH 1 -#define R_MMU_CONFIG__seg_e__seg 1 -#define R_MMU_CONFIG__seg_e__page 0 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_d__WIDTH 1 -#define R_MMU_CONFIG__seg_d__seg 1 -#define R_MMU_CONFIG__seg_d__page 0 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_c__WIDTH 1 -#define R_MMU_CONFIG__seg_c__seg 1 -#define R_MMU_CONFIG__seg_c__page 0 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_b__WIDTH 1 -#define R_MMU_CONFIG__seg_b__seg 1 -#define R_MMU_CONFIG__seg_b__page 0 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_a__WIDTH 1 -#define R_MMU_CONFIG__seg_a__seg 1 -#define R_MMU_CONFIG__seg_a__page 0 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_9__WIDTH 1 -#define R_MMU_CONFIG__seg_9__seg 1 -#define R_MMU_CONFIG__seg_9__page 0 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_8__WIDTH 1 -#define R_MMU_CONFIG__seg_8__seg 1 -#define R_MMU_CONFIG__seg_8__page 0 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_7__WIDTH 1 -#define R_MMU_CONFIG__seg_7__seg 1 -#define R_MMU_CONFIG__seg_7__page 0 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_6__WIDTH 1 -#define R_MMU_CONFIG__seg_6__seg 1 -#define R_MMU_CONFIG__seg_6__page 0 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_5__WIDTH 1 -#define R_MMU_CONFIG__seg_5__seg 1 -#define R_MMU_CONFIG__seg_5__page 0 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_4__WIDTH 1 -#define R_MMU_CONFIG__seg_4__seg 1 -#define R_MMU_CONFIG__seg_4__page 0 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_3__WIDTH 1 -#define R_MMU_CONFIG__seg_3__seg 1 -#define R_MMU_CONFIG__seg_3__page 0 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_2__WIDTH 1 -#define R_MMU_CONFIG__seg_2__seg 1 -#define R_MMU_CONFIG__seg_2__page 0 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_1__WIDTH 1 -#define R_MMU_CONFIG__seg_1__seg 1 -#define R_MMU_CONFIG__seg_1__page 0 -#define R_MMU_CONFIG__seg_0__BITNR 0 -#define R_MMU_CONFIG__seg_0__WIDTH 1 -#define R_MMU_CONFIG__seg_0__seg 1 -#define R_MMU_CONFIG__seg_0__page 0 - -#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_f__WIDTH 1 -#define R_MMU_KSEG__seg_f__seg 1 -#define R_MMU_KSEG__seg_f__page 0 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_e__WIDTH 1 -#define R_MMU_KSEG__seg_e__seg 1 -#define R_MMU_KSEG__seg_e__page 0 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_d__WIDTH 1 -#define R_MMU_KSEG__seg_d__seg 1 -#define R_MMU_KSEG__seg_d__page 0 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_c__WIDTH 1 -#define R_MMU_KSEG__seg_c__seg 1 -#define R_MMU_KSEG__seg_c__page 0 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_b__WIDTH 1 -#define R_MMU_KSEG__seg_b__seg 1 -#define R_MMU_KSEG__seg_b__page 0 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_a__WIDTH 1 -#define R_MMU_KSEG__seg_a__seg 1 -#define R_MMU_KSEG__seg_a__page 0 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_9__WIDTH 1 -#define R_MMU_KSEG__seg_9__seg 1 -#define R_MMU_KSEG__seg_9__page 0 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_8__WIDTH 1 -#define R_MMU_KSEG__seg_8__seg 1 -#define R_MMU_KSEG__seg_8__page 0 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_7__WIDTH 1 -#define R_MMU_KSEG__seg_7__seg 1 -#define R_MMU_KSEG__seg_7__page 0 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_6__WIDTH 1 -#define R_MMU_KSEG__seg_6__seg 1 -#define R_MMU_KSEG__seg_6__page 0 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_5__WIDTH 1 -#define R_MMU_KSEG__seg_5__seg 1 -#define R_MMU_KSEG__seg_5__page 0 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_4__WIDTH 1 -#define R_MMU_KSEG__seg_4__seg 1 -#define R_MMU_KSEG__seg_4__page 0 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_3__WIDTH 1 -#define R_MMU_KSEG__seg_3__seg 1 -#define R_MMU_KSEG__seg_3__page 0 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_2__WIDTH 1 -#define R_MMU_KSEG__seg_2__seg 1 -#define R_MMU_KSEG__seg_2__page 0 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_1__WIDTH 1 -#define R_MMU_KSEG__seg_1__seg 1 -#define R_MMU_KSEG__seg_1__page 0 -#define R_MMU_KSEG__seg_0__BITNR 0 -#define R_MMU_KSEG__seg_0__WIDTH 1 -#define R_MMU_KSEG__seg_0__seg 1 -#define R_MMU_KSEG__seg_0__page 0 - -#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__inv_excp__WIDTH 1 -#define R_MMU_CTRL__inv_excp__enable 1 -#define R_MMU_CTRL__inv_excp__disable 0 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__acc_excp__WIDTH 1 -#define R_MMU_CTRL__acc_excp__enable 1 -#define R_MMU_CTRL__acc_excp__disable 0 -#define R_MMU_CTRL__we_excp__BITNR 0 -#define R_MMU_CTRL__we_excp__WIDTH 1 -#define R_MMU_CTRL__we_excp__enable 1 -#define R_MMU_CTRL__we_excp__disable 0 - -#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) -#define R_MMU_ENABLE__mmu_enable__BITNR 7 -#define R_MMU_ENABLE__mmu_enable__WIDTH 1 -#define R_MMU_ENABLE__mmu_enable__enable 1 -#define R_MMU_ENABLE__mmu_enable__disable 0 - -#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_7__WIDTH 4 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_6__WIDTH 4 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_5__WIDTH 4 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_4__WIDTH 4 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_3__WIDTH 4 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_2__WIDTH 4 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_1__WIDTH 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 -#define R_MMU_KBASE_LO__base_0__WIDTH 4 - -#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_f__WIDTH 4 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_e__WIDTH 4 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_d__WIDTH 4 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_c__WIDTH 4 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_b__WIDTH 4 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_a__WIDTH 4 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_9__WIDTH 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 -#define R_MMU_KBASE_HI__base_8__WIDTH 4 - -#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__page_id__BITNR 0 -#define R_MMU_CONTEXT__page_id__WIDTH 6 - -#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__vpn__WIDTH 19 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__miss_excp__WIDTH 1 -#define R_MMU_CAUSE__miss_excp__yes 1 -#define R_MMU_CAUSE__miss_excp__no 0 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__inv_excp__WIDTH 1 -#define R_MMU_CAUSE__inv_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__no 0 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__acc_excp__WIDTH 1 -#define R_MMU_CAUSE__acc_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__no 0 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__we_excp__WIDTH 1 -#define R_MMU_CAUSE__we_excp__yes 1 -#define R_MMU_CAUSE__we_excp__no 0 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__wr_rd__WIDTH 1 -#define R_MMU_CAUSE__wr_rd__write 1 -#define R_MMU_CAUSE__wr_rd__read 0 -#define R_MMU_CAUSE__page_id__BITNR 0 -#define R_MMU_CAUSE__page_id__WIDTH 6 - -#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__index__BITNR 0 -#define R_TLB_SELECT__index__WIDTH 6 - -#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__pfn__WIDTH 19 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__global__WIDTH 1 -#define R_TLB_LO__global__yes 1 -#define R_TLB_LO__global__no 0 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__valid__WIDTH 1 -#define R_TLB_LO__valid__yes 1 -#define R_TLB_LO__valid__no 0 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__kernel__WIDTH 1 -#define R_TLB_LO__kernel__yes 1 -#define R_TLB_LO__kernel__no 0 -#define R_TLB_LO__we__BITNR 0 -#define R_TLB_LO__we__WIDTH 1 -#define R_TLB_LO__we__yes 1 -#define R_TLB_LO__we__no 0 - -#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__vpn__WIDTH 19 -#define R_TLB_HI__page_id__BITNR 0 -#define R_TLB_HI__page_id__WIDTH 6 - -/* -!* Syncrounous serial port registers -!*/ - -#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 - -#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 - diff --git a/include/asm-cris/arch-v10/sv_addr_ag.h b/include/asm-cris/arch-v10/sv_addr_ag.h deleted file mode 100644 index e4a6b68b8982..000000000000 --- a/include/asm-cris/arch-v10/sv_addr_ag.h +++ /dev/null @@ -1,139 +0,0 @@ -/*!************************************************************************** -*! -*! MACROS: -*! IO_MASK(reg,field) -*! IO_STATE(reg,field,state) -*! IO_EXTRACT(reg,field,val) -*! IO_STATE_VALUE(reg,field,state) -*! IO_BITNR(reg,field) -*! IO_WIDTH(reg,field) -*! IO_FIELD(reg,field,val) -*! IO_RD(reg) -*! All moderegister addresses and fields of these. -*! -*!**************************************************************************/ - -#ifndef __sv_addr_ag_h__ -#define __sv_addr_ag_h__ - - -#define __test_sv_addr__ 0 - -/*------------------------------------------------------------ -!* General macros to manipulate moderegisters. -!*-----------------------------------------------------------*/ - -/* IO_MASK returns a mask for a specified bitfield in a register. - Note that this macro doesn't work when field width is 32 bits. */ -#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) -#define IO_MASK_(reg_, field_) \ - ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) - -/* IO_STATE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Shifted to correct position) */ -#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) -#define IO_STATE_(reg_, field_, _state) \ - ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) - -/* IO_EXTRACT returns the masked and shifted value corresponding to the - bitfield can have. */ -#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) -#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ - - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) - -/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Not shifted) */ -#define IO_STATE_VALUE(reg, field, state) \ - IO_STATE_VALUE_ (reg##_, field##_, _##state) -#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) - -/* IO_FIELD shifts the val parameter to be aligned with the bitfield - specified. */ -#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) -#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) - -/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is - LSB and the returned bitnumber is LSB of the field. */ -#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) -#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) - -/* IO_WIDTH returns the width, in bits, of a bitfield. */ -#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) -#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) - -/*--- Obsolete. Kept for backw compatibility. ---*/ -/* Reads (or writes) a byte/uword/udword from the specified mode - register. */ -#define IO_RD(reg) (*(volatile u32*)(reg)) -#define IO_RD_B(reg) (*(volatile u8*)(reg)) -#define IO_RD_W(reg) (*(volatile u16*)(reg)) -#define IO_RD_D(reg) (*(volatile u32*)(reg)) - -/*------------------------------------------------------------ -!* Start addresses of the different memory areas. -!*-----------------------------------------------------------*/ - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -/*------------------------------------------------------------ -!* Type casts used in mode register macros, making pointer -!* dereferencing possible. Empty in assembler. -!*-----------------------------------------------------------*/ - -#ifndef __ASSEMBLER__ -# define IO_TYPECAST_UDWORD (volatile u32*) -# define IO_TYPECAST_RO_UDWORD (const volatile u32*) -# define IO_TYPECAST_UWORD (volatile u16*) -# define IO_TYPECAST_RO_UWORD (const volatile u16*) -# define IO_TYPECAST_BYTE (volatile u8*) -# define IO_TYPECAST_RO_BYTE (const volatile u8*) -#else -# define IO_TYPECAST_UDWORD -# define IO_TYPECAST_RO_UDWORD -# define IO_TYPECAST_UWORD -# define IO_TYPECAST_RO_UWORD -# define IO_TYPECAST_BYTE -# define IO_TYPECAST_RO_BYTE -#endif - -/*------------------------------------------------------------*/ - -#include "sv_addr.agh" - -#if __test_sv_addr__ -/* IO_MASK( R_BUS_CONFIG , CE ) */ -IO_MASK( R_WAITSTATES , SRAM_WS ) -IO_MASK( R_TEST , W32 ) - -IO_STATE( R_BUS_CONFIG, CE, DISABLE ) -IO_STATE( R_BUS_CONFIG, CE, ENABLE ) - -IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) - -IO_MASK( R_DRAM_TIMING, REF ) - -IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) - -IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) - == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) -#endif - - -#endif /* ifndef __sv_addr_ag_h__ */ - diff --git a/include/asm-cris/arch-v10/svinto.h b/include/asm-cris/arch-v10/svinto.h deleted file mode 100644 index 0881a1af7cee..000000000000 --- a/include/asm-cris/arch-v10/svinto.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CRIS_SVINTO_H -#define _ASM_CRIS_SVINTO_H - -#include "sv_addr_ag.h" - -extern unsigned int genconfig_shadow; /* defined and set in head.S */ - -/* dma stuff */ - -enum { /* Available in: */ - d_eol = (1 << 0), /* flags */ - d_eop = (1 << 1), /* flags & status */ - d_wait = (1 << 2), /* flags */ - d_int = (1 << 3), /* flags */ - d_txerr = (1 << 4), /* flags */ - d_stop = (1 << 4), /* status */ - d_ecp = (1 << 4), /* flags & status */ - d_pri = (1 << 5), /* flags & status */ - d_alignerr = (1 << 6), /* status */ - d_crcerr = (1 << 7) /* status */ -}; - -/* Do remember that DMA does not go through the MMU and needs - * a real physical address, not an address virtually mapped or - * paged. Therefore the buf/next ptrs below are unsigned long instead - * of void * to give a warning if you try to put a pointer directly - * to them instead of going through virt_to_phys/phys_to_virt. - */ - -typedef struct etrax_dma_descr { - unsigned short sw_len; /* 0-1 */ - unsigned short ctrl; /* 2-3 */ - unsigned long next; /* 4-7 */ - unsigned long buf; /* 8-11 */ - unsigned short hw_len; /* 12-13 */ - unsigned char status; /* 14 */ - unsigned char fifo_len; /* 15 */ -} etrax_dma_descr; - - -/* Use this for constant numbers only */ -#define RESET_DMA_NUM( n ) \ - *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) - -/* Use this for constant numbers or symbols, - * having two macros makes it possible to use constant expressions. - */ -#define RESET_DMA( n ) RESET_DMA_NUM( n ) - - -/* Use this for constant numbers only */ -#define WAIT_DMA_NUM( n ) \ - while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ - IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) - -/* Use this for constant numbers or symbols - * having two macros makes it possible to use constant expressions. - */ -#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) - -extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); -extern void flush_etrax_cache(void); - -#endif diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h deleted file mode 100644 index 4a9cd36c9e16..000000000000 --- a/include/asm-cris/arch-v10/system.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_SYSTEM_H -#define __ASM_CRIS_ARCH_SYSTEM_H - - -/* read the CPU version register */ - -static inline unsigned long rdvr(void) { - unsigned char vr; - __asm__ volatile ("move $vr,%0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "cris" - -/* read/write the user-mode stackpointer */ - -static inline unsigned long rdusp(void) { - unsigned long usp; - __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); - return usp; -} - -#define wrusp(usp) \ - __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) - -/* read the current stackpointer */ - -static inline unsigned long rdsp(void) { - unsigned long sp; - __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); - return sp; -} - -static inline unsigned long _get_base(char * addr) -{ - return 0; -} - -#define nop() __asm__ __volatile__ ("nop"); - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* interrupt control.. */ -#define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory"); -#define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory"); -#define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory"); -#define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - !(flags & (1<<5)); \ -}) - -/* For spinlocks etc */ -#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory"); - -#endif diff --git a/include/asm-cris/arch-v10/thread_info.h b/include/asm-cris/arch-v10/thread_info.h deleted file mode 100644 index 218f4152d3e5..000000000000 --- a/include/asm-cris/arch-v10/thread_info.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_ARCH_THREAD_INFO_H -#define _ASM_ARCH_THREAD_INFO_H - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif diff --git a/include/asm-cris/arch-v10/timex.h b/include/asm-cris/arch-v10/timex.h deleted file mode 100644 index e48447d94faf..000000000000 --- a/include/asm-cris/arch-v10/timex.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Use prescale timer at 25000 Hz instead of the baudrate timer at - * 19200 to get rid of the 64ppm to fast timer (and we get better - * resolution within a jiffie as well. - */ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ -/* If you change anything here you must check time.c as well... */ -#define PRESCALE_FREQ 25000000 -#define PRESCALE_VALUE 1000 -#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ -/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_CLKSEL flexible -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - - -#define GET_JIFFIES_USEC() \ - ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) - -unsigned long get_ns_in_jiffie(void); - -static inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie()/1000; -} - -#endif diff --git a/include/asm-cris/arch-v10/tlb.h b/include/asm-cris/arch-v10/tlb.h deleted file mode 100644 index 31525bbe75c3..000000000000 --- a/include/asm-cris/arch-v10/tlb.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* The TLB can host up to 64 different mm contexts at the same time. - * The last page_id is never running - it is used as an invalid page_id - * so we can make TLB entries that will never match. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 64 -#define INVALID_PAGEID 63 -#define NO_CONTEXT -1 - -#endif diff --git a/include/asm-cris/arch-v10/uaccess.h b/include/asm-cris/arch-v10/uaccess.h deleted file mode 100644 index 65b02d9b605a..000000000000 --- a/include/asm-cris/arch-v10/uaccess.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Authors: Bjorn Wesen (bjornw@axis.com) - * Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *after* the faulting - * instruction. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - " "op" %1,[%2]\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) \ - __asm__ __volatile__( \ - " move.d %M1,[%2]\n" \ - "2: move.d %H1,[%2+4]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - " "op" [%2],%1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " moveq 0,%1\n" \ - " jump 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) \ - __asm__ __volatile__( \ - " move.d [%2],%M1\n" \ - "2: move.d [%2+4],%H1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " moveq 0,%1\n" \ - " jump 4b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -static inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3 - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - " move.b [%2+],$r9\n" - "1: beq 2f\n" - " move.b $r9,[%1+]\n" - - " subq 1,%0\n" - " bne 1b\n" - " move.b [%2+],$r9\n" - - "2: sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - - /* There's one address for a fault at the first move, and - two possible PC values for a fault at the second move, - being a delay-slot filler. However, the branch-target - for the second move is the same as the first address. - Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 1b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "r9"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address *after* the insn. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " jump 1b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=r" (to), "=r" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "r9", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "2: move.b $r9,[%0+]\n", \ - "3: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "2: move.w $r9,[%0+]\n" COPY, \ - "3: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "4: move.b $r9,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "2: move.d $r9,[%0+]\n" COPY, \ - "3: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "4: move.b $r9,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "4: move.w $r9,[%0+]\n" COPY, \ - "5: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "6: move.b $r9,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "4: move.d $r9,[%0+]\n" COPY, \ - "5: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "6: move.b $r9,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "6: move.w $r9,[%0+]\n" COPY, \ - "7: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "8: move.b $r9,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "6: move.d $r9,[%0+]\n" COPY, \ - "7: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "8: move.b $r9,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "8: move.w $r9,[%0+]\n" COPY, \ - "9: addq 2,%2\n" \ - " clear.w [%0+]\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "10: move.b $r9,[%0+]\n", \ - "11: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "8: move.d $r9,[%0+]\n" COPY, \ - "9: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "10: move.d $r9,[%0+]\n" COPY, \ - "11: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "12: move.d $r9,[%0+]\n" COPY, \ - "13: addq 4,%2\n" \ - " clear.d [%0+]\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n2:\n", \ - "3: addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n2:\n" COPY, \ - "3: addq 2,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n4:\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n2:\n" COPY, \ - "3: addq 4,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n4:\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n4:\n" COPY, \ - "5: addq 2,%2\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n6:\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n4:\n" COPY, \ - "5: addq 4,%2\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n6:\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n6:\n" COPY, \ - "7: addq 2,%2\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n8:\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n6:\n" COPY, \ - "7: addq 4,%2\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n8:\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n8:\n" COPY, \ - "9: addq 2,%2\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n10:\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n8:\n" COPY, \ - "9: addq 4,%2\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n10:\n" COPY, \ - "11: addq 4,%2\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n12:\n" COPY, \ - "13: addq 4,%2\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " jump 1b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=r" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - " clear.b [%0+]\n2:\n", \ - "3: addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - " clear.w [%0+]\n2:\n", \ - "3: addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - " clear.w [%0+]\n" \ - "2: clear.b [%0+]\n3:\n", \ - "4: addq 2,%1\n" \ - "5: addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - " clear.d [%0+]\n2:\n" CLEAR, \ - "3: addq 4,%1\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - " clear.d [%0+]\n4:\n" CLEAR, \ - "5: addq 4,%1\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - " clear.d [%0+]\n6:\n" CLEAR, \ - "7: addq 4,%1\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - " clear.d [%0+]\n8:\n" CLEAR, \ - "9: addq 4,%1\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - " clear.d [%0+]\n10:\n" CLEAR, \ - "11: addq 4,%1\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - " clear.d [%0+]\n12:\n" CLEAR, \ - "13: addq 4,%1\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -static inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$r9\n" - "0:\n" - " ble 1f\n" - " subq 1,$r9\n" - - " test.b [%0+]\n" - " bne 0b\n" - " test.d $r9\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $r9,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: clear.d %0\n" - " jump 2b\n" - - /* There's one address for a fault at the first move, and - two possible PC values for a fault at the second move, - being a delay-slot filler. However, the branch-target - for the second move is the same as the first address. - Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 0b,3b\n" - " .dword 1b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "r9"); - - return res; -} - -#endif diff --git a/include/asm-cris/arch-v10/unistd.h b/include/asm-cris/arch-v10/unistd.h deleted file mode 100644 index d1a38b9e6264..000000000000 --- a/include/asm-cris/arch-v10/unistd.h +++ /dev/null @@ -1,148 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "move %6,$mof\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "g" (arg5)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "move %6,$mof\n\tmove %7,$srp\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ - : "srp"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/include/asm-cris/arch-v10/user.h b/include/asm-cris/arch-v10/user.h deleted file mode 100644 index 9303ea77c915..000000000000 --- a/include/asm-cris/arch-v10/user.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_USER_H -#define __ASM_CRIS_ARCH_USER_H - -/* User mode registers, used for core dumps. In order to keep ELF_NGREG - sensible we let all registers be 32 bits. The csr registers are included - for future use. */ -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* Stack pointer. */ - unsigned long pc; /* Program counter. */ - unsigned long p0; /* Constant zero (only 8 bits). */ - unsigned long vr; /* Version register (only 8 bits). */ - unsigned long p2; /* Reserved. */ - unsigned long p3; /* Reserved. */ - unsigned long p4; /* Constant zero (only 16 bits). */ - unsigned long ccr; /* Condition code register (only 16 bits). */ - unsigned long p6; /* Reserved. */ - unsigned long mof; /* Multiply overflow register. */ - unsigned long p8; /* Constant zero. */ - unsigned long ibr; /* Not accessible. */ - unsigned long irp; /* Not accessible. */ - unsigned long srp; /* Subroutine return pointer. */ - unsigned long bar; /* Not accessible. */ - unsigned long dccr; /* Dword condition code register. */ - unsigned long brp; /* Not accessible. */ - unsigned long usp; /* User-mode stack pointer. Same as sp when - in user mode. */ - unsigned long csrinstr; /* Internal status registers. */ - unsigned long csraddr; - unsigned long csrdata; -}; - -#endif diff --git a/include/asm-cris/arch-v32/Kbuild b/include/asm-cris/arch-v32/Kbuild deleted file mode 100644 index 35f2fc4f993e..000000000000 --- a/include/asm-cris/arch-v32/Kbuild +++ /dev/null @@ -1,2 +0,0 @@ -header-y += user.h -header-y += cryptocop.h diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h deleted file mode 100644 index 081a911d7af1..000000000000 --- a/include/asm-cris/arch-v32/arbiter.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum -{ - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum -{ - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback* cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h deleted file mode 100644 index 852ceff8013f..000000000000 --- a/include/asm-cris/arch-v32/atomic.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_ATOMIC__ -#define __ASM_CRIS_ARCH_ATOMIC__ - -#include <linux/spinlock_types.h> - -extern void cris_spin_unlock(void *l, int val); -extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void* l); - -#ifndef CONFIG_SMP -#define cris_atomic_save(addr, flags) local_irq_save(flags); -#define cris_atomic_restore(addr, flags) local_irq_restore(flags); -#else - -extern spinlock_t cris_atomic_locks[]; -#define LOCK_COUNT 128 -#define HASH_ADDR(a) (((int)a) & 127) - -#define cris_atomic_save(addr, flags) \ - local_irq_save(flags); \ - cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock); - -#define cris_atomic_restore(addr, flags) \ - { \ - spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ - __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->raw_lock.slock) \ - : "r" (1) \ - : "memory"); \ - local_irq_restore(flags); \ - } - -#endif - -#endif - diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h deleted file mode 100644 index 147689d6b624..000000000000 --- a/include/asm-cris/arch-v32/bitops.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_BITOPS_H -#define _ASM_CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions. They compute the - * number of leading zeroes of a bits-in-byte, byte-in-word and - * word-in-dword-swapped number. They differ in that the first function also - * inverts all bits in the input. - */ - -static inline unsigned long -cris_swapnwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapnwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -static inline unsigned long -cris_swapwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -/* - * Find First Zero in word. Undefined if no zero exist, so the caller should - * check against ~0 first. - */ -static inline unsigned long -ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/* - * Find First Set bit in word. Undefined if no 1 exist, so the caller - * should check against 0 first. - */ -static inline unsigned long -__ffs(unsigned long w) -{ - return cris_swapnwbrlz(~w); -} - -/* - * Find First Bit that is set. - */ -static inline unsigned long -kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/include/asm-cris/arch-v32/bug.h b/include/asm-cris/arch-v32/bug.h deleted file mode 100644 index 0f211e135248..000000000000 --- a/include/asm-cris/arch-v32/bug.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_CRISv32_ARCH_BUG_H -#define __ASM_CRISv32_ARCH_BUG_H - -#include <linux/stringify.h> - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -/* - * The penalty for the in-band code path will be the size of break 14. - * All other stuff is done out-of-band with exception handlers. - */ -#define BUG() \ - __asm__ __volatile__ ("0: break 14\n\t" \ - ".section .fixup,\"ax\"\n" \ - "1:\n\t" \ - "move.d %0, $r10\n\t" \ - "move.d %1, $r11\n\t" \ - "jump do_BUG\n\t" \ - "nop\n\t" \ - ".previous\n\t" \ - ".section __ex_table,\"a\"\n\t" \ - ".dword 0b, 1b\n\t" \ - ".previous\n\t" \ - : : "ri" (__FILE__), "i" (__LINE__)) -#else -#define BUG() __asm__ __volatile__ ("break 14\n\t") -#endif - -#define HAVE_ARCH_BUG -#endif - -#include <asm-generic/bug.h> -#endif diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h deleted file mode 100644 index 6ef8fb4a35f2..000000000000 --- a/include/asm-cris/arch-v32/byteorder.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_BYTEORDER_H -#define _ASM_CRIS_ARCH_BYTEORDER_H - -#include <asm/types.h> - -static inline __const__ __u32 -___arch__swab32(__u32 x) -{ - __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); - return (x); -} - -static inline __const__ __u16 -___arch__swab16(__u16 x) -{ - __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); - return (x); -} - -#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */ diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h deleted file mode 100644 index b3d752dfe15b..000000000000 --- a/include/asm-cris/arch-v32/cache.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_CACHE_H -#define _ASM_CRIS_ARCH_CACHE_H - -#include <asm/arch/hwregs/dma.h> - -/* A cache-line is 32 bytes. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 - -void flush_dma_list(dma_descr_data *descr); -void flush_dma_descr(dma_descr_data *descr, int flush_buf); - -#define flush_dma_context(c) \ - flush_dma_list(phys_to_virt((c)->saved_data)); - -void cris_flush_cache_range(void *buf, unsigned long len); -void cris_flush_cache(void); - -#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h deleted file mode 100644 index e5dcfce6e0dc..000000000000 --- a/include/asm-cris/arch-v32/checksum.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_CHECKSUM_H -#define _ASM_CRIS_ARCH_CHECKSUM_H - -/* - * Check values used in TCP/UDP headers. - * - * The gain of doing this in assembler instead of C, is that C doesn't - * generate carry-additions for the 32-bit components of the - * checksum. Which means it would be necessary to split all those into - * 16-bit components and then add. - */ -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, - unsigned short len, unsigned short proto, __wsum sum) -{ - __wsum res; - - __asm__ __volatile__ ("add.d %2, %0\n\t" - "addc %3, %0\n\t" - "addc %4, %0\n\t" - "addc 0, %0\n\t" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), \ - "r" ((len + proto) << 8)); - - return res; -} - -#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h deleted file mode 100644 index dfa1f66fb987..000000000000 --- a/include/asm-cris/arch-v32/cryptocop.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * The device /dev/cryptocop is accessible using this driver using - * CRYPTOCOP_MAJOR (254) and minor number 0. - */ - -#ifndef CRYPTOCOP_H -#define CRYPTOCOP_H - -#include <linux/uio.h> - - -#define CRYPTOCOP_SESSION_ID_NONE (0) - -typedef unsigned long long int cryptocop_session_id; - -/* cryptocop ioctls */ -#define ETRAXCRYPTOCOP_IOCTYPE (250) - -#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) -#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) -#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) -#define CRYPTOCOP_IO_MAXNR (3) - -typedef enum { - cryptocop_cipher_des = 0, - cryptocop_cipher_3des = 1, - cryptocop_cipher_aes = 2, - cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ - cryptocop_cipher_none -} cryptocop_cipher_type; - -typedef enum { - cryptocop_digest_sha1 = 0, - cryptocop_digest_md5 = 1, - cryptocop_digest_none -} cryptocop_digest_type; - -typedef enum { - cryptocop_csum_le = 0, - cryptocop_csum_be = 1, - cryptocop_csum_none -} cryptocop_csum_type; - -typedef enum { - cryptocop_cipher_mode_ecb = 0, - cryptocop_cipher_mode_cbc, - cryptocop_cipher_mode_none -} cryptocop_cipher_mode; - -typedef enum { - cryptocop_3des_eee = 0, - cryptocop_3des_eed = 1, - cryptocop_3des_ede = 2, - cryptocop_3des_edd = 3, - cryptocop_3des_dee = 4, - cryptocop_3des_ded = 5, - cryptocop_3des_dde = 6, - cryptocop_3des_ddd = 7 -} cryptocop_3des_mode; - -/* Usermode accessible (ioctl) operations. */ -struct strcop_session_op{ - cryptocop_session_id ses_id; - - cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ - - cryptocop_cipher_mode cmode; /* ECB, CBC, none */ - cryptocop_3des_mode des3_mode; - - cryptocop_digest_type digest; /* MD5, SHA1, none */ - - cryptocop_csum_type csum; /* BE, LE, none */ - - unsigned char *key; - size_t keylen; -}; - -#define CRYPTOCOP_CSUM_LENGTH (2) -#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ -#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ -#define CRYPTOCOP_MAX_KEY_LENGTH (32) - -struct strcop_crypto_op{ - cryptocop_session_id ses_id; - - /* Indata. */ - unsigned char *indata; - size_t inlen; /* Total indata length. */ - - /* Cipher configuration. */ - unsigned char do_cipher:1; - unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ - unsigned char cipher_explicit:1; - size_t cipher_start; - size_t cipher_len; - /* cipher_iv is used if do_cipher and cipher_explicit and the cipher - mode is CBC. The length is controlled by the type of cipher, - e.g. DES/3DES 8 octets and AES 16 octets. */ - unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; - /* Outdata. */ - unsigned char *cipher_outdata; - size_t cipher_outlen; - - /* digest configuration. */ - unsigned char do_digest:1; - size_t digest_start; - size_t digest_len; - /* Outdata. The actual length is determined by the type of the digest. */ - unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; - - /* Checksum configuration. */ - unsigned char do_csum:1; - size_t csum_start; - size_t csum_len; - /* Outdata. */ - unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; -}; - - - -#ifdef __KERNEL__ - -/********** The API to use from inside the kernel. ************/ - -#include <asm/arch/hwregs/dma.h> - -typedef enum { - cryptocop_alg_csum = 0, - cryptocop_alg_mem2mem, - cryptocop_alg_md5, - cryptocop_alg_sha1, - cryptocop_alg_des, - cryptocop_alg_3des, - cryptocop_alg_aes, - cryptocop_no_alg, -} cryptocop_algorithm; - -typedef u8 cryptocop_tfrm_id; - - -struct cryptocop_operation; - -typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); - -struct cryptocop_transform_init { - cryptocop_algorithm alg; - /* Keydata for ciphers. */ - unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; - unsigned int keylen; - cryptocop_cipher_mode cipher_mode; - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ - - cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ - struct cryptocop_transform_init *next; -}; - - -typedef enum { - cryptocop_source_dma = 0, - cryptocop_source_des, - cryptocop_source_3des, - cryptocop_source_aes, - cryptocop_source_md5, - cryptocop_source_sha1, - cryptocop_source_csum, - cryptocop_source_none, -} cryptocop_source; - - -struct cryptocop_desc_cfg { - cryptocop_tfrm_id tid; - cryptocop_source src; - unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ - struct cryptocop_desc_cfg *next; -}; - -struct cryptocop_desc { - size_t length; - struct cryptocop_desc_cfg *cfg; - struct cryptocop_desc *next; -}; - - -/* Flags for cryptocop_tfrm_cfg */ -#define CRYPTOCOP_NO_FLAG (0x00) -#define CRYPTOCOP_ENCRYPT (0x01) -#define CRYPTOCOP_DECRYPT (0x02) -#define CRYPTOCOP_EXPLICIT_IV (0x04) - -struct cryptocop_tfrm_cfg { - cryptocop_tfrm_id tid; - - unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ - - /* CBC initialisation vector for cihers. */ - u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; - - /* The position in output where to write the transform output. The order - in which the driver writes the output is unspecified, hence if several - transforms write on the same positions in the output the result is - unspecified. */ - size_t inject_ix; - - struct cryptocop_tfrm_cfg *next; -}; - - - -struct cryptocop_dma_list_operation{ - /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in - struct cryptocop_operation must be set for the driver to use them. outlist, - out_data_buf, inlist and in_data_buf must all be physical addresses since they will - be loaded to DMA . */ - dma_descr_data *outlist; /* Out from memory to the co-processor. */ - char *out_data_buf; - dma_descr_data *inlist; /* In from the co-processor to memory. */ - char *in_data_buf; - - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; -}; - - -struct cryptocop_tfrm_operation{ - /* Operation configuration, if not 'use_dmalists' is set. */ - struct cryptocop_tfrm_cfg *tfrm_cfg; - struct cryptocop_desc *desc; - - struct iovec *indata; - size_t incount; - size_t inlen; /* Total inlength. */ - - struct iovec *outdata; - size_t outcount; - size_t outlen; /* Total outlength. */ -}; - - -struct cryptocop_operation { - cryptocop_callback *cb; - void *cb_data; - - cryptocop_session_id sid; - - /* The status of the operation when returned to consumer. */ - int operation_status; /* 0, -EAGAIN */ - - /* Flags */ - unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ - unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ - unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ - - union{ - struct cryptocop_dma_list_operation list_op; - struct cryptocop_tfrm_operation tfrm_op; - }; -}; - - -int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); -int cryptocop_free_session(cryptocop_session_id sid); - -int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); - -#endif /* __KERNEL__ */ - -#endif /* CRYPTOCOP_H */ diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h deleted file mode 100644 index e9fda03810a9..000000000000 --- a/include/asm-cris/arch-v32/delay.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_DELAY_H -#define _ASM_CRIS_ARCH_DELAY_H - -extern void cris_delay10ns(u32 n10ns); -#define udelay(u) cris_delay10ns((u)*100) -#define ndelay(n) cris_delay10ns(((n)+9)/10) - -/* - * Not used anymore for udelay or ndelay. Referenced by - * e.g. init/calibrate.c. All other references are likely bugs; - * should be replaced by mdelay, udelay or ndelay. - */ - -static inline void -__delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0, $r9\n\t" - "beq 2f\n\t" - "subq 1, $r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1, $r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h deleted file mode 100644 index 3674081389fd..000000000000 --- a/include/asm-cris/arch-v32/dma.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 10 - -#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ -#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ - -#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ -#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ - -#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ -#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ - -#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ -#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ - -#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ -#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ - -#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ -#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ - -#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ -#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ - -#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ -#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ - -#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ -#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ - -#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ -#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ - -#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ -#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ - -#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ -#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ - -#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ -#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ - -#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ -#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ - -enum dma_owner -{ - dma_eth0, - dma_eth1, - dma_iop0, - dma_iop1, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_sser0, - dma_sser1, - dma_ata, - dma_strp, - dma_ext0, - dma_ext1, - dma_ext2, - dma_ext3 -}; - -int crisv32_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, unsigned bandwidth, enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h deleted file mode 100644 index 1324e505a4d8..000000000000 --- a/include/asm-cris/arch-v32/elf.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef _ASM_CRIS_ELF_H -#define _ASM_CRIS_ELF_H - -#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* CRISv32 ELF register definitions. */ - -#include <asm/ptrace.h> - -/* Explicitly zero out registers to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ - (_r)->acr = 0; \ -} while (0) - -/* - * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. - */ -#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) - -/* - * This is basically a pt_regs with the additional definition - * of the stack pointer since it's needed in a core dump. - * pr_regs is a elf_gregset_t and should be filled according - * to the layout of user_regs_struct. - */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* SP */ \ - pr_reg[15] = regs->acr; /* ACR */ \ - pr_reg[16] = 0; /* BZ */ \ - pr_reg[17] = rdvr(); /* VR */ \ - pr_reg[18] = 0; /* PID */ \ - pr_reg[19] = regs->srs; /* SRS */ \ - pr_reg[20] = 0; /* WZ */ \ - pr_reg[21] = regs->exs; /* EXS */ \ - pr_reg[22] = regs->eda; /* EDA */ \ - pr_reg[23] = regs->mof; /* MOF */ \ - pr_reg[24] = 0; /* DZ */ \ - pr_reg[25] = 0; /* EBP */ \ - pr_reg[26] = regs->erp; /* ERP */ \ - pr_reg[27] = regs->srp; /* SRP */ \ - pr_reg[28] = 0; /* NRP */ \ - pr_reg[29] = regs->ccs; /* CCS */ \ - pr_reg[30] = rdusp(); /* USP */ \ - pr_reg[31] = regs->spc; /* SPC */ \ - -#endif /* _ASM_CRIS_ELF_H */ diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile deleted file mode 100644 index f9a05d2aa061..000000000000 --- a/include/asm-cris/arch-v32/hwregs/Makefile +++ /dev/null @@ -1,186 +0,0 @@ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The offical place for these files is at: -RELEASE ?= r1_alfa5 -OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -# which is updated on each new release. -INCL_ASMFILES = -INCL_FILES = ata_defs.h -INCL_FILES += bif_core_defs.h -INCL_ASMFILES += bif_core_defs_asm.h -INCL_FILES += bif_slave_defs.h -#INCL_FILES += bif_slave_ext_defs.h -INCL_FILES += config_defs.h -INCL_ASMFILES += config_defs_asm.h -INCL_FILES += cpu_vect.h -#INCL_FILES += cris_defs.h -#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h -INCL_FILES += dma.h -INCL_FILES += dma_defs.h -INCL_FILES += eth_defs.h -INCL_FILES += extmem_defs.h -INCL_FILES += gio_defs.h -INCL_ASMFILES += gio_defs_asm.h -INCL_FILES += intr_vect.h -INCL_FILES += intr_vect_defs.h -INCL_ASMFILES += intr_vect_defs_asm.h -INCL_FILES += marb_bp_defs.h -INCL_FILES += marb_defs.h -INCL_ASMFILES += mmu_defs_asm.h -#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h -#INCL_FILES += par_defs.h # No useful content -INCL_FILES += pinmux_defs.h -INCL_FILES += reg_map.h -INCL_ASMFILES += reg_map_asm.h -INCL_FILES += reg_rdwr.h -INCL_FILES += ser_defs.h -#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h -INCL_FILES += sser_defs.h -INCL_FILES += strcop_defs.h -#INCL_FILES += strcop.h # Where is this? -INCL_FILES += strmux_defs.h -#INCL_FILES += supp_reg.h # Handcrafted instead -INCL_FILES += timer_defs.h - -REGDESC = -REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r -#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r -REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r -REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r -REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r -REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r -REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r -REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r -REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r -#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r -REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r -REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r -REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r -REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r -REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r -#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - - -BASEDIR = /n/asic/design -DESIGNDIR = /n/asic/projects/guinness/design -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -# Disable implicit rule that may generate deleted files from RCS/ directory. -%.r: - -%.h: - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(INCL_FILES) $(INCL_ASMFILES) - -ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r - $(RDES2C) $< -config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) $< -config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) -asm $< -# Can't generate cpu_vect.h yet -#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? -# $(RDES2INTR) $< -cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r - $(RDES2C) $< -$(BASEDIR)/core/dma/sw/dma.h: -dma.h: $(BASEDIR)/core/dma/sw/dma.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r - $(RDES2C) $< -extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r - $(RDES2C) $< -gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r - $(RDES2C) $< -intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) $< -intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) -asm $< -# Can't generate intr_vect.h yet -#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -# $(RDES2INTR) $< -intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r - $(RDES2C) -asm $< -par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r - $(RDES2C) $< - -# From /n/asic/projects/guinness/design/ -reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 $^ -reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ - -reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r - $(RDES2C) $< -strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r - $(RDES2C) $< -strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r - $(RDES2C) $< -timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r - $(RDES2C) $< -usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - $(RDES2C) $< - -## copy - Copy files from official location -copy: - @for HFILE in $(INCL_FILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(INCL_ASMFILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done -## ls_official - List official location -ls_official: - (cd $(OFFICIAL_INCDIR); ls -l *.h ) - -## diff_official - Diff current directory with official location -diff_official: - diff . $(OFFICIAL_INCDIR) - -## doc - Generate .axw files from register description. -doc: $(REGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming ir .r files. -%.axw: axw - @for RDES in $(REGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(INCL_FILES) *.axw - diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h deleted file mode 100644 index 866191418f9c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef __ata_defs_asm_h -#define __ata_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ctrl0, scope ata, type rw */ -#define reg_ata_rw_ctrl0___pio_hold___lsb 0 -#define reg_ata_rw_ctrl0___pio_hold___width 6 -#define reg_ata_rw_ctrl0___pio_strb___lsb 6 -#define reg_ata_rw_ctrl0___pio_strb___width 6 -#define reg_ata_rw_ctrl0___pio_setup___lsb 12 -#define reg_ata_rw_ctrl0___pio_setup___width 6 -#define reg_ata_rw_ctrl0___dma_hold___lsb 18 -#define reg_ata_rw_ctrl0___dma_hold___width 6 -#define reg_ata_rw_ctrl0___dma_strb___lsb 24 -#define reg_ata_rw_ctrl0___dma_strb___width 6 -#define reg_ata_rw_ctrl0___rst___lsb 30 -#define reg_ata_rw_ctrl0___rst___width 1 -#define reg_ata_rw_ctrl0___rst___bit 30 -#define reg_ata_rw_ctrl0___en___lsb 31 -#define reg_ata_rw_ctrl0___en___width 1 -#define reg_ata_rw_ctrl0___en___bit 31 -#define reg_ata_rw_ctrl0_offset 12 - -/* Register rw_ctrl1, scope ata, type rw */ -#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 -#define reg_ata_rw_ctrl1___udma_tcyc___width 4 -#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 -#define reg_ata_rw_ctrl1___udma_tdvs___width 4 -#define reg_ata_rw_ctrl1_offset 16 - -/* Register rw_ctrl2, scope ata, type rw */ -#define reg_ata_rw_ctrl2___data___lsb 0 -#define reg_ata_rw_ctrl2___data___width 16 -#define reg_ata_rw_ctrl2___dma_size___lsb 19 -#define reg_ata_rw_ctrl2___dma_size___width 1 -#define reg_ata_rw_ctrl2___dma_size___bit 19 -#define reg_ata_rw_ctrl2___multi___lsb 20 -#define reg_ata_rw_ctrl2___multi___width 1 -#define reg_ata_rw_ctrl2___multi___bit 20 -#define reg_ata_rw_ctrl2___hsh___lsb 21 -#define reg_ata_rw_ctrl2___hsh___width 2 -#define reg_ata_rw_ctrl2___trf_mode___lsb 23 -#define reg_ata_rw_ctrl2___trf_mode___width 1 -#define reg_ata_rw_ctrl2___trf_mode___bit 23 -#define reg_ata_rw_ctrl2___rw___lsb 24 -#define reg_ata_rw_ctrl2___rw___width 1 -#define reg_ata_rw_ctrl2___rw___bit 24 -#define reg_ata_rw_ctrl2___addr___lsb 25 -#define reg_ata_rw_ctrl2___addr___width 3 -#define reg_ata_rw_ctrl2___cs0___lsb 28 -#define reg_ata_rw_ctrl2___cs0___width 1 -#define reg_ata_rw_ctrl2___cs0___bit 28 -#define reg_ata_rw_ctrl2___cs1___lsb 29 -#define reg_ata_rw_ctrl2___cs1___width 1 -#define reg_ata_rw_ctrl2___cs1___bit 29 -#define reg_ata_rw_ctrl2___sel___lsb 30 -#define reg_ata_rw_ctrl2___sel___width 2 -#define reg_ata_rw_ctrl2_offset 0 - -/* Register rs_stat_data, scope ata, type rs */ -#define reg_ata_rs_stat_data___data___lsb 0 -#define reg_ata_rs_stat_data___data___width 16 -#define reg_ata_rs_stat_data___dav___lsb 16 -#define reg_ata_rs_stat_data___dav___width 1 -#define reg_ata_rs_stat_data___dav___bit 16 -#define reg_ata_rs_stat_data___busy___lsb 17 -#define reg_ata_rs_stat_data___busy___width 1 -#define reg_ata_rs_stat_data___busy___bit 17 -#define reg_ata_rs_stat_data_offset 4 - -/* Register r_stat_data, scope ata, type r */ -#define reg_ata_r_stat_data___data___lsb 0 -#define reg_ata_r_stat_data___data___width 16 -#define reg_ata_r_stat_data___dav___lsb 16 -#define reg_ata_r_stat_data___dav___width 1 -#define reg_ata_r_stat_data___dav___bit 16 -#define reg_ata_r_stat_data___busy___lsb 17 -#define reg_ata_r_stat_data___busy___width 1 -#define reg_ata_r_stat_data___busy___bit 17 -#define reg_ata_r_stat_data_offset 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -#define reg_ata_rw_trf_cnt___cnt___lsb 0 -#define reg_ata_rw_trf_cnt___cnt___width 17 -#define reg_ata_rw_trf_cnt_offset 20 - -/* Register r_stat_misc, scope ata, type r */ -#define reg_ata_r_stat_misc___crc___lsb 0 -#define reg_ata_r_stat_misc___crc___width 16 -#define reg_ata_r_stat_misc_offset 24 - -/* Register rw_intr_mask, scope ata, type rw */ -#define reg_ata_rw_intr_mask___bus0___lsb 0 -#define reg_ata_rw_intr_mask___bus0___width 1 -#define reg_ata_rw_intr_mask___bus0___bit 0 -#define reg_ata_rw_intr_mask___bus1___lsb 1 -#define reg_ata_rw_intr_mask___bus1___width 1 -#define reg_ata_rw_intr_mask___bus1___bit 1 -#define reg_ata_rw_intr_mask___bus2___lsb 2 -#define reg_ata_rw_intr_mask___bus2___width 1 -#define reg_ata_rw_intr_mask___bus2___bit 2 -#define reg_ata_rw_intr_mask___bus3___lsb 3 -#define reg_ata_rw_intr_mask___bus3___width 1 -#define reg_ata_rw_intr_mask___bus3___bit 3 -#define reg_ata_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope ata, type rw */ -#define reg_ata_rw_ack_intr___bus0___lsb 0 -#define reg_ata_rw_ack_intr___bus0___width 1 -#define reg_ata_rw_ack_intr___bus0___bit 0 -#define reg_ata_rw_ack_intr___bus1___lsb 1 -#define reg_ata_rw_ack_intr___bus1___width 1 -#define reg_ata_rw_ack_intr___bus1___bit 1 -#define reg_ata_rw_ack_intr___bus2___lsb 2 -#define reg_ata_rw_ack_intr___bus2___width 1 -#define reg_ata_rw_ack_intr___bus2___bit 2 -#define reg_ata_rw_ack_intr___bus3___lsb 3 -#define reg_ata_rw_ack_intr___bus3___width 1 -#define reg_ata_rw_ack_intr___bus3___bit 3 -#define reg_ata_rw_ack_intr_offset 32 - -/* Register r_intr, scope ata, type r */ -#define reg_ata_r_intr___bus0___lsb 0 -#define reg_ata_r_intr___bus0___width 1 -#define reg_ata_r_intr___bus0___bit 0 -#define reg_ata_r_intr___bus1___lsb 1 -#define reg_ata_r_intr___bus1___width 1 -#define reg_ata_r_intr___bus1___bit 1 -#define reg_ata_r_intr___bus2___lsb 2 -#define reg_ata_r_intr___bus2___width 1 -#define reg_ata_r_intr___bus2___bit 2 -#define reg_ata_r_intr___bus3___lsb 3 -#define reg_ata_r_intr___bus3___width 1 -#define reg_ata_r_intr___bus3___bit 3 -#define reg_ata_r_intr_offset 36 - -/* Register r_masked_intr, scope ata, type r */ -#define reg_ata_r_masked_intr___bus0___lsb 0 -#define reg_ata_r_masked_intr___bus0___width 1 -#define reg_ata_r_masked_intr___bus0___bit 0 -#define reg_ata_r_masked_intr___bus1___lsb 1 -#define reg_ata_r_masked_intr___bus1___width 1 -#define reg_ata_r_masked_intr___bus1___bit 1 -#define reg_ata_r_masked_intr___bus2___lsb 2 -#define reg_ata_r_masked_intr___bus2___width 1 -#define reg_ata_r_masked_intr___bus2___bit 2 -#define reg_ata_r_masked_intr___bus3___lsb 3 -#define reg_ata_r_masked_intr___bus3___width 1 -#define reg_ata_r_masked_intr___bus3___bit 3 -#define reg_ata_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_ata_active 0x00000001 -#define regk_ata_byte 0x00000001 -#define regk_ata_data 0x00000001 -#define regk_ata_dma 0x00000001 -#define regk_ata_inactive 0x00000000 -#define regk_ata_no 0x00000000 -#define regk_ata_nodata 0x00000000 -#define regk_ata_pio 0x00000000 -#define regk_ata_rd 0x00000001 -#define regk_ata_reg 0x00000000 -#define regk_ata_rw_ctrl0_default 0x00000000 -#define regk_ata_rw_ctrl2_default 0x00000000 -#define regk_ata_rw_intr_mask_default 0x00000000 -#define regk_ata_udma 0x00000002 -#define regk_ata_word 0x00000000 -#define regk_ata_wr 0x00000000 -#define regk_ata_yes 0x00000001 -#endif /* __ata_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index c686cb335621..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,319 +0,0 @@ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h deleted file mode 100644 index 71532aa18168..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h +++ /dev/null @@ -1,495 +0,0 @@ -#ifndef __bif_dma_defs_asm_h -#define __bif_dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch0_ctrl_offset 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch0_addr___addr___width 32 -#define reg_bif_dma_rw_ch0_addr_offset 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_start___run___lsb 0 -#define reg_bif_dma_rw_ch0_start___run___width 1 -#define reg_bif_dma_rw_ch0_start___run___bit 0 -#define reg_bif_dma_rw_ch0_start_offset 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch0_cnt_offset 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch0_stat___cnt___width 16 -#define reg_bif_dma_r_ch0_stat___run___lsb 31 -#define reg_bif_dma_r_ch0_stat___run___width 1 -#define reg_bif_dma_r_ch0_stat___run___bit 31 -#define reg_bif_dma_r_ch0_stat_offset 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch1_ctrl_offset 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch1_addr___addr___width 32 -#define reg_bif_dma_rw_ch1_addr_offset 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_start___run___lsb 0 -#define reg_bif_dma_rw_ch1_start___run___width 1 -#define reg_bif_dma_rw_ch1_start___run___bit 0 -#define reg_bif_dma_rw_ch1_start_offset 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch1_cnt_offset 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch1_stat___cnt___width 16 -#define reg_bif_dma_r_ch1_stat___run___lsb 31 -#define reg_bif_dma_r_ch1_stat___run___width 1 -#define reg_bif_dma_r_ch1_stat___run___bit 31 -#define reg_bif_dma_r_ch1_stat_offset 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch2_ctrl_offset 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch2_addr___addr___width 32 -#define reg_bif_dma_rw_ch2_addr_offset 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_start___run___lsb 0 -#define reg_bif_dma_rw_ch2_start___run___width 1 -#define reg_bif_dma_rw_ch2_start___run___bit 0 -#define reg_bif_dma_rw_ch2_start_offset 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch2_cnt_offset 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch2_stat___cnt___width 16 -#define reg_bif_dma_r_ch2_stat___run___lsb 31 -#define reg_bif_dma_r_ch2_stat___run___width 1 -#define reg_bif_dma_r_ch2_stat___run___bit 31 -#define reg_bif_dma_r_ch2_stat_offset 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch3_ctrl_offset 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch3_addr___addr___width 32 -#define reg_bif_dma_rw_ch3_addr_offset 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_start___run___lsb 0 -#define reg_bif_dma_rw_ch3_start___run___width 1 -#define reg_bif_dma_rw_ch3_start___run___bit 0 -#define reg_bif_dma_rw_ch3_start_offset 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch3_cnt_offset 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch3_stat___cnt___width 16 -#define reg_bif_dma_r_ch3_stat___run___lsb 31 -#define reg_bif_dma_r_ch3_stat___run___width 1 -#define reg_bif_dma_r_ch3_stat___run___bit 31 -#define reg_bif_dma_r_ch3_stat_offset 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 -#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 -#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 -#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 -#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 -#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 -#define reg_bif_dma_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 -#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 -#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 -#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 -#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 -#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 -#define reg_bif_dma_rw_ack_intr_offset 132 - -/* Register r_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_intr___ext_dma0___width 1 -#define reg_bif_dma_r_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_intr___ext_dma1___width 1 -#define reg_bif_dma_r_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_intr___ext_dma2___width 1 -#define reg_bif_dma_r_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_intr___ext_dma3___width 1 -#define reg_bif_dma_r_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_intr_offset 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_masked_intr_offset 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg_offset 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg_offset 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg_offset 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg_offset 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg_offset 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg_offset 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg_offset 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg_offset 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_pin_stat___pin0___lsb 0 -#define reg_bif_dma_r_pin_stat___pin0___width 1 -#define reg_bif_dma_r_pin_stat___pin0___bit 0 -#define reg_bif_dma_r_pin_stat___pin1___lsb 1 -#define reg_bif_dma_r_pin_stat___pin1___width 1 -#define reg_bif_dma_r_pin_stat___pin1___bit 1 -#define reg_bif_dma_r_pin_stat___pin2___lsb 2 -#define reg_bif_dma_r_pin_stat___pin2___width 1 -#define reg_bif_dma_r_pin_stat___pin2___bit 2 -#define reg_bif_dma_r_pin_stat___pin3___lsb 3 -#define reg_bif_dma_r_pin_stat___pin3___width 1 -#define reg_bif_dma_r_pin_stat___pin3___bit 3 -#define reg_bif_dma_r_pin_stat___pin4___lsb 4 -#define reg_bif_dma_r_pin_stat___pin4___width 1 -#define reg_bif_dma_r_pin_stat___pin4___bit 4 -#define reg_bif_dma_r_pin_stat___pin5___lsb 5 -#define reg_bif_dma_r_pin_stat___pin5___width 1 -#define reg_bif_dma_r_pin_stat___pin5___bit 5 -#define reg_bif_dma_r_pin_stat___pin6___lsb 6 -#define reg_bif_dma_r_pin_stat___pin6___width 1 -#define reg_bif_dma_r_pin_stat___pin6___bit 6 -#define reg_bif_dma_r_pin_stat___pin7___lsb 7 -#define reg_bif_dma_r_pin_stat___pin7___width 1 -#define reg_bif_dma_r_pin_stat___pin7___bit 7 -#define reg_bif_dma_r_pin_stat_offset 192 - - -/* Constants */ -#define regk_bif_dma_as_master 0x00000001 -#define regk_bif_dma_as_slave 0x00000001 -#define regk_bif_dma_burst1 0x00000000 -#define regk_bif_dma_burst8 0x00000001 -#define regk_bif_dma_bw16 0x00000001 -#define regk_bif_dma_bw32 0x00000002 -#define regk_bif_dma_bw8 0x00000000 -#define regk_bif_dma_dack 0x00000006 -#define regk_bif_dma_dack_inv 0x00000007 -#define regk_bif_dma_force 0x00000001 -#define regk_bif_dma_hi 0x00000003 -#define regk_bif_dma_inv 0x00000003 -#define regk_bif_dma_lo 0x00000002 -#define regk_bif_dma_master 0x00000001 -#define regk_bif_dma_no 0x00000000 -#define regk_bif_dma_norm 0x00000002 -#define regk_bif_dma_off 0x00000000 -#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch0_start_default 0x00000000 -#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch1_start_default 0x00000000 -#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch2_start_default 0x00000000 -#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch3_start_default 0x00000000 -#define regk_bif_dma_rw_intr_mask_default 0x00000000 -#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 -#define regk_bif_dma_slave 0x00000002 -#define regk_bif_dma_sreq 0x00000006 -#define regk_bif_dma_sreq_inv 0x00000007 -#define regk_bif_dma_tc 0x00000004 -#define regk_bif_dma_tc_inv 0x00000005 -#define regk_bif_dma_yes 0x00000001 -#endif /* __bif_dma_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h deleted file mode 100644 index 031f33a365bb..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_asm_h -#define __bif_slave_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 -#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 -#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 -#define reg_bif_slave_rw_slave_cfg___loopback___width 1 -#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 -#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 -#define reg_bif_slave_rw_slave_cfg___dis___width 1 -#define reg_bif_slave_rw_slave_cfg___dis___bit 6 -#define reg_bif_slave_rw_slave_cfg_offset 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 -#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 -#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 -#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 -#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 -#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 -#define reg_bif_slave_r_slave_mode_offset 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch0_cfg_offset 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch1_cfg_offset 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch2_cfg_offset 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch3_cfg_offset 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 -#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 -#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 -#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 -#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 -#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___release___lsb 7 -#define reg_bif_slave_rw_arb_cfg___release___width 2 -#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 -#define reg_bif_slave_rw_arb_cfg___acquire___width 1 -#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 -#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 -#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 -#define reg_bif_slave_rw_arb_cfg_offset 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 -#define reg_bif_slave_r_arb_stat___init_mode___width 1 -#define reg_bif_slave_r_arb_stat___init_mode___bit 0 -#define reg_bif_slave_r_arb_stat___mode___lsb 1 -#define reg_bif_slave_r_arb_stat___mode___width 1 -#define reg_bif_slave_r_arb_stat___mode___bit 1 -#define reg_bif_slave_r_arb_stat___brin___lsb 2 -#define reg_bif_slave_r_arb_stat___brin___width 1 -#define reg_bif_slave_r_arb_stat___brin___bit 2 -#define reg_bif_slave_r_arb_stat___brout___lsb 3 -#define reg_bif_slave_r_arb_stat___brout___width 1 -#define reg_bif_slave_r_arb_stat___brout___bit 3 -#define reg_bif_slave_r_arb_stat___bg___lsb 4 -#define reg_bif_slave_r_arb_stat___bg___width 1 -#define reg_bif_slave_r_arb_stat___bg___bit 4 -#define reg_bif_slave_r_arb_stat_offset 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 -#define reg_bif_slave_rw_intr_mask___bus_release___width 1 -#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 -#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 -#define reg_bif_slave_rw_intr_mask_offset 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 -#define reg_bif_slave_rw_ack_intr___bus_release___width 1 -#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 -#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 -#define reg_bif_slave_rw_ack_intr_offset 68 - -/* Register r_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_intr___bus_release___lsb 0 -#define reg_bif_slave_r_intr___bus_release___width 1 -#define reg_bif_slave_r_intr___bus_release___bit 0 -#define reg_bif_slave_r_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_intr___bus_acquire___width 1 -#define reg_bif_slave_r_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_intr_offset 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 -#define reg_bif_slave_r_masked_intr___bus_release___width 1 -#define reg_bif_slave_r_masked_intr___bus_release___bit 0 -#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_masked_intr_offset 76 - - -/* Constants */ -#define regk_bif_slave_active_hi 0x00000003 -#define regk_bif_slave_active_lo 0x00000002 -#define regk_bif_slave_addr 0x00000000 -#define regk_bif_slave_always 0x00000001 -#define regk_bif_slave_at_idle 0x00000002 -#define regk_bif_slave_burst_end 0x00000003 -#define regk_bif_slave_dma 0x00000001 -#define regk_bif_slave_hi 0x00000003 -#define regk_bif_slave_inv 0x00000001 -#define regk_bif_slave_lo 0x00000002 -#define regk_bif_slave_local 0x00000001 -#define regk_bif_slave_master 0x00000000 -#define regk_bif_slave_mode_reg 0x00000001 -#define regk_bif_slave_no 0x00000000 -#define regk_bif_slave_norm 0x00000000 -#define regk_bif_slave_on_access 0x00000000 -#define regk_bif_slave_rw_arb_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 -#define regk_bif_slave_rw_intr_mask_default 0x00000000 -#define regk_bif_slave_rw_slave_cfg_default 0x00000000 -#define regk_bif_slave_shared 0x00000000 -#define regk_bif_slave_slave 0x00000001 -#define regk_bif_slave_t0ns 0x00000003 -#define regk_bif_slave_t10ns 0x00000002 -#define regk_bif_slave_t20ns 0x00000003 -#define regk_bif_slave_t30ns 0x00000002 -#define regk_bif_slave_t40ns 0x00000001 -#define regk_bif_slave_t50ns 0x00000000 -#define regk_bif_slave_yes 0x00000001 -#define regk_bif_slave_z 0x00000004 -#endif /* __bif_slave_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h deleted file mode 100644 index e98476332e1f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h deleted file mode 100644 index 7f768db272e2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef __cris_defs_asm_h -#define __cris_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/crisp/doc/cris.r - * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp - * last modfied: Mon Apr 11 16:06:39 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r - * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gc_cfg, scope cris, type rw */ -#define reg_cris_rw_gc_cfg___ic___lsb 0 -#define reg_cris_rw_gc_cfg___ic___width 1 -#define reg_cris_rw_gc_cfg___ic___bit 0 -#define reg_cris_rw_gc_cfg___dc___lsb 1 -#define reg_cris_rw_gc_cfg___dc___width 1 -#define reg_cris_rw_gc_cfg___dc___bit 1 -#define reg_cris_rw_gc_cfg___im___lsb 2 -#define reg_cris_rw_gc_cfg___im___width 1 -#define reg_cris_rw_gc_cfg___im___bit 2 -#define reg_cris_rw_gc_cfg___dm___lsb 3 -#define reg_cris_rw_gc_cfg___dm___width 1 -#define reg_cris_rw_gc_cfg___dm___bit 3 -#define reg_cris_rw_gc_cfg___gb___lsb 4 -#define reg_cris_rw_gc_cfg___gb___width 1 -#define reg_cris_rw_gc_cfg___gb___bit 4 -#define reg_cris_rw_gc_cfg___gk___lsb 5 -#define reg_cris_rw_gc_cfg___gk___width 1 -#define reg_cris_rw_gc_cfg___gk___bit 5 -#define reg_cris_rw_gc_cfg___gp___lsb 6 -#define reg_cris_rw_gc_cfg___gp___width 1 -#define reg_cris_rw_gc_cfg___gp___bit 6 -#define reg_cris_rw_gc_cfg_offset 0 - -/* Register rw_gc_ccs, scope cris, type rw */ -#define reg_cris_rw_gc_ccs_offset 4 - -/* Register rw_gc_srs, scope cris, type rw */ -#define reg_cris_rw_gc_srs___srs___lsb 0 -#define reg_cris_rw_gc_srs___srs___width 8 -#define reg_cris_rw_gc_srs_offset 8 - -/* Register rw_gc_nrp, scope cris, type rw */ -#define reg_cris_rw_gc_nrp_offset 12 - -/* Register rw_gc_exs, scope cris, type rw */ -#define reg_cris_rw_gc_exs_offset 16 - -/* Register rw_gc_eda, scope cris, type rw */ -#define reg_cris_rw_gc_eda_offset 20 - -/* Register rw_gc_r0, scope cris, type rw */ -#define reg_cris_rw_gc_r0_offset 32 - -/* Register rw_gc_r1, scope cris, type rw */ -#define reg_cris_rw_gc_r1_offset 36 - -/* Register rw_gc_r2, scope cris, type rw */ -#define reg_cris_rw_gc_r2_offset 40 - -/* Register rw_gc_r3, scope cris, type rw */ -#define reg_cris_rw_gc_r3_offset 44 - - -/* Constants */ -#define regk_cris_no 0x00000000 -#define regk_cris_rw_gc_cfg_default 0x00000000 -#define regk_cris_yes 0x00000001 -#endif /* __cris_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h deleted file mode 100644 index 7d3689a6f80d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h +++ /dev/null @@ -1,10 +0,0 @@ -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_EDA 5 -#define RW_GC_R0 8 -#define RW_GC_R1 9 -#define RW_GC_R2 10 -#define RW_GC_R3 11 diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h deleted file mode 100644 index 0cb71bc127ae..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h +++ /dev/null @@ -1,368 +0,0 @@ -#ifndef __dma_defs_asm_h -#define __dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope dma, type rw */ -#define reg_dma_rw_data_offset 0 - -/* Register rw_data_next, scope dma, type rw */ -#define reg_dma_rw_data_next_offset 4 - -/* Register rw_data_buf, scope dma, type rw */ -#define reg_dma_rw_data_buf_offset 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -#define reg_dma_rw_data_ctrl___eol___lsb 0 -#define reg_dma_rw_data_ctrl___eol___width 1 -#define reg_dma_rw_data_ctrl___eol___bit 0 -#define reg_dma_rw_data_ctrl___out_eop___lsb 3 -#define reg_dma_rw_data_ctrl___out_eop___width 1 -#define reg_dma_rw_data_ctrl___out_eop___bit 3 -#define reg_dma_rw_data_ctrl___intr___lsb 4 -#define reg_dma_rw_data_ctrl___intr___width 1 -#define reg_dma_rw_data_ctrl___intr___bit 4 -#define reg_dma_rw_data_ctrl___wait___lsb 5 -#define reg_dma_rw_data_ctrl___wait___width 1 -#define reg_dma_rw_data_ctrl___wait___bit 5 -#define reg_dma_rw_data_ctrl_offset 12 - -/* Register rw_data_stat, scope dma, type rw */ -#define reg_dma_rw_data_stat___in_eop___lsb 3 -#define reg_dma_rw_data_stat___in_eop___width 1 -#define reg_dma_rw_data_stat___in_eop___bit 3 -#define reg_dma_rw_data_stat_offset 16 - -/* Register rw_data_md, scope dma, type rw */ -#define reg_dma_rw_data_md___md___lsb 0 -#define reg_dma_rw_data_md___md___width 16 -#define reg_dma_rw_data_md_offset 20 - -/* Register rw_data_md_s, scope dma, type rw */ -#define reg_dma_rw_data_md_s___md_s___lsb 0 -#define reg_dma_rw_data_md_s___md_s___width 16 -#define reg_dma_rw_data_md_s_offset 24 - -/* Register rw_data_after, scope dma, type rw */ -#define reg_dma_rw_data_after_offset 28 - -/* Register rw_ctxt, scope dma, type rw */ -#define reg_dma_rw_ctxt_offset 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -#define reg_dma_rw_ctxt_next_offset 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 -#define reg_dma_rw_ctxt_ctrl___eol___width 1 -#define reg_dma_rw_ctxt_ctrl___eol___bit 0 -#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 -#define reg_dma_rw_ctxt_ctrl___intr___width 1 -#define reg_dma_rw_ctxt_ctrl___intr___bit 4 -#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 -#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 -#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 -#define reg_dma_rw_ctxt_ctrl___en___lsb 7 -#define reg_dma_rw_ctxt_ctrl___en___width 1 -#define reg_dma_rw_ctxt_ctrl___en___bit 7 -#define reg_dma_rw_ctxt_ctrl_offset 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -#define reg_dma_rw_ctxt_stat___dis___lsb 7 -#define reg_dma_rw_ctxt_stat___dis___width 1 -#define reg_dma_rw_ctxt_stat___dis___bit 7 -#define reg_dma_rw_ctxt_stat_offset 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0___md0___lsb 0 -#define reg_dma_rw_ctxt_md0___md0___width 16 -#define reg_dma_rw_ctxt_md0_offset 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 -#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 -#define reg_dma_rw_ctxt_md0_s_offset 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_offset 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_s_offset 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_offset 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_s_offset 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_offset 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_s_offset 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_offset 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_s_offset 84 - -/* Register rw_saved_data, scope dma, type rw */ -#define reg_dma_rw_saved_data_offset 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -#define reg_dma_rw_saved_data_buf_offset 92 - -/* Register rw_group, scope dma, type rw */ -#define reg_dma_rw_group_offset 96 - -/* Register rw_group_next, scope dma, type rw */ -#define reg_dma_rw_group_next_offset 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -#define reg_dma_rw_group_ctrl___eol___lsb 0 -#define reg_dma_rw_group_ctrl___eol___width 1 -#define reg_dma_rw_group_ctrl___eol___bit 0 -#define reg_dma_rw_group_ctrl___tol___lsb 1 -#define reg_dma_rw_group_ctrl___tol___width 1 -#define reg_dma_rw_group_ctrl___tol___bit 1 -#define reg_dma_rw_group_ctrl___bol___lsb 2 -#define reg_dma_rw_group_ctrl___bol___width 1 -#define reg_dma_rw_group_ctrl___bol___bit 2 -#define reg_dma_rw_group_ctrl___intr___lsb 4 -#define reg_dma_rw_group_ctrl___intr___width 1 -#define reg_dma_rw_group_ctrl___intr___bit 4 -#define reg_dma_rw_group_ctrl___en___lsb 7 -#define reg_dma_rw_group_ctrl___en___width 1 -#define reg_dma_rw_group_ctrl___en___bit 7 -#define reg_dma_rw_group_ctrl_offset 104 - -/* Register rw_group_stat, scope dma, type rw */ -#define reg_dma_rw_group_stat___dis___lsb 7 -#define reg_dma_rw_group_stat___dis___width 1 -#define reg_dma_rw_group_stat___dis___bit 7 -#define reg_dma_rw_group_stat_offset 108 - -/* Register rw_group_md, scope dma, type rw */ -#define reg_dma_rw_group_md___md___lsb 0 -#define reg_dma_rw_group_md___md___width 16 -#define reg_dma_rw_group_md_offset 112 - -/* Register rw_group_md_s, scope dma, type rw */ -#define reg_dma_rw_group_md_s___md_s___lsb 0 -#define reg_dma_rw_group_md_s___md_s___width 16 -#define reg_dma_rw_group_md_s_offset 116 - -/* Register rw_group_up, scope dma, type rw */ -#define reg_dma_rw_group_up_offset 120 - -/* Register rw_group_down, scope dma, type rw */ -#define reg_dma_rw_group_down_offset 124 - -/* Register rw_cmd, scope dma, type rw */ -#define reg_dma_rw_cmd___cont_data___lsb 0 -#define reg_dma_rw_cmd___cont_data___width 1 -#define reg_dma_rw_cmd___cont_data___bit 0 -#define reg_dma_rw_cmd_offset 128 - -/* Register rw_cfg, scope dma, type rw */ -#define reg_dma_rw_cfg___en___lsb 0 -#define reg_dma_rw_cfg___en___width 1 -#define reg_dma_rw_cfg___en___bit 0 -#define reg_dma_rw_cfg___stop___lsb 1 -#define reg_dma_rw_cfg___stop___width 1 -#define reg_dma_rw_cfg___stop___bit 1 -#define reg_dma_rw_cfg_offset 132 - -/* Register rw_stat, scope dma, type rw */ -#define reg_dma_rw_stat___mode___lsb 0 -#define reg_dma_rw_stat___mode___width 5 -#define reg_dma_rw_stat___list_state___lsb 5 -#define reg_dma_rw_stat___list_state___width 3 -#define reg_dma_rw_stat___stream_cmd_src___lsb 8 -#define reg_dma_rw_stat___stream_cmd_src___width 8 -#define reg_dma_rw_stat___buf___lsb 24 -#define reg_dma_rw_stat___buf___width 8 -#define reg_dma_rw_stat_offset 136 - -/* Register rw_intr_mask, scope dma, type rw */ -#define reg_dma_rw_intr_mask___group___lsb 0 -#define reg_dma_rw_intr_mask___group___width 1 -#define reg_dma_rw_intr_mask___group___bit 0 -#define reg_dma_rw_intr_mask___ctxt___lsb 1 -#define reg_dma_rw_intr_mask___ctxt___width 1 -#define reg_dma_rw_intr_mask___ctxt___bit 1 -#define reg_dma_rw_intr_mask___data___lsb 2 -#define reg_dma_rw_intr_mask___data___width 1 -#define reg_dma_rw_intr_mask___data___bit 2 -#define reg_dma_rw_intr_mask___in_eop___lsb 3 -#define reg_dma_rw_intr_mask___in_eop___width 1 -#define reg_dma_rw_intr_mask___in_eop___bit 3 -#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 -#define reg_dma_rw_intr_mask___stream_cmd___width 1 -#define reg_dma_rw_intr_mask___stream_cmd___bit 4 -#define reg_dma_rw_intr_mask_offset 140 - -/* Register rw_ack_intr, scope dma, type rw */ -#define reg_dma_rw_ack_intr___group___lsb 0 -#define reg_dma_rw_ack_intr___group___width 1 -#define reg_dma_rw_ack_intr___group___bit 0 -#define reg_dma_rw_ack_intr___ctxt___lsb 1 -#define reg_dma_rw_ack_intr___ctxt___width 1 -#define reg_dma_rw_ack_intr___ctxt___bit 1 -#define reg_dma_rw_ack_intr___data___lsb 2 -#define reg_dma_rw_ack_intr___data___width 1 -#define reg_dma_rw_ack_intr___data___bit 2 -#define reg_dma_rw_ack_intr___in_eop___lsb 3 -#define reg_dma_rw_ack_intr___in_eop___width 1 -#define reg_dma_rw_ack_intr___in_eop___bit 3 -#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 -#define reg_dma_rw_ack_intr___stream_cmd___width 1 -#define reg_dma_rw_ack_intr___stream_cmd___bit 4 -#define reg_dma_rw_ack_intr_offset 144 - -/* Register r_intr, scope dma, type r */ -#define reg_dma_r_intr___group___lsb 0 -#define reg_dma_r_intr___group___width 1 -#define reg_dma_r_intr___group___bit 0 -#define reg_dma_r_intr___ctxt___lsb 1 -#define reg_dma_r_intr___ctxt___width 1 -#define reg_dma_r_intr___ctxt___bit 1 -#define reg_dma_r_intr___data___lsb 2 -#define reg_dma_r_intr___data___width 1 -#define reg_dma_r_intr___data___bit 2 -#define reg_dma_r_intr___in_eop___lsb 3 -#define reg_dma_r_intr___in_eop___width 1 -#define reg_dma_r_intr___in_eop___bit 3 -#define reg_dma_r_intr___stream_cmd___lsb 4 -#define reg_dma_r_intr___stream_cmd___width 1 -#define reg_dma_r_intr___stream_cmd___bit 4 -#define reg_dma_r_intr_offset 148 - -/* Register r_masked_intr, scope dma, type r */ -#define reg_dma_r_masked_intr___group___lsb 0 -#define reg_dma_r_masked_intr___group___width 1 -#define reg_dma_r_masked_intr___group___bit 0 -#define reg_dma_r_masked_intr___ctxt___lsb 1 -#define reg_dma_r_masked_intr___ctxt___width 1 -#define reg_dma_r_masked_intr___ctxt___bit 1 -#define reg_dma_r_masked_intr___data___lsb 2 -#define reg_dma_r_masked_intr___data___width 1 -#define reg_dma_r_masked_intr___data___bit 2 -#define reg_dma_r_masked_intr___in_eop___lsb 3 -#define reg_dma_r_masked_intr___in_eop___width 1 -#define reg_dma_r_masked_intr___in_eop___bit 3 -#define reg_dma_r_masked_intr___stream_cmd___lsb 4 -#define reg_dma_r_masked_intr___stream_cmd___width 1 -#define reg_dma_r_masked_intr___stream_cmd___bit 4 -#define reg_dma_r_masked_intr_offset 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -#define reg_dma_rw_stream_cmd___cmd___lsb 0 -#define reg_dma_rw_stream_cmd___cmd___width 10 -#define reg_dma_rw_stream_cmd___n___lsb 16 -#define reg_dma_rw_stream_cmd___n___width 8 -#define reg_dma_rw_stream_cmd___busy___lsb 31 -#define reg_dma_rw_stream_cmd___busy___width 1 -#define reg_dma_rw_stream_cmd___busy___bit 31 -#define reg_dma_rw_stream_cmd_offset 156 - - -/* Constants */ -#define regk_dma_ack_pkt 0x00000100 -#define regk_dma_anytime 0x00000001 -#define regk_dma_array 0x00000008 -#define regk_dma_burst 0x00000020 -#define regk_dma_client 0x00000002 -#define regk_dma_copy_next 0x00000010 -#define regk_dma_copy_up 0x00000020 -#define regk_dma_data_at_eol 0x00000001 -#define regk_dma_dis_c 0x00000010 -#define regk_dma_dis_g 0x00000020 -#define regk_dma_idle 0x00000001 -#define regk_dma_intern 0x00000004 -#define regk_dma_load_c 0x00000200 -#define regk_dma_load_c_n 0x00000280 -#define regk_dma_load_c_next 0x00000240 -#define regk_dma_load_d 0x00000140 -#define regk_dma_load_g 0x00000300 -#define regk_dma_load_g_down 0x000003c0 -#define regk_dma_load_g_next 0x00000340 -#define regk_dma_load_g_up 0x00000380 -#define regk_dma_next_en 0x00000010 -#define regk_dma_next_pkt 0x00000010 -#define regk_dma_no 0x00000000 -#define regk_dma_only_at_wait 0x00000000 -#define regk_dma_restore 0x00000020 -#define regk_dma_rst 0x00000001 -#define regk_dma_running 0x00000004 -#define regk_dma_rw_cfg_default 0x00000000 -#define regk_dma_rw_cmd_default 0x00000000 -#define regk_dma_rw_intr_mask_default 0x00000000 -#define regk_dma_rw_stat_default 0x00000101 -#define regk_dma_rw_stream_cmd_default 0x00000000 -#define regk_dma_save_down 0x00000020 -#define regk_dma_save_up 0x00000020 -#define regk_dma_set_reg 0x00000050 -#define regk_dma_set_w_size1 0x00000190 -#define regk_dma_set_w_size2 0x000001a0 -#define regk_dma_set_w_size4 0x000001c0 -#define regk_dma_stopped 0x00000002 -#define regk_dma_store_c 0x00000002 -#define regk_dma_store_descr 0x00000000 -#define regk_dma_store_g 0x00000004 -#define regk_dma_store_md 0x00000001 -#define regk_dma_sw 0x00000008 -#define regk_dma_update_down 0x00000020 -#define regk_dma_yes 0x00000001 -#endif /* __dma_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h deleted file mode 100644 index c9f49864831b..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h +++ /dev/null @@ -1,498 +0,0 @@ -#ifndef __eth_defs_asm_h -#define __eth_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/eth/rtl/eth_regs.r - * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp - * last modfied: Mon Apr 11 16:07:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r - * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ma0_lo, scope eth, type rw */ -#define reg_eth_rw_ma0_lo___addr___lsb 0 -#define reg_eth_rw_ma0_lo___addr___width 32 -#define reg_eth_rw_ma0_lo_offset 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -#define reg_eth_rw_ma0_hi___addr___lsb 0 -#define reg_eth_rw_ma0_hi___addr___width 16 -#define reg_eth_rw_ma0_hi_offset 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -#define reg_eth_rw_ma1_lo___addr___lsb 0 -#define reg_eth_rw_ma1_lo___addr___width 32 -#define reg_eth_rw_ma1_lo_offset 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -#define reg_eth_rw_ma1_hi___addr___lsb 0 -#define reg_eth_rw_ma1_hi___addr___width 16 -#define reg_eth_rw_ma1_hi_offset 12 - -/* Register rw_ga_lo, scope eth, type rw */ -#define reg_eth_rw_ga_lo___table___lsb 0 -#define reg_eth_rw_ga_lo___table___width 32 -#define reg_eth_rw_ga_lo_offset 16 - -/* Register rw_ga_hi, scope eth, type rw */ -#define reg_eth_rw_ga_hi___table___lsb 0 -#define reg_eth_rw_ga_hi___table___width 32 -#define reg_eth_rw_ga_hi_offset 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -#define reg_eth_rw_gen_ctrl___en___lsb 0 -#define reg_eth_rw_gen_ctrl___en___width 1 -#define reg_eth_rw_gen_ctrl___en___bit 0 -#define reg_eth_rw_gen_ctrl___phy___lsb 1 -#define reg_eth_rw_gen_ctrl___phy___width 2 -#define reg_eth_rw_gen_ctrl___protocol___lsb 3 -#define reg_eth_rw_gen_ctrl___protocol___width 1 -#define reg_eth_rw_gen_ctrl___protocol___bit 3 -#define reg_eth_rw_gen_ctrl___loopback___lsb 4 -#define reg_eth_rw_gen_ctrl___loopback___width 1 -#define reg_eth_rw_gen_ctrl___loopback___bit 4 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 -#define reg_eth_rw_gen_ctrl_offset 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -#define reg_eth_rw_rec_ctrl___ma0___lsb 0 -#define reg_eth_rw_rec_ctrl___ma0___width 1 -#define reg_eth_rw_rec_ctrl___ma0___bit 0 -#define reg_eth_rw_rec_ctrl___ma1___lsb 1 -#define reg_eth_rw_rec_ctrl___ma1___width 1 -#define reg_eth_rw_rec_ctrl___ma1___bit 1 -#define reg_eth_rw_rec_ctrl___individual___lsb 2 -#define reg_eth_rw_rec_ctrl___individual___width 1 -#define reg_eth_rw_rec_ctrl___individual___bit 2 -#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 -#define reg_eth_rw_rec_ctrl___broadcast___width 1 -#define reg_eth_rw_rec_ctrl___broadcast___bit 3 -#define reg_eth_rw_rec_ctrl___undersize___lsb 4 -#define reg_eth_rw_rec_ctrl___undersize___width 1 -#define reg_eth_rw_rec_ctrl___undersize___bit 4 -#define reg_eth_rw_rec_ctrl___oversize___lsb 5 -#define reg_eth_rw_rec_ctrl___oversize___width 1 -#define reg_eth_rw_rec_ctrl___oversize___bit 5 -#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 -#define reg_eth_rw_rec_ctrl___bad_crc___width 1 -#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 -#define reg_eth_rw_rec_ctrl___duplex___lsb 7 -#define reg_eth_rw_rec_ctrl___duplex___width 1 -#define reg_eth_rw_rec_ctrl___duplex___bit 7 -#define reg_eth_rw_rec_ctrl___max_size___lsb 8 -#define reg_eth_rw_rec_ctrl___max_size___width 1 -#define reg_eth_rw_rec_ctrl___max_size___bit 8 -#define reg_eth_rw_rec_ctrl_offset 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -#define reg_eth_rw_tr_ctrl___crc___lsb 0 -#define reg_eth_rw_tr_ctrl___crc___width 1 -#define reg_eth_rw_tr_ctrl___crc___bit 0 -#define reg_eth_rw_tr_ctrl___pad___lsb 1 -#define reg_eth_rw_tr_ctrl___pad___width 1 -#define reg_eth_rw_tr_ctrl___pad___bit 1 -#define reg_eth_rw_tr_ctrl___retry___lsb 2 -#define reg_eth_rw_tr_ctrl___retry___width 1 -#define reg_eth_rw_tr_ctrl___retry___bit 2 -#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 -#define reg_eth_rw_tr_ctrl___ignore_col___width 1 -#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 -#define reg_eth_rw_tr_ctrl___cancel___lsb 4 -#define reg_eth_rw_tr_ctrl___cancel___width 1 -#define reg_eth_rw_tr_ctrl___cancel___bit 4 -#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 -#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 -#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 -#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 -#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 -#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 -#define reg_eth_rw_tr_ctrl_offset 32 - -/* Register rw_clr_err, scope eth, type rw */ -#define reg_eth_rw_clr_err___clr___lsb 0 -#define reg_eth_rw_clr_err___clr___width 1 -#define reg_eth_rw_clr_err___clr___bit 0 -#define reg_eth_rw_clr_err_offset 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 -#define reg_eth_rw_mgm_ctrl___mdio___width 1 -#define reg_eth_rw_mgm_ctrl___mdio___bit 0 -#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 -#define reg_eth_rw_mgm_ctrl___mdoe___width 1 -#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 -#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 -#define reg_eth_rw_mgm_ctrl___mdc___width 1 -#define reg_eth_rw_mgm_ctrl___mdc___bit 2 -#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 -#define reg_eth_rw_mgm_ctrl___phyclk___width 1 -#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 -#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 -#define reg_eth_rw_mgm_ctrl___txdata___width 4 -#define reg_eth_rw_mgm_ctrl___txen___lsb 8 -#define reg_eth_rw_mgm_ctrl___txen___width 1 -#define reg_eth_rw_mgm_ctrl___txen___bit 8 -#define reg_eth_rw_mgm_ctrl_offset 40 - -/* Register r_stat, scope eth, type r */ -#define reg_eth_r_stat___mdio___lsb 0 -#define reg_eth_r_stat___mdio___width 1 -#define reg_eth_r_stat___mdio___bit 0 -#define reg_eth_r_stat___exc_col___lsb 1 -#define reg_eth_r_stat___exc_col___width 1 -#define reg_eth_r_stat___exc_col___bit 1 -#define reg_eth_r_stat___urun___lsb 2 -#define reg_eth_r_stat___urun___width 1 -#define reg_eth_r_stat___urun___bit 2 -#define reg_eth_r_stat___phyclk___lsb 3 -#define reg_eth_r_stat___phyclk___width 1 -#define reg_eth_r_stat___phyclk___bit 3 -#define reg_eth_r_stat___txdata___lsb 4 -#define reg_eth_r_stat___txdata___width 4 -#define reg_eth_r_stat___txen___lsb 8 -#define reg_eth_r_stat___txen___width 1 -#define reg_eth_r_stat___txen___bit 8 -#define reg_eth_r_stat___col___lsb 9 -#define reg_eth_r_stat___col___width 1 -#define reg_eth_r_stat___col___bit 9 -#define reg_eth_r_stat___crs___lsb 10 -#define reg_eth_r_stat___crs___width 1 -#define reg_eth_r_stat___crs___bit 10 -#define reg_eth_r_stat___txclk___lsb 11 -#define reg_eth_r_stat___txclk___width 1 -#define reg_eth_r_stat___txclk___bit 11 -#define reg_eth_r_stat___rxdata___lsb 12 -#define reg_eth_r_stat___rxdata___width 4 -#define reg_eth_r_stat___rxer___lsb 16 -#define reg_eth_r_stat___rxer___width 1 -#define reg_eth_r_stat___rxer___bit 16 -#define reg_eth_r_stat___rxdv___lsb 17 -#define reg_eth_r_stat___rxdv___width 1 -#define reg_eth_r_stat___rxdv___bit 17 -#define reg_eth_r_stat___rxclk___lsb 18 -#define reg_eth_r_stat___rxclk___width 1 -#define reg_eth_r_stat___rxclk___bit 18 -#define reg_eth_r_stat_offset 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -#define reg_eth_rs_rec_cnt___crc_err___lsb 0 -#define reg_eth_rs_rec_cnt___crc_err___width 8 -#define reg_eth_rs_rec_cnt___align_err___lsb 8 -#define reg_eth_rs_rec_cnt___align_err___width 8 -#define reg_eth_rs_rec_cnt___oversize___lsb 16 -#define reg_eth_rs_rec_cnt___oversize___width 8 -#define reg_eth_rs_rec_cnt___congestion___lsb 24 -#define reg_eth_rs_rec_cnt___congestion___width 8 -#define reg_eth_rs_rec_cnt_offset 48 - -/* Register r_rec_cnt, scope eth, type r */ -#define reg_eth_r_rec_cnt___crc_err___lsb 0 -#define reg_eth_r_rec_cnt___crc_err___width 8 -#define reg_eth_r_rec_cnt___align_err___lsb 8 -#define reg_eth_r_rec_cnt___align_err___width 8 -#define reg_eth_r_rec_cnt___oversize___lsb 16 -#define reg_eth_r_rec_cnt___oversize___width 8 -#define reg_eth_r_rec_cnt___congestion___lsb 24 -#define reg_eth_r_rec_cnt___congestion___width 8 -#define reg_eth_r_rec_cnt_offset 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -#define reg_eth_rs_tr_cnt___single_col___lsb 0 -#define reg_eth_rs_tr_cnt___single_col___width 8 -#define reg_eth_rs_tr_cnt___mult_col___lsb 8 -#define reg_eth_rs_tr_cnt___mult_col___width 8 -#define reg_eth_rs_tr_cnt___late_col___lsb 16 -#define reg_eth_rs_tr_cnt___late_col___width 8 -#define reg_eth_rs_tr_cnt___deferred___lsb 24 -#define reg_eth_rs_tr_cnt___deferred___width 8 -#define reg_eth_rs_tr_cnt_offset 56 - -/* Register r_tr_cnt, scope eth, type r */ -#define reg_eth_r_tr_cnt___single_col___lsb 0 -#define reg_eth_r_tr_cnt___single_col___width 8 -#define reg_eth_r_tr_cnt___mult_col___lsb 8 -#define reg_eth_r_tr_cnt___mult_col___width 8 -#define reg_eth_r_tr_cnt___late_col___lsb 16 -#define reg_eth_r_tr_cnt___late_col___width 8 -#define reg_eth_r_tr_cnt___deferred___lsb 24 -#define reg_eth_r_tr_cnt___deferred___width 8 -#define reg_eth_r_tr_cnt_offset 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_rs_phy_cnt___carrier_loss___width 8 -#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 -#define reg_eth_rs_phy_cnt___sqe_err___width 8 -#define reg_eth_rs_phy_cnt_offset 64 - -/* Register r_phy_cnt, scope eth, type r */ -#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_r_phy_cnt___carrier_loss___width 8 -#define reg_eth_r_phy_cnt___sqe_err___lsb 8 -#define reg_eth_r_phy_cnt___sqe_err___width 8 -#define reg_eth_r_phy_cnt_offset 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 -#define reg_eth_rw_test_ctrl___snmp_inc___width 1 -#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 -#define reg_eth_rw_test_ctrl___snmp___lsb 1 -#define reg_eth_rw_test_ctrl___snmp___width 1 -#define reg_eth_rw_test_ctrl___snmp___bit 1 -#define reg_eth_rw_test_ctrl___backoff___lsb 2 -#define reg_eth_rw_test_ctrl___backoff___width 1 -#define reg_eth_rw_test_ctrl___backoff___bit 2 -#define reg_eth_rw_test_ctrl_offset 72 - -/* Register rw_intr_mask, scope eth, type rw */ -#define reg_eth_rw_intr_mask___crc___lsb 0 -#define reg_eth_rw_intr_mask___crc___width 1 -#define reg_eth_rw_intr_mask___crc___bit 0 -#define reg_eth_rw_intr_mask___align___lsb 1 -#define reg_eth_rw_intr_mask___align___width 1 -#define reg_eth_rw_intr_mask___align___bit 1 -#define reg_eth_rw_intr_mask___oversize___lsb 2 -#define reg_eth_rw_intr_mask___oversize___width 1 -#define reg_eth_rw_intr_mask___oversize___bit 2 -#define reg_eth_rw_intr_mask___congestion___lsb 3 -#define reg_eth_rw_intr_mask___congestion___width 1 -#define reg_eth_rw_intr_mask___congestion___bit 3 -#define reg_eth_rw_intr_mask___single_col___lsb 4 -#define reg_eth_rw_intr_mask___single_col___width 1 -#define reg_eth_rw_intr_mask___single_col___bit 4 -#define reg_eth_rw_intr_mask___mult_col___lsb 5 -#define reg_eth_rw_intr_mask___mult_col___width 1 -#define reg_eth_rw_intr_mask___mult_col___bit 5 -#define reg_eth_rw_intr_mask___late_col___lsb 6 -#define reg_eth_rw_intr_mask___late_col___width 1 -#define reg_eth_rw_intr_mask___late_col___bit 6 -#define reg_eth_rw_intr_mask___deferred___lsb 7 -#define reg_eth_rw_intr_mask___deferred___width 1 -#define reg_eth_rw_intr_mask___deferred___bit 7 -#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 -#define reg_eth_rw_intr_mask___carrier_loss___width 1 -#define reg_eth_rw_intr_mask___carrier_loss___bit 8 -#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 -#define reg_eth_rw_intr_mask___sqe_test_err___width 1 -#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 -#define reg_eth_rw_intr_mask___orun___lsb 10 -#define reg_eth_rw_intr_mask___orun___width 1 -#define reg_eth_rw_intr_mask___orun___bit 10 -#define reg_eth_rw_intr_mask___urun___lsb 11 -#define reg_eth_rw_intr_mask___urun___width 1 -#define reg_eth_rw_intr_mask___urun___bit 11 -#define reg_eth_rw_intr_mask___excessive_col___lsb 12 -#define reg_eth_rw_intr_mask___excessive_col___width 1 -#define reg_eth_rw_intr_mask___excessive_col___bit 12 -#define reg_eth_rw_intr_mask___mdio___lsb 13 -#define reg_eth_rw_intr_mask___mdio___width 1 -#define reg_eth_rw_intr_mask___mdio___bit 13 -#define reg_eth_rw_intr_mask_offset 76 - -/* Register rw_ack_intr, scope eth, type rw */ -#define reg_eth_rw_ack_intr___crc___lsb 0 -#define reg_eth_rw_ack_intr___crc___width 1 -#define reg_eth_rw_ack_intr___crc___bit 0 -#define reg_eth_rw_ack_intr___align___lsb 1 -#define reg_eth_rw_ack_intr___align___width 1 -#define reg_eth_rw_ack_intr___align___bit 1 -#define reg_eth_rw_ack_intr___oversize___lsb 2 -#define reg_eth_rw_ack_intr___oversize___width 1 -#define reg_eth_rw_ack_intr___oversize___bit 2 -#define reg_eth_rw_ack_intr___congestion___lsb 3 -#define reg_eth_rw_ack_intr___congestion___width 1 -#define reg_eth_rw_ack_intr___congestion___bit 3 -#define reg_eth_rw_ack_intr___single_col___lsb 4 -#define reg_eth_rw_ack_intr___single_col___width 1 -#define reg_eth_rw_ack_intr___single_col___bit 4 -#define reg_eth_rw_ack_intr___mult_col___lsb 5 -#define reg_eth_rw_ack_intr___mult_col___width 1 -#define reg_eth_rw_ack_intr___mult_col___bit 5 -#define reg_eth_rw_ack_intr___late_col___lsb 6 -#define reg_eth_rw_ack_intr___late_col___width 1 -#define reg_eth_rw_ack_intr___late_col___bit 6 -#define reg_eth_rw_ack_intr___deferred___lsb 7 -#define reg_eth_rw_ack_intr___deferred___width 1 -#define reg_eth_rw_ack_intr___deferred___bit 7 -#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 -#define reg_eth_rw_ack_intr___carrier_loss___width 1 -#define reg_eth_rw_ack_intr___carrier_loss___bit 8 -#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 -#define reg_eth_rw_ack_intr___sqe_test_err___width 1 -#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 -#define reg_eth_rw_ack_intr___orun___lsb 10 -#define reg_eth_rw_ack_intr___orun___width 1 -#define reg_eth_rw_ack_intr___orun___bit 10 -#define reg_eth_rw_ack_intr___urun___lsb 11 -#define reg_eth_rw_ack_intr___urun___width 1 -#define reg_eth_rw_ack_intr___urun___bit 11 -#define reg_eth_rw_ack_intr___excessive_col___lsb 12 -#define reg_eth_rw_ack_intr___excessive_col___width 1 -#define reg_eth_rw_ack_intr___excessive_col___bit 12 -#define reg_eth_rw_ack_intr___mdio___lsb 13 -#define reg_eth_rw_ack_intr___mdio___width 1 -#define reg_eth_rw_ack_intr___mdio___bit 13 -#define reg_eth_rw_ack_intr_offset 80 - -/* Register r_intr, scope eth, type r */ -#define reg_eth_r_intr___crc___lsb 0 -#define reg_eth_r_intr___crc___width 1 -#define reg_eth_r_intr___crc___bit 0 -#define reg_eth_r_intr___align___lsb 1 -#define reg_eth_r_intr___align___width 1 -#define reg_eth_r_intr___align___bit 1 -#define reg_eth_r_intr___oversize___lsb 2 -#define reg_eth_r_intr___oversize___width 1 -#define reg_eth_r_intr___oversize___bit 2 -#define reg_eth_r_intr___congestion___lsb 3 -#define reg_eth_r_intr___congestion___width 1 -#define reg_eth_r_intr___congestion___bit 3 -#define reg_eth_r_intr___single_col___lsb 4 -#define reg_eth_r_intr___single_col___width 1 -#define reg_eth_r_intr___single_col___bit 4 -#define reg_eth_r_intr___mult_col___lsb 5 -#define reg_eth_r_intr___mult_col___width 1 -#define reg_eth_r_intr___mult_col___bit 5 -#define reg_eth_r_intr___late_col___lsb 6 -#define reg_eth_r_intr___late_col___width 1 -#define reg_eth_r_intr___late_col___bit 6 -#define reg_eth_r_intr___deferred___lsb 7 -#define reg_eth_r_intr___deferred___width 1 -#define reg_eth_r_intr___deferred___bit 7 -#define reg_eth_r_intr___carrier_loss___lsb 8 -#define reg_eth_r_intr___carrier_loss___width 1 -#define reg_eth_r_intr___carrier_loss___bit 8 -#define reg_eth_r_intr___sqe_test_err___lsb 9 -#define reg_eth_r_intr___sqe_test_err___width 1 -#define reg_eth_r_intr___sqe_test_err___bit 9 -#define reg_eth_r_intr___orun___lsb 10 -#define reg_eth_r_intr___orun___width 1 -#define reg_eth_r_intr___orun___bit 10 -#define reg_eth_r_intr___urun___lsb 11 -#define reg_eth_r_intr___urun___width 1 -#define reg_eth_r_intr___urun___bit 11 -#define reg_eth_r_intr___excessive_col___lsb 12 -#define reg_eth_r_intr___excessive_col___width 1 -#define reg_eth_r_intr___excessive_col___bit 12 -#define reg_eth_r_intr___mdio___lsb 13 -#define reg_eth_r_intr___mdio___width 1 -#define reg_eth_r_intr___mdio___bit 13 -#define reg_eth_r_intr_offset 84 - -/* Register r_masked_intr, scope eth, type r */ -#define reg_eth_r_masked_intr___crc___lsb 0 -#define reg_eth_r_masked_intr___crc___width 1 -#define reg_eth_r_masked_intr___crc___bit 0 -#define reg_eth_r_masked_intr___align___lsb 1 -#define reg_eth_r_masked_intr___align___width 1 -#define reg_eth_r_masked_intr___align___bit 1 -#define reg_eth_r_masked_intr___oversize___lsb 2 -#define reg_eth_r_masked_intr___oversize___width 1 -#define reg_eth_r_masked_intr___oversize___bit 2 -#define reg_eth_r_masked_intr___congestion___lsb 3 -#define reg_eth_r_masked_intr___congestion___width 1 -#define reg_eth_r_masked_intr___congestion___bit 3 -#define reg_eth_r_masked_intr___single_col___lsb 4 -#define reg_eth_r_masked_intr___single_col___width 1 -#define reg_eth_r_masked_intr___single_col___bit 4 -#define reg_eth_r_masked_intr___mult_col___lsb 5 -#define reg_eth_r_masked_intr___mult_col___width 1 -#define reg_eth_r_masked_intr___mult_col___bit 5 -#define reg_eth_r_masked_intr___late_col___lsb 6 -#define reg_eth_r_masked_intr___late_col___width 1 -#define reg_eth_r_masked_intr___late_col___bit 6 -#define reg_eth_r_masked_intr___deferred___lsb 7 -#define reg_eth_r_masked_intr___deferred___width 1 -#define reg_eth_r_masked_intr___deferred___bit 7 -#define reg_eth_r_masked_intr___carrier_loss___lsb 8 -#define reg_eth_r_masked_intr___carrier_loss___width 1 -#define reg_eth_r_masked_intr___carrier_loss___bit 8 -#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 -#define reg_eth_r_masked_intr___sqe_test_err___width 1 -#define reg_eth_r_masked_intr___sqe_test_err___bit 9 -#define reg_eth_r_masked_intr___orun___lsb 10 -#define reg_eth_r_masked_intr___orun___width 1 -#define reg_eth_r_masked_intr___orun___bit 10 -#define reg_eth_r_masked_intr___urun___lsb 11 -#define reg_eth_r_masked_intr___urun___width 1 -#define reg_eth_r_masked_intr___urun___bit 11 -#define reg_eth_r_masked_intr___excessive_col___lsb 12 -#define reg_eth_r_masked_intr___excessive_col___width 1 -#define reg_eth_r_masked_intr___excessive_col___bit 12 -#define reg_eth_r_masked_intr___mdio___lsb 13 -#define reg_eth_r_masked_intr___mdio___width 1 -#define reg_eth_r_masked_intr___mdio___bit 13 -#define reg_eth_r_masked_intr_offset 88 - - -/* Constants */ -#define regk_eth_discard 0x00000000 -#define regk_eth_ether 0x00000000 -#define regk_eth_full 0x00000001 -#define regk_eth_half 0x00000000 -#define regk_eth_hsh 0x00000001 -#define regk_eth_mii 0x00000001 -#define regk_eth_mii_clk 0x00000000 -#define regk_eth_mii_rec 0x00000002 -#define regk_eth_no 0x00000000 -#define regk_eth_rec 0x00000001 -#define regk_eth_rw_ga_hi_default 0x00000000 -#define regk_eth_rw_ga_lo_default 0x00000000 -#define regk_eth_rw_gen_ctrl_default 0x00000000 -#define regk_eth_rw_intr_mask_default 0x00000000 -#define regk_eth_rw_ma0_hi_default 0x00000000 -#define regk_eth_rw_ma0_lo_default 0x00000000 -#define regk_eth_rw_ma1_hi_default 0x00000000 -#define regk_eth_rw_ma1_lo_default 0x00000000 -#define regk_eth_rw_mgm_ctrl_default 0x00000000 -#define regk_eth_rw_test_ctrl_default 0x00000000 -#define regk_eth_size1518 0x00000000 -#define regk_eth_size1522 0x00000001 -#define regk_eth_yes 0x00000001 -#endif /* __eth_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 35356bc08629..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h deleted file mode 100644 index c8315905c571..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h deleted file mode 100644 index 6df2a433b02d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h +++ /dev/null @@ -1,355 +0,0 @@ -#ifndef __intr_vect_defs_asm_h -#define __intr_vect_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mask, scope intr_vect, type rw */ -#define reg_intr_vect_rw_mask___memarb___lsb 0 -#define reg_intr_vect_rw_mask___memarb___width 1 -#define reg_intr_vect_rw_mask___memarb___bit 0 -#define reg_intr_vect_rw_mask___gen_io___lsb 1 -#define reg_intr_vect_rw_mask___gen_io___width 1 -#define reg_intr_vect_rw_mask___gen_io___bit 1 -#define reg_intr_vect_rw_mask___iop0___lsb 2 -#define reg_intr_vect_rw_mask___iop0___width 1 -#define reg_intr_vect_rw_mask___iop0___bit 2 -#define reg_intr_vect_rw_mask___iop1___lsb 3 -#define reg_intr_vect_rw_mask___iop1___width 1 -#define reg_intr_vect_rw_mask___iop1___bit 3 -#define reg_intr_vect_rw_mask___iop2___lsb 4 -#define reg_intr_vect_rw_mask___iop2___width 1 -#define reg_intr_vect_rw_mask___iop2___bit 4 -#define reg_intr_vect_rw_mask___iop3___lsb 5 -#define reg_intr_vect_rw_mask___iop3___width 1 -#define reg_intr_vect_rw_mask___iop3___bit 5 -#define reg_intr_vect_rw_mask___dma0___lsb 6 -#define reg_intr_vect_rw_mask___dma0___width 1 -#define reg_intr_vect_rw_mask___dma0___bit 6 -#define reg_intr_vect_rw_mask___dma1___lsb 7 -#define reg_intr_vect_rw_mask___dma1___width 1 -#define reg_intr_vect_rw_mask___dma1___bit 7 -#define reg_intr_vect_rw_mask___dma2___lsb 8 -#define reg_intr_vect_rw_mask___dma2___width 1 -#define reg_intr_vect_rw_mask___dma2___bit 8 -#define reg_intr_vect_rw_mask___dma3___lsb 9 -#define reg_intr_vect_rw_mask___dma3___width 1 -#define reg_intr_vect_rw_mask___dma3___bit 9 -#define reg_intr_vect_rw_mask___dma4___lsb 10 -#define reg_intr_vect_rw_mask___dma4___width 1 -#define reg_intr_vect_rw_mask___dma4___bit 10 -#define reg_intr_vect_rw_mask___dma5___lsb 11 -#define reg_intr_vect_rw_mask___dma5___width 1 -#define reg_intr_vect_rw_mask___dma5___bit 11 -#define reg_intr_vect_rw_mask___dma6___lsb 12 -#define reg_intr_vect_rw_mask___dma6___width 1 -#define reg_intr_vect_rw_mask___dma6___bit 12 -#define reg_intr_vect_rw_mask___dma7___lsb 13 -#define reg_intr_vect_rw_mask___dma7___width 1 -#define reg_intr_vect_rw_mask___dma7___bit 13 -#define reg_intr_vect_rw_mask___dma8___lsb 14 -#define reg_intr_vect_rw_mask___dma8___width 1 -#define reg_intr_vect_rw_mask___dma8___bit 14 -#define reg_intr_vect_rw_mask___dma9___lsb 15 -#define reg_intr_vect_rw_mask___dma9___width 1 -#define reg_intr_vect_rw_mask___dma9___bit 15 -#define reg_intr_vect_rw_mask___ata___lsb 16 -#define reg_intr_vect_rw_mask___ata___width 1 -#define reg_intr_vect_rw_mask___ata___bit 16 -#define reg_intr_vect_rw_mask___sser0___lsb 17 -#define reg_intr_vect_rw_mask___sser0___width 1 -#define reg_intr_vect_rw_mask___sser0___bit 17 -#define reg_intr_vect_rw_mask___sser1___lsb 18 -#define reg_intr_vect_rw_mask___sser1___width 1 -#define reg_intr_vect_rw_mask___sser1___bit 18 -#define reg_intr_vect_rw_mask___ser0___lsb 19 -#define reg_intr_vect_rw_mask___ser0___width 1 -#define reg_intr_vect_rw_mask___ser0___bit 19 -#define reg_intr_vect_rw_mask___ser1___lsb 20 -#define reg_intr_vect_rw_mask___ser1___width 1 -#define reg_intr_vect_rw_mask___ser1___bit 20 -#define reg_intr_vect_rw_mask___ser2___lsb 21 -#define reg_intr_vect_rw_mask___ser2___width 1 -#define reg_intr_vect_rw_mask___ser2___bit 21 -#define reg_intr_vect_rw_mask___ser3___lsb 22 -#define reg_intr_vect_rw_mask___ser3___width 1 -#define reg_intr_vect_rw_mask___ser3___bit 22 -#define reg_intr_vect_rw_mask___p21___lsb 23 -#define reg_intr_vect_rw_mask___p21___width 1 -#define reg_intr_vect_rw_mask___p21___bit 23 -#define reg_intr_vect_rw_mask___eth0___lsb 24 -#define reg_intr_vect_rw_mask___eth0___width 1 -#define reg_intr_vect_rw_mask___eth0___bit 24 -#define reg_intr_vect_rw_mask___eth1___lsb 25 -#define reg_intr_vect_rw_mask___eth1___width 1 -#define reg_intr_vect_rw_mask___eth1___bit 25 -#define reg_intr_vect_rw_mask___timer___lsb 26 -#define reg_intr_vect_rw_mask___timer___width 1 -#define reg_intr_vect_rw_mask___timer___bit 26 -#define reg_intr_vect_rw_mask___bif_arb___lsb 27 -#define reg_intr_vect_rw_mask___bif_arb___width 1 -#define reg_intr_vect_rw_mask___bif_arb___bit 27 -#define reg_intr_vect_rw_mask___bif_dma___lsb 28 -#define reg_intr_vect_rw_mask___bif_dma___width 1 -#define reg_intr_vect_rw_mask___bif_dma___bit 28 -#define reg_intr_vect_rw_mask___ext___lsb 29 -#define reg_intr_vect_rw_mask___ext___width 1 -#define reg_intr_vect_rw_mask___ext___bit 29 -#define reg_intr_vect_rw_mask_offset 0 - -/* Register r_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_vect___memarb___lsb 0 -#define reg_intr_vect_r_vect___memarb___width 1 -#define reg_intr_vect_r_vect___memarb___bit 0 -#define reg_intr_vect_r_vect___gen_io___lsb 1 -#define reg_intr_vect_r_vect___gen_io___width 1 -#define reg_intr_vect_r_vect___gen_io___bit 1 -#define reg_intr_vect_r_vect___iop0___lsb 2 -#define reg_intr_vect_r_vect___iop0___width 1 -#define reg_intr_vect_r_vect___iop0___bit 2 -#define reg_intr_vect_r_vect___iop1___lsb 3 -#define reg_intr_vect_r_vect___iop1___width 1 -#define reg_intr_vect_r_vect___iop1___bit 3 -#define reg_intr_vect_r_vect___iop2___lsb 4 -#define reg_intr_vect_r_vect___iop2___width 1 -#define reg_intr_vect_r_vect___iop2___bit 4 -#define reg_intr_vect_r_vect___iop3___lsb 5 -#define reg_intr_vect_r_vect___iop3___width 1 -#define reg_intr_vect_r_vect___iop3___bit 5 -#define reg_intr_vect_r_vect___dma0___lsb 6 -#define reg_intr_vect_r_vect___dma0___width 1 -#define reg_intr_vect_r_vect___dma0___bit 6 -#define reg_intr_vect_r_vect___dma1___lsb 7 -#define reg_intr_vect_r_vect___dma1___width 1 -#define reg_intr_vect_r_vect___dma1___bit 7 -#define reg_intr_vect_r_vect___dma2___lsb 8 -#define reg_intr_vect_r_vect___dma2___width 1 -#define reg_intr_vect_r_vect___dma2___bit 8 -#define reg_intr_vect_r_vect___dma3___lsb 9 -#define reg_intr_vect_r_vect___dma3___width 1 -#define reg_intr_vect_r_vect___dma3___bit 9 -#define reg_intr_vect_r_vect___dma4___lsb 10 -#define reg_intr_vect_r_vect___dma4___width 1 -#define reg_intr_vect_r_vect___dma4___bit 10 -#define reg_intr_vect_r_vect___dma5___lsb 11 -#define reg_intr_vect_r_vect___dma5___width 1 -#define reg_intr_vect_r_vect___dma5___bit 11 -#define reg_intr_vect_r_vect___dma6___lsb 12 -#define reg_intr_vect_r_vect___dma6___width 1 -#define reg_intr_vect_r_vect___dma6___bit 12 -#define reg_intr_vect_r_vect___dma7___lsb 13 -#define reg_intr_vect_r_vect___dma7___width 1 -#define reg_intr_vect_r_vect___dma7___bit 13 -#define reg_intr_vect_r_vect___dma8___lsb 14 -#define reg_intr_vect_r_vect___dma8___width 1 -#define reg_intr_vect_r_vect___dma8___bit 14 -#define reg_intr_vect_r_vect___dma9___lsb 15 -#define reg_intr_vect_r_vect___dma9___width 1 -#define reg_intr_vect_r_vect___dma9___bit 15 -#define reg_intr_vect_r_vect___ata___lsb 16 -#define reg_intr_vect_r_vect___ata___width 1 -#define reg_intr_vect_r_vect___ata___bit 16 -#define reg_intr_vect_r_vect___sser0___lsb 17 -#define reg_intr_vect_r_vect___sser0___width 1 -#define reg_intr_vect_r_vect___sser0___bit 17 -#define reg_intr_vect_r_vect___sser1___lsb 18 -#define reg_intr_vect_r_vect___sser1___width 1 -#define reg_intr_vect_r_vect___sser1___bit 18 -#define reg_intr_vect_r_vect___ser0___lsb 19 -#define reg_intr_vect_r_vect___ser0___width 1 -#define reg_intr_vect_r_vect___ser0___bit 19 -#define reg_intr_vect_r_vect___ser1___lsb 20 -#define reg_intr_vect_r_vect___ser1___width 1 -#define reg_intr_vect_r_vect___ser1___bit 20 -#define reg_intr_vect_r_vect___ser2___lsb 21 -#define reg_intr_vect_r_vect___ser2___width 1 -#define reg_intr_vect_r_vect___ser2___bit 21 -#define reg_intr_vect_r_vect___ser3___lsb 22 -#define reg_intr_vect_r_vect___ser3___width 1 -#define reg_intr_vect_r_vect___ser3___bit 22 -#define reg_intr_vect_r_vect___p21___lsb 23 -#define reg_intr_vect_r_vect___p21___width 1 -#define reg_intr_vect_r_vect___p21___bit 23 -#define reg_intr_vect_r_vect___eth0___lsb 24 -#define reg_intr_vect_r_vect___eth0___width 1 -#define reg_intr_vect_r_vect___eth0___bit 24 -#define reg_intr_vect_r_vect___eth1___lsb 25 -#define reg_intr_vect_r_vect___eth1___width 1 -#define reg_intr_vect_r_vect___eth1___bit 25 -#define reg_intr_vect_r_vect___timer___lsb 26 -#define reg_intr_vect_r_vect___timer___width 1 -#define reg_intr_vect_r_vect___timer___bit 26 -#define reg_intr_vect_r_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_vect___bif_arb___width 1 -#define reg_intr_vect_r_vect___bif_arb___bit 27 -#define reg_intr_vect_r_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_vect___bif_dma___width 1 -#define reg_intr_vect_r_vect___bif_dma___bit 28 -#define reg_intr_vect_r_vect___ext___lsb 29 -#define reg_intr_vect_r_vect___ext___width 1 -#define reg_intr_vect_r_vect___ext___bit 29 -#define reg_intr_vect_r_vect_offset 4 - -/* Register r_masked_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_masked_vect___memarb___lsb 0 -#define reg_intr_vect_r_masked_vect___memarb___width 1 -#define reg_intr_vect_r_masked_vect___memarb___bit 0 -#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 -#define reg_intr_vect_r_masked_vect___gen_io___width 1 -#define reg_intr_vect_r_masked_vect___gen_io___bit 1 -#define reg_intr_vect_r_masked_vect___iop0___lsb 2 -#define reg_intr_vect_r_masked_vect___iop0___width 1 -#define reg_intr_vect_r_masked_vect___iop0___bit 2 -#define reg_intr_vect_r_masked_vect___iop1___lsb 3 -#define reg_intr_vect_r_masked_vect___iop1___width 1 -#define reg_intr_vect_r_masked_vect___iop1___bit 3 -#define reg_intr_vect_r_masked_vect___iop2___lsb 4 -#define reg_intr_vect_r_masked_vect___iop2___width 1 -#define reg_intr_vect_r_masked_vect___iop2___bit 4 -#define reg_intr_vect_r_masked_vect___iop3___lsb 5 -#define reg_intr_vect_r_masked_vect___iop3___width 1 -#define reg_intr_vect_r_masked_vect___iop3___bit 5 -#define reg_intr_vect_r_masked_vect___dma0___lsb 6 -#define reg_intr_vect_r_masked_vect___dma0___width 1 -#define reg_intr_vect_r_masked_vect___dma0___bit 6 -#define reg_intr_vect_r_masked_vect___dma1___lsb 7 -#define reg_intr_vect_r_masked_vect___dma1___width 1 -#define reg_intr_vect_r_masked_vect___dma1___bit 7 -#define reg_intr_vect_r_masked_vect___dma2___lsb 8 -#define reg_intr_vect_r_masked_vect___dma2___width 1 -#define reg_intr_vect_r_masked_vect___dma2___bit 8 -#define reg_intr_vect_r_masked_vect___dma3___lsb 9 -#define reg_intr_vect_r_masked_vect___dma3___width 1 -#define reg_intr_vect_r_masked_vect___dma3___bit 9 -#define reg_intr_vect_r_masked_vect___dma4___lsb 10 -#define reg_intr_vect_r_masked_vect___dma4___width 1 -#define reg_intr_vect_r_masked_vect___dma4___bit 10 -#define reg_intr_vect_r_masked_vect___dma5___lsb 11 -#define reg_intr_vect_r_masked_vect___dma5___width 1 -#define reg_intr_vect_r_masked_vect___dma5___bit 11 -#define reg_intr_vect_r_masked_vect___dma6___lsb 12 -#define reg_intr_vect_r_masked_vect___dma6___width 1 -#define reg_intr_vect_r_masked_vect___dma6___bit 12 -#define reg_intr_vect_r_masked_vect___dma7___lsb 13 -#define reg_intr_vect_r_masked_vect___dma7___width 1 -#define reg_intr_vect_r_masked_vect___dma7___bit 13 -#define reg_intr_vect_r_masked_vect___dma8___lsb 14 -#define reg_intr_vect_r_masked_vect___dma8___width 1 -#define reg_intr_vect_r_masked_vect___dma8___bit 14 -#define reg_intr_vect_r_masked_vect___dma9___lsb 15 -#define reg_intr_vect_r_masked_vect___dma9___width 1 -#define reg_intr_vect_r_masked_vect___dma9___bit 15 -#define reg_intr_vect_r_masked_vect___ata___lsb 16 -#define reg_intr_vect_r_masked_vect___ata___width 1 -#define reg_intr_vect_r_masked_vect___ata___bit 16 -#define reg_intr_vect_r_masked_vect___sser0___lsb 17 -#define reg_intr_vect_r_masked_vect___sser0___width 1 -#define reg_intr_vect_r_masked_vect___sser0___bit 17 -#define reg_intr_vect_r_masked_vect___sser1___lsb 18 -#define reg_intr_vect_r_masked_vect___sser1___width 1 -#define reg_intr_vect_r_masked_vect___sser1___bit 18 -#define reg_intr_vect_r_masked_vect___ser0___lsb 19 -#define reg_intr_vect_r_masked_vect___ser0___width 1 -#define reg_intr_vect_r_masked_vect___ser0___bit 19 -#define reg_intr_vect_r_masked_vect___ser1___lsb 20 -#define reg_intr_vect_r_masked_vect___ser1___width 1 -#define reg_intr_vect_r_masked_vect___ser1___bit 20 -#define reg_intr_vect_r_masked_vect___ser2___lsb 21 -#define reg_intr_vect_r_masked_vect___ser2___width 1 -#define reg_intr_vect_r_masked_vect___ser2___bit 21 -#define reg_intr_vect_r_masked_vect___ser3___lsb 22 -#define reg_intr_vect_r_masked_vect___ser3___width 1 -#define reg_intr_vect_r_masked_vect___ser3___bit 22 -#define reg_intr_vect_r_masked_vect___p21___lsb 23 -#define reg_intr_vect_r_masked_vect___p21___width 1 -#define reg_intr_vect_r_masked_vect___p21___bit 23 -#define reg_intr_vect_r_masked_vect___eth0___lsb 24 -#define reg_intr_vect_r_masked_vect___eth0___width 1 -#define reg_intr_vect_r_masked_vect___eth0___bit 24 -#define reg_intr_vect_r_masked_vect___eth1___lsb 25 -#define reg_intr_vect_r_masked_vect___eth1___width 1 -#define reg_intr_vect_r_masked_vect___eth1___bit 25 -#define reg_intr_vect_r_masked_vect___timer___lsb 26 -#define reg_intr_vect_r_masked_vect___timer___width 1 -#define reg_intr_vect_r_masked_vect___timer___bit 26 -#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_masked_vect___bif_arb___width 1 -#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 -#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_masked_vect___bif_dma___width 1 -#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 -#define reg_intr_vect_r_masked_vect___ext___lsb 29 -#define reg_intr_vect_r_masked_vect___ext___width 1 -#define reg_intr_vect_r_masked_vect___ext___bit 29 -#define reg_intr_vect_r_masked_vect_offset 8 - -/* Register r_nmi, scope intr_vect, type r */ -#define reg_intr_vect_r_nmi___ext___lsb 0 -#define reg_intr_vect_r_nmi___ext___width 1 -#define reg_intr_vect_r_nmi___ext___bit 0 -#define reg_intr_vect_r_nmi___watchdog___lsb 1 -#define reg_intr_vect_r_nmi___watchdog___width 1 -#define reg_intr_vect_r_nmi___watchdog___bit 1 -#define reg_intr_vect_r_nmi_offset 12 - -/* Register r_guru, scope intr_vect, type r */ -#define reg_intr_vect_r_guru___jtag___lsb 0 -#define reg_intr_vect_r_guru___jtag___width 1 -#define reg_intr_vect_r_guru___jtag___bit 0 -#define reg_intr_vect_r_guru_offset 16 - - -/* Constants */ -#define regk_intr_vect_off 0x00000000 -#define regk_intr_vect_on 0x00000001 -#define regk_intr_vect_rw_mask_default 0x00000000 -#endif /* __intr_vect_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h deleted file mode 100644 index 0c8084054840..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef __irq_nmi_defs_asm_h -#define __irq_nmi_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: <not found> - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cmd, scope irq_nmi, type rw */ -#define reg_irq_nmi_rw_cmd___delay___lsb 0 -#define reg_irq_nmi_rw_cmd___delay___width 16 -#define reg_irq_nmi_rw_cmd___op___lsb 16 -#define reg_irq_nmi_rw_cmd___op___width 2 -#define reg_irq_nmi_rw_cmd_offset 0 - - -/* Constants */ -#define regk_irq_nmi_ack_irq 0x00000002 -#define regk_irq_nmi_ack_nmi 0x00000003 -#define regk_irq_nmi_irq 0x00000000 -#define regk_irq_nmi_nmi 0x00000001 -#endif /* __irq_nmi_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h deleted file mode 100644 index 45400eb8d389..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h +++ /dev/null @@ -1,579 +0,0 @@ -#ifndef __marb_defs_asm_h -#define __marb_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -#define reg_marb_rw_int_slots___owner___lsb 0 -#define reg_marb_rw_int_slots___owner___width 4 -#define reg_marb_rw_int_slots_offset 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -#define reg_marb_rw_ext_slots___owner___lsb 0 -#define reg_marb_rw_ext_slots___owner___width 4 -#define reg_marb_rw_ext_slots_offset 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -#define reg_marb_rw_regs_slots___owner___lsb 0 -#define reg_marb_rw_regs_slots___owner___width 4 -#define reg_marb_rw_regs_slots_offset 512 - -/* Register rw_intr_mask, scope marb, type rw */ -#define reg_marb_rw_intr_mask___bp0___lsb 0 -#define reg_marb_rw_intr_mask___bp0___width 1 -#define reg_marb_rw_intr_mask___bp0___bit 0 -#define reg_marb_rw_intr_mask___bp1___lsb 1 -#define reg_marb_rw_intr_mask___bp1___width 1 -#define reg_marb_rw_intr_mask___bp1___bit 1 -#define reg_marb_rw_intr_mask___bp2___lsb 2 -#define reg_marb_rw_intr_mask___bp2___width 1 -#define reg_marb_rw_intr_mask___bp2___bit 2 -#define reg_marb_rw_intr_mask___bp3___lsb 3 -#define reg_marb_rw_intr_mask___bp3___width 1 -#define reg_marb_rw_intr_mask___bp3___bit 3 -#define reg_marb_rw_intr_mask_offset 528 - -/* Register rw_ack_intr, scope marb, type rw */ -#define reg_marb_rw_ack_intr___bp0___lsb 0 -#define reg_marb_rw_ack_intr___bp0___width 1 -#define reg_marb_rw_ack_intr___bp0___bit 0 -#define reg_marb_rw_ack_intr___bp1___lsb 1 -#define reg_marb_rw_ack_intr___bp1___width 1 -#define reg_marb_rw_ack_intr___bp1___bit 1 -#define reg_marb_rw_ack_intr___bp2___lsb 2 -#define reg_marb_rw_ack_intr___bp2___width 1 -#define reg_marb_rw_ack_intr___bp2___bit 2 -#define reg_marb_rw_ack_intr___bp3___lsb 3 -#define reg_marb_rw_ack_intr___bp3___width 1 -#define reg_marb_rw_ack_intr___bp3___bit 3 -#define reg_marb_rw_ack_intr_offset 532 - -/* Register r_intr, scope marb, type r */ -#define reg_marb_r_intr___bp0___lsb 0 -#define reg_marb_r_intr___bp0___width 1 -#define reg_marb_r_intr___bp0___bit 0 -#define reg_marb_r_intr___bp1___lsb 1 -#define reg_marb_r_intr___bp1___width 1 -#define reg_marb_r_intr___bp1___bit 1 -#define reg_marb_r_intr___bp2___lsb 2 -#define reg_marb_r_intr___bp2___width 1 -#define reg_marb_r_intr___bp2___bit 2 -#define reg_marb_r_intr___bp3___lsb 3 -#define reg_marb_r_intr___bp3___width 1 -#define reg_marb_r_intr___bp3___bit 3 -#define reg_marb_r_intr_offset 536 - -/* Register r_masked_intr, scope marb, type r */ -#define reg_marb_r_masked_intr___bp0___lsb 0 -#define reg_marb_r_masked_intr___bp0___width 1 -#define reg_marb_r_masked_intr___bp0___bit 0 -#define reg_marb_r_masked_intr___bp1___lsb 1 -#define reg_marb_r_masked_intr___bp1___width 1 -#define reg_marb_r_masked_intr___bp1___bit 1 -#define reg_marb_r_masked_intr___bp2___lsb 2 -#define reg_marb_r_masked_intr___bp2___width 1 -#define reg_marb_r_masked_intr___bp2___bit 2 -#define reg_marb_r_masked_intr___bp3___lsb 3 -#define reg_marb_r_masked_intr___bp3___width 1 -#define reg_marb_r_masked_intr___bp3___bit 3 -#define reg_marb_r_masked_intr_offset 540 - -/* Register rw_stop_mask, scope marb, type rw */ -#define reg_marb_rw_stop_mask___dma0___lsb 0 -#define reg_marb_rw_stop_mask___dma0___width 1 -#define reg_marb_rw_stop_mask___dma0___bit 0 -#define reg_marb_rw_stop_mask___dma1___lsb 1 -#define reg_marb_rw_stop_mask___dma1___width 1 -#define reg_marb_rw_stop_mask___dma1___bit 1 -#define reg_marb_rw_stop_mask___dma2___lsb 2 -#define reg_marb_rw_stop_mask___dma2___width 1 -#define reg_marb_rw_stop_mask___dma2___bit 2 -#define reg_marb_rw_stop_mask___dma3___lsb 3 -#define reg_marb_rw_stop_mask___dma3___width 1 -#define reg_marb_rw_stop_mask___dma3___bit 3 -#define reg_marb_rw_stop_mask___dma4___lsb 4 -#define reg_marb_rw_stop_mask___dma4___width 1 -#define reg_marb_rw_stop_mask___dma4___bit 4 -#define reg_marb_rw_stop_mask___dma5___lsb 5 -#define reg_marb_rw_stop_mask___dma5___width 1 -#define reg_marb_rw_stop_mask___dma5___bit 5 -#define reg_marb_rw_stop_mask___dma6___lsb 6 -#define reg_marb_rw_stop_mask___dma6___width 1 -#define reg_marb_rw_stop_mask___dma6___bit 6 -#define reg_marb_rw_stop_mask___dma7___lsb 7 -#define reg_marb_rw_stop_mask___dma7___width 1 -#define reg_marb_rw_stop_mask___dma7___bit 7 -#define reg_marb_rw_stop_mask___dma8___lsb 8 -#define reg_marb_rw_stop_mask___dma8___width 1 -#define reg_marb_rw_stop_mask___dma8___bit 8 -#define reg_marb_rw_stop_mask___dma9___lsb 9 -#define reg_marb_rw_stop_mask___dma9___width 1 -#define reg_marb_rw_stop_mask___dma9___bit 9 -#define reg_marb_rw_stop_mask___cpui___lsb 10 -#define reg_marb_rw_stop_mask___cpui___width 1 -#define reg_marb_rw_stop_mask___cpui___bit 10 -#define reg_marb_rw_stop_mask___cpud___lsb 11 -#define reg_marb_rw_stop_mask___cpud___width 1 -#define reg_marb_rw_stop_mask___cpud___bit 11 -#define reg_marb_rw_stop_mask___iop___lsb 12 -#define reg_marb_rw_stop_mask___iop___width 1 -#define reg_marb_rw_stop_mask___iop___bit 12 -#define reg_marb_rw_stop_mask___slave___lsb 13 -#define reg_marb_rw_stop_mask___slave___width 1 -#define reg_marb_rw_stop_mask___slave___bit 13 -#define reg_marb_rw_stop_mask_offset 544 - -/* Register r_stopped, scope marb, type r */ -#define reg_marb_r_stopped___dma0___lsb 0 -#define reg_marb_r_stopped___dma0___width 1 -#define reg_marb_r_stopped___dma0___bit 0 -#define reg_marb_r_stopped___dma1___lsb 1 -#define reg_marb_r_stopped___dma1___width 1 -#define reg_marb_r_stopped___dma1___bit 1 -#define reg_marb_r_stopped___dma2___lsb 2 -#define reg_marb_r_stopped___dma2___width 1 -#define reg_marb_r_stopped___dma2___bit 2 -#define reg_marb_r_stopped___dma3___lsb 3 -#define reg_marb_r_stopped___dma3___width 1 -#define reg_marb_r_stopped___dma3___bit 3 -#define reg_marb_r_stopped___dma4___lsb 4 -#define reg_marb_r_stopped___dma4___width 1 -#define reg_marb_r_stopped___dma4___bit 4 -#define reg_marb_r_stopped___dma5___lsb 5 -#define reg_marb_r_stopped___dma5___width 1 -#define reg_marb_r_stopped___dma5___bit 5 -#define reg_marb_r_stopped___dma6___lsb 6 -#define reg_marb_r_stopped___dma6___width 1 -#define reg_marb_r_stopped___dma6___bit 6 -#define reg_marb_r_stopped___dma7___lsb 7 -#define reg_marb_r_stopped___dma7___width 1 -#define reg_marb_r_stopped___dma7___bit 7 -#define reg_marb_r_stopped___dma8___lsb 8 -#define reg_marb_r_stopped___dma8___width 1 -#define reg_marb_r_stopped___dma8___bit 8 -#define reg_marb_r_stopped___dma9___lsb 9 -#define reg_marb_r_stopped___dma9___width 1 -#define reg_marb_r_stopped___dma9___bit 9 -#define reg_marb_r_stopped___cpui___lsb 10 -#define reg_marb_r_stopped___cpui___width 1 -#define reg_marb_r_stopped___cpui___bit 10 -#define reg_marb_r_stopped___cpud___lsb 11 -#define reg_marb_r_stopped___cpud___width 1 -#define reg_marb_r_stopped___cpud___bit 11 -#define reg_marb_r_stopped___iop___lsb 12 -#define reg_marb_r_stopped___iop___width 1 -#define reg_marb_r_stopped___iop___bit 12 -#define reg_marb_r_stopped___slave___lsb 13 -#define reg_marb_r_stopped___slave___width 1 -#define reg_marb_r_stopped___slave___bit 13 -#define reg_marb_r_stopped_offset 548 - -/* Register rw_no_snoop, scope marb, type rw */ -#define reg_marb_rw_no_snoop___dma0___lsb 0 -#define reg_marb_rw_no_snoop___dma0___width 1 -#define reg_marb_rw_no_snoop___dma0___bit 0 -#define reg_marb_rw_no_snoop___dma1___lsb 1 -#define reg_marb_rw_no_snoop___dma1___width 1 -#define reg_marb_rw_no_snoop___dma1___bit 1 -#define reg_marb_rw_no_snoop___dma2___lsb 2 -#define reg_marb_rw_no_snoop___dma2___width 1 -#define reg_marb_rw_no_snoop___dma2___bit 2 -#define reg_marb_rw_no_snoop___dma3___lsb 3 -#define reg_marb_rw_no_snoop___dma3___width 1 -#define reg_marb_rw_no_snoop___dma3___bit 3 -#define reg_marb_rw_no_snoop___dma4___lsb 4 -#define reg_marb_rw_no_snoop___dma4___width 1 -#define reg_marb_rw_no_snoop___dma4___bit 4 -#define reg_marb_rw_no_snoop___dma5___lsb 5 -#define reg_marb_rw_no_snoop___dma5___width 1 -#define reg_marb_rw_no_snoop___dma5___bit 5 -#define reg_marb_rw_no_snoop___dma6___lsb 6 -#define reg_marb_rw_no_snoop___dma6___width 1 -#define reg_marb_rw_no_snoop___dma6___bit 6 -#define reg_marb_rw_no_snoop___dma7___lsb 7 -#define reg_marb_rw_no_snoop___dma7___width 1 -#define reg_marb_rw_no_snoop___dma7___bit 7 -#define reg_marb_rw_no_snoop___dma8___lsb 8 -#define reg_marb_rw_no_snoop___dma8___width 1 -#define reg_marb_rw_no_snoop___dma8___bit 8 -#define reg_marb_rw_no_snoop___dma9___lsb 9 -#define reg_marb_rw_no_snoop___dma9___width 1 -#define reg_marb_rw_no_snoop___dma9___bit 9 -#define reg_marb_rw_no_snoop___cpui___lsb 10 -#define reg_marb_rw_no_snoop___cpui___width 1 -#define reg_marb_rw_no_snoop___cpui___bit 10 -#define reg_marb_rw_no_snoop___cpud___lsb 11 -#define reg_marb_rw_no_snoop___cpud___width 1 -#define reg_marb_rw_no_snoop___cpud___bit 11 -#define reg_marb_rw_no_snoop___iop___lsb 12 -#define reg_marb_rw_no_snoop___iop___width 1 -#define reg_marb_rw_no_snoop___iop___bit 12 -#define reg_marb_rw_no_snoop___slave___lsb 13 -#define reg_marb_rw_no_snoop___slave___width 1 -#define reg_marb_rw_no_snoop___slave___bit 13 -#define reg_marb_rw_no_snoop_offset 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 -#define reg_marb_rw_no_snoop_rq___cpui___width 1 -#define reg_marb_rw_no_snoop_rq___cpui___bit 10 -#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 -#define reg_marb_rw_no_snoop_rq___cpud___width 1 -#define reg_marb_rw_no_snoop_rq___cpud___bit 11 -#define reg_marb_rw_no_snoop_rq_offset 836 - - -/* Constants */ -#define regk_marb_cpud 0x0000000b -#define regk_marb_cpui 0x0000000a -#define regk_marb_dma0 0x00000000 -#define regk_marb_dma1 0x00000001 -#define regk_marb_dma2 0x00000002 -#define regk_marb_dma3 0x00000003 -#define regk_marb_dma4 0x00000004 -#define regk_marb_dma5 0x00000005 -#define regk_marb_dma6 0x00000006 -#define regk_marb_dma7 0x00000007 -#define regk_marb_dma8 0x00000008 -#define regk_marb_dma9 0x00000009 -#define regk_marb_iop 0x0000000c -#define regk_marb_no 0x00000000 -#define regk_marb_r_stopped_default 0x00000000 -#define regk_marb_rw_ext_slots_default 0x00000000 -#define regk_marb_rw_ext_slots_size 0x00000040 -#define regk_marb_rw_int_slots_default 0x00000000 -#define regk_marb_rw_int_slots_size 0x00000040 -#define regk_marb_rw_intr_mask_default 0x00000000 -#define regk_marb_rw_no_snoop_default 0x00000000 -#define regk_marb_rw_no_snoop_rq_default 0x00000000 -#define regk_marb_rw_regs_slots_default 0x00000000 -#define regk_marb_rw_regs_slots_size 0x00000004 -#define regk_marb_rw_stop_mask_default 0x00000000 -#define regk_marb_slave 0x0000000d -#define regk_marb_yes 0x00000001 -#endif /* __marb_defs_asm_h */ -#ifndef __marb_bp_defs_asm_h -#define __marb_bp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_first_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_first_addr_offset 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_last_addr_offset 4 - -/* Register rw_op, scope marb_bp, type rw */ -#define reg_marb_bp_rw_op___rd___lsb 0 -#define reg_marb_bp_rw_op___rd___width 1 -#define reg_marb_bp_rw_op___rd___bit 0 -#define reg_marb_bp_rw_op___wr___lsb 1 -#define reg_marb_bp_rw_op___wr___width 1 -#define reg_marb_bp_rw_op___wr___bit 1 -#define reg_marb_bp_rw_op___rd_excl___lsb 2 -#define reg_marb_bp_rw_op___rd_excl___width 1 -#define reg_marb_bp_rw_op___rd_excl___bit 2 -#define reg_marb_bp_rw_op___pri_wr___lsb 3 -#define reg_marb_bp_rw_op___pri_wr___width 1 -#define reg_marb_bp_rw_op___pri_wr___bit 3 -#define reg_marb_bp_rw_op___us_rd___lsb 4 -#define reg_marb_bp_rw_op___us_rd___width 1 -#define reg_marb_bp_rw_op___us_rd___bit 4 -#define reg_marb_bp_rw_op___us_wr___lsb 5 -#define reg_marb_bp_rw_op___us_wr___width 1 -#define reg_marb_bp_rw_op___us_wr___bit 5 -#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 -#define reg_marb_bp_rw_op___us_rd_excl___width 1 -#define reg_marb_bp_rw_op___us_rd_excl___bit 6 -#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 -#define reg_marb_bp_rw_op___us_pri_wr___width 1 -#define reg_marb_bp_rw_op___us_pri_wr___bit 7 -#define reg_marb_bp_rw_op_offset 8 - -/* Register rw_clients, scope marb_bp, type rw */ -#define reg_marb_bp_rw_clients___dma0___lsb 0 -#define reg_marb_bp_rw_clients___dma0___width 1 -#define reg_marb_bp_rw_clients___dma0___bit 0 -#define reg_marb_bp_rw_clients___dma1___lsb 1 -#define reg_marb_bp_rw_clients___dma1___width 1 -#define reg_marb_bp_rw_clients___dma1___bit 1 -#define reg_marb_bp_rw_clients___dma2___lsb 2 -#define reg_marb_bp_rw_clients___dma2___width 1 -#define reg_marb_bp_rw_clients___dma2___bit 2 -#define reg_marb_bp_rw_clients___dma3___lsb 3 -#define reg_marb_bp_rw_clients___dma3___width 1 -#define reg_marb_bp_rw_clients___dma3___bit 3 -#define reg_marb_bp_rw_clients___dma4___lsb 4 -#define reg_marb_bp_rw_clients___dma4___width 1 -#define reg_marb_bp_rw_clients___dma4___bit 4 -#define reg_marb_bp_rw_clients___dma5___lsb 5 -#define reg_marb_bp_rw_clients___dma5___width 1 -#define reg_marb_bp_rw_clients___dma5___bit 5 -#define reg_marb_bp_rw_clients___dma6___lsb 6 -#define reg_marb_bp_rw_clients___dma6___width 1 -#define reg_marb_bp_rw_clients___dma6___bit 6 -#define reg_marb_bp_rw_clients___dma7___lsb 7 -#define reg_marb_bp_rw_clients___dma7___width 1 -#define reg_marb_bp_rw_clients___dma7___bit 7 -#define reg_marb_bp_rw_clients___dma8___lsb 8 -#define reg_marb_bp_rw_clients___dma8___width 1 -#define reg_marb_bp_rw_clients___dma8___bit 8 -#define reg_marb_bp_rw_clients___dma9___lsb 9 -#define reg_marb_bp_rw_clients___dma9___width 1 -#define reg_marb_bp_rw_clients___dma9___bit 9 -#define reg_marb_bp_rw_clients___cpui___lsb 10 -#define reg_marb_bp_rw_clients___cpui___width 1 -#define reg_marb_bp_rw_clients___cpui___bit 10 -#define reg_marb_bp_rw_clients___cpud___lsb 11 -#define reg_marb_bp_rw_clients___cpud___width 1 -#define reg_marb_bp_rw_clients___cpud___bit 11 -#define reg_marb_bp_rw_clients___iop___lsb 12 -#define reg_marb_bp_rw_clients___iop___width 1 -#define reg_marb_bp_rw_clients___iop___bit 12 -#define reg_marb_bp_rw_clients___slave___lsb 13 -#define reg_marb_bp_rw_clients___slave___width 1 -#define reg_marb_bp_rw_clients___slave___bit 13 -#define reg_marb_bp_rw_clients_offset 12 - -/* Register rw_options, scope marb_bp, type rw */ -#define reg_marb_bp_rw_options___wrap___lsb 0 -#define reg_marb_bp_rw_options___wrap___width 1 -#define reg_marb_bp_rw_options___wrap___bit 0 -#define reg_marb_bp_rw_options_offset 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_addr_offset 20 - -/* Register r_brk_op, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_op___rd___lsb 0 -#define reg_marb_bp_r_brk_op___rd___width 1 -#define reg_marb_bp_r_brk_op___rd___bit 0 -#define reg_marb_bp_r_brk_op___wr___lsb 1 -#define reg_marb_bp_r_brk_op___wr___width 1 -#define reg_marb_bp_r_brk_op___wr___bit 1 -#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 -#define reg_marb_bp_r_brk_op___rd_excl___width 1 -#define reg_marb_bp_r_brk_op___rd_excl___bit 2 -#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 -#define reg_marb_bp_r_brk_op___pri_wr___width 1 -#define reg_marb_bp_r_brk_op___pri_wr___bit 3 -#define reg_marb_bp_r_brk_op___us_rd___lsb 4 -#define reg_marb_bp_r_brk_op___us_rd___width 1 -#define reg_marb_bp_r_brk_op___us_rd___bit 4 -#define reg_marb_bp_r_brk_op___us_wr___lsb 5 -#define reg_marb_bp_r_brk_op___us_wr___width 1 -#define reg_marb_bp_r_brk_op___us_wr___bit 5 -#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 -#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 -#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 -#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 -#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 -#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 -#define reg_marb_bp_r_brk_op_offset 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_clients___dma0___lsb 0 -#define reg_marb_bp_r_brk_clients___dma0___width 1 -#define reg_marb_bp_r_brk_clients___dma0___bit 0 -#define reg_marb_bp_r_brk_clients___dma1___lsb 1 -#define reg_marb_bp_r_brk_clients___dma1___width 1 -#define reg_marb_bp_r_brk_clients___dma1___bit 1 -#define reg_marb_bp_r_brk_clients___dma2___lsb 2 -#define reg_marb_bp_r_brk_clients___dma2___width 1 -#define reg_marb_bp_r_brk_clients___dma2___bit 2 -#define reg_marb_bp_r_brk_clients___dma3___lsb 3 -#define reg_marb_bp_r_brk_clients___dma3___width 1 -#define reg_marb_bp_r_brk_clients___dma3___bit 3 -#define reg_marb_bp_r_brk_clients___dma4___lsb 4 -#define reg_marb_bp_r_brk_clients___dma4___width 1 -#define reg_marb_bp_r_brk_clients___dma4___bit 4 -#define reg_marb_bp_r_brk_clients___dma5___lsb 5 -#define reg_marb_bp_r_brk_clients___dma5___width 1 -#define reg_marb_bp_r_brk_clients___dma5___bit 5 -#define reg_marb_bp_r_brk_clients___dma6___lsb 6 -#define reg_marb_bp_r_brk_clients___dma6___width 1 -#define reg_marb_bp_r_brk_clients___dma6___bit 6 -#define reg_marb_bp_r_brk_clients___dma7___lsb 7 -#define reg_marb_bp_r_brk_clients___dma7___width 1 -#define reg_marb_bp_r_brk_clients___dma7___bit 7 -#define reg_marb_bp_r_brk_clients___dma8___lsb 8 -#define reg_marb_bp_r_brk_clients___dma8___width 1 -#define reg_marb_bp_r_brk_clients___dma8___bit 8 -#define reg_marb_bp_r_brk_clients___dma9___lsb 9 -#define reg_marb_bp_r_brk_clients___dma9___width 1 -#define reg_marb_bp_r_brk_clients___dma9___bit 9 -#define reg_marb_bp_r_brk_clients___cpui___lsb 10 -#define reg_marb_bp_r_brk_clients___cpui___width 1 -#define reg_marb_bp_r_brk_clients___cpui___bit 10 -#define reg_marb_bp_r_brk_clients___cpud___lsb 11 -#define reg_marb_bp_r_brk_clients___cpud___width 1 -#define reg_marb_bp_r_brk_clients___cpud___bit 11 -#define reg_marb_bp_r_brk_clients___iop___lsb 12 -#define reg_marb_bp_r_brk_clients___iop___width 1 -#define reg_marb_bp_r_brk_clients___iop___bit 12 -#define reg_marb_bp_r_brk_clients___slave___lsb 13 -#define reg_marb_bp_r_brk_clients___slave___width 1 -#define reg_marb_bp_r_brk_clients___slave___bit 13 -#define reg_marb_bp_r_brk_clients_offset 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 -#define reg_marb_bp_r_brk_first_client___dma0___width 1 -#define reg_marb_bp_r_brk_first_client___dma0___bit 0 -#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 -#define reg_marb_bp_r_brk_first_client___dma1___width 1 -#define reg_marb_bp_r_brk_first_client___dma1___bit 1 -#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 -#define reg_marb_bp_r_brk_first_client___dma2___width 1 -#define reg_marb_bp_r_brk_first_client___dma2___bit 2 -#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 -#define reg_marb_bp_r_brk_first_client___dma3___width 1 -#define reg_marb_bp_r_brk_first_client___dma3___bit 3 -#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 -#define reg_marb_bp_r_brk_first_client___dma4___width 1 -#define reg_marb_bp_r_brk_first_client___dma4___bit 4 -#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 -#define reg_marb_bp_r_brk_first_client___dma5___width 1 -#define reg_marb_bp_r_brk_first_client___dma5___bit 5 -#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 -#define reg_marb_bp_r_brk_first_client___dma6___width 1 -#define reg_marb_bp_r_brk_first_client___dma6___bit 6 -#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 -#define reg_marb_bp_r_brk_first_client___dma7___width 1 -#define reg_marb_bp_r_brk_first_client___dma7___bit 7 -#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 -#define reg_marb_bp_r_brk_first_client___dma8___width 1 -#define reg_marb_bp_r_brk_first_client___dma8___bit 8 -#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 -#define reg_marb_bp_r_brk_first_client___dma9___width 1 -#define reg_marb_bp_r_brk_first_client___dma9___bit 9 -#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 -#define reg_marb_bp_r_brk_first_client___cpui___width 1 -#define reg_marb_bp_r_brk_first_client___cpui___bit 10 -#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 -#define reg_marb_bp_r_brk_first_client___cpud___width 1 -#define reg_marb_bp_r_brk_first_client___cpud___bit 11 -#define reg_marb_bp_r_brk_first_client___iop___lsb 12 -#define reg_marb_bp_r_brk_first_client___iop___width 1 -#define reg_marb_bp_r_brk_first_client___iop___bit 12 -#define reg_marb_bp_r_brk_first_client___slave___lsb 13 -#define reg_marb_bp_r_brk_first_client___slave___width 1 -#define reg_marb_bp_r_brk_first_client___slave___bit 13 -#define reg_marb_bp_r_brk_first_client_offset 32 - -/* Register r_brk_size, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_size_offset 36 - -/* Register rw_ack, scope marb_bp, type rw */ -#define reg_marb_bp_rw_ack_offset 40 - - -/* Constants */ -#define regk_marb_bp_no 0x00000000 -#define regk_marb_bp_rw_op_default 0x00000000 -#define regk_marb_bp_rw_options_default 0x00000000 -#define regk_marb_bp_yes 0x00000001 -#endif /* __marb_bp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h deleted file mode 100644 index 505b7a16d878..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h +++ /dev/null @@ -1,212 +0,0 @@ -#ifndef __mmu_defs_asm_h -#define __mmu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/mmu/doc/mmu_regs.r - * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp - * last modfied: Mon Apr 11 17:03:20 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r - * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mm_cfg, scope mmu, type rw */ -#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 -#define reg_mmu_rw_mm_cfg___seg_0___width 1 -#define reg_mmu_rw_mm_cfg___seg_0___bit 0 -#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 -#define reg_mmu_rw_mm_cfg___seg_1___width 1 -#define reg_mmu_rw_mm_cfg___seg_1___bit 1 -#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 -#define reg_mmu_rw_mm_cfg___seg_2___width 1 -#define reg_mmu_rw_mm_cfg___seg_2___bit 2 -#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 -#define reg_mmu_rw_mm_cfg___seg_3___width 1 -#define reg_mmu_rw_mm_cfg___seg_3___bit 3 -#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 -#define reg_mmu_rw_mm_cfg___seg_4___width 1 -#define reg_mmu_rw_mm_cfg___seg_4___bit 4 -#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 -#define reg_mmu_rw_mm_cfg___seg_5___width 1 -#define reg_mmu_rw_mm_cfg___seg_5___bit 5 -#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 -#define reg_mmu_rw_mm_cfg___seg_6___width 1 -#define reg_mmu_rw_mm_cfg___seg_6___bit 6 -#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 -#define reg_mmu_rw_mm_cfg___seg_7___width 1 -#define reg_mmu_rw_mm_cfg___seg_7___bit 7 -#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 -#define reg_mmu_rw_mm_cfg___seg_8___width 1 -#define reg_mmu_rw_mm_cfg___seg_8___bit 8 -#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 -#define reg_mmu_rw_mm_cfg___seg_9___width 1 -#define reg_mmu_rw_mm_cfg___seg_9___bit 9 -#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 -#define reg_mmu_rw_mm_cfg___seg_a___width 1 -#define reg_mmu_rw_mm_cfg___seg_a___bit 10 -#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 -#define reg_mmu_rw_mm_cfg___seg_b___width 1 -#define reg_mmu_rw_mm_cfg___seg_b___bit 11 -#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 -#define reg_mmu_rw_mm_cfg___seg_c___width 1 -#define reg_mmu_rw_mm_cfg___seg_c___bit 12 -#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 -#define reg_mmu_rw_mm_cfg___seg_d___width 1 -#define reg_mmu_rw_mm_cfg___seg_d___bit 13 -#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 -#define reg_mmu_rw_mm_cfg___seg_e___width 1 -#define reg_mmu_rw_mm_cfg___seg_e___bit 14 -#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 -#define reg_mmu_rw_mm_cfg___seg_f___width 1 -#define reg_mmu_rw_mm_cfg___seg_f___bit 15 -#define reg_mmu_rw_mm_cfg___inv___lsb 16 -#define reg_mmu_rw_mm_cfg___inv___width 1 -#define reg_mmu_rw_mm_cfg___inv___bit 16 -#define reg_mmu_rw_mm_cfg___ex___lsb 17 -#define reg_mmu_rw_mm_cfg___ex___width 1 -#define reg_mmu_rw_mm_cfg___ex___bit 17 -#define reg_mmu_rw_mm_cfg___acc___lsb 18 -#define reg_mmu_rw_mm_cfg___acc___width 1 -#define reg_mmu_rw_mm_cfg___acc___bit 18 -#define reg_mmu_rw_mm_cfg___we___lsb 19 -#define reg_mmu_rw_mm_cfg___we___width 1 -#define reg_mmu_rw_mm_cfg___we___bit 19 -#define reg_mmu_rw_mm_cfg_offset 0 - -/* Register rw_mm_kbase_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 -#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 -#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 -#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 -#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 -#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 -#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 -#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 -#define reg_mmu_rw_mm_kbase_lo_offset 4 - -/* Register rw_mm_kbase_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 -#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 -#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 -#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 -#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 -#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 -#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 -#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 -#define reg_mmu_rw_mm_kbase_hi_offset 8 - -/* Register r_mm_cause, scope mmu, type r */ -#define reg_mmu_r_mm_cause___pid___lsb 0 -#define reg_mmu_r_mm_cause___pid___width 8 -#define reg_mmu_r_mm_cause___op___lsb 8 -#define reg_mmu_r_mm_cause___op___width 2 -#define reg_mmu_r_mm_cause___vpn___lsb 13 -#define reg_mmu_r_mm_cause___vpn___width 19 -#define reg_mmu_r_mm_cause_offset 12 - -/* Register rw_mm_tlb_sel, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 -#define reg_mmu_rw_mm_tlb_sel___idx___width 4 -#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 -#define reg_mmu_rw_mm_tlb_sel___set___width 2 -#define reg_mmu_rw_mm_tlb_sel_offset 16 - -/* Register rw_mm_tlb_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 -#define reg_mmu_rw_mm_tlb_lo___x___width 1 -#define reg_mmu_rw_mm_tlb_lo___x___bit 0 -#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 -#define reg_mmu_rw_mm_tlb_lo___w___width 1 -#define reg_mmu_rw_mm_tlb_lo___w___bit 1 -#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 -#define reg_mmu_rw_mm_tlb_lo___k___width 1 -#define reg_mmu_rw_mm_tlb_lo___k___bit 2 -#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 -#define reg_mmu_rw_mm_tlb_lo___v___width 1 -#define reg_mmu_rw_mm_tlb_lo___v___bit 3 -#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 -#define reg_mmu_rw_mm_tlb_lo___g___width 1 -#define reg_mmu_rw_mm_tlb_lo___g___bit 4 -#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 -#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 -#define reg_mmu_rw_mm_tlb_lo_offset 20 - -/* Register rw_mm_tlb_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 -#define reg_mmu_rw_mm_tlb_hi___pid___width 8 -#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 -#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 -#define reg_mmu_rw_mm_tlb_hi_offset 24 - - -/* Constants */ -#define regk_mmu_execute 0x00000000 -#define regk_mmu_flush 0x00000003 -#define regk_mmu_linear 0x00000001 -#define regk_mmu_no 0x00000000 -#define regk_mmu_off 0x00000000 -#define regk_mmu_on 0x00000001 -#define regk_mmu_page 0x00000000 -#define regk_mmu_read 0x00000001 -#define regk_mmu_write 0x00000002 -#define regk_mmu_yes 0x00000001 -#endif /* __mmu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h deleted file mode 100644 index 339500bf3bc0..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h +++ /dev/null @@ -1,7 +0,0 @@ -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define R_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 13c725e4c774..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,632 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 76959b70cd2c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h deleted file mode 100644 index 10246f49fb28..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __rt_trace_defs_asm_h -#define __rt_trace_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope rt_trace, type rw */ -#define reg_rt_trace_rw_cfg___en___lsb 0 -#define reg_rt_trace_rw_cfg___en___width 1 -#define reg_rt_trace_rw_cfg___en___bit 0 -#define reg_rt_trace_rw_cfg___mode___lsb 1 -#define reg_rt_trace_rw_cfg___mode___width 1 -#define reg_rt_trace_rw_cfg___mode___bit 1 -#define reg_rt_trace_rw_cfg___owner___lsb 2 -#define reg_rt_trace_rw_cfg___owner___width 1 -#define reg_rt_trace_rw_cfg___owner___bit 2 -#define reg_rt_trace_rw_cfg___wp___lsb 3 -#define reg_rt_trace_rw_cfg___wp___width 1 -#define reg_rt_trace_rw_cfg___wp___bit 3 -#define reg_rt_trace_rw_cfg___stall___lsb 4 -#define reg_rt_trace_rw_cfg___stall___width 1 -#define reg_rt_trace_rw_cfg___stall___bit 4 -#define reg_rt_trace_rw_cfg___wp_start___lsb 8 -#define reg_rt_trace_rw_cfg___wp_start___width 7 -#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 -#define reg_rt_trace_rw_cfg___wp_stop___width 7 -#define reg_rt_trace_rw_cfg_offset 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 -#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 -#define reg_rt_trace_rw_tap_ctrl_offset 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -#define reg_rt_trace_r_tap_stat___dav___lsb 0 -#define reg_rt_trace_r_tap_stat___dav___width 1 -#define reg_rt_trace_r_tap_stat___dav___bit 0 -#define reg_rt_trace_r_tap_stat___empty___lsb 1 -#define reg_rt_trace_r_tap_stat___empty___width 1 -#define reg_rt_trace_r_tap_stat___empty___bit 1 -#define reg_rt_trace_r_tap_stat_offset 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_data_offset 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_hdata___op___lsb 0 -#define reg_rt_trace_rw_tap_hdata___op___width 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 -#define reg_rt_trace_rw_tap_hdata_offset 16 - -/* Register r_redir, scope rt_trace, type r */ -#define reg_rt_trace_r_redir_offset 20 - - -/* Constants */ -#define regk_rt_trace_brk 0x0000000c -#define regk_rt_trace_dbg 0x00000003 -#define regk_rt_trace_dbgdi 0x00000004 -#define regk_rt_trace_dbgdo 0x00000005 -#define regk_rt_trace_gmode 0x00000000 -#define regk_rt_trace_no 0x00000000 -#define regk_rt_trace_nop 0x00000000 -#define regk_rt_trace_normal 0x00000000 -#define regk_rt_trace_rdmem 0x00000007 -#define regk_rt_trace_rdmemb 0x00000009 -#define regk_rt_trace_rdpreg 0x00000002 -#define regk_rt_trace_rdreg 0x00000001 -#define regk_rt_trace_rdsreg 0x00000003 -#define regk_rt_trace_redir 0x00000006 -#define regk_rt_trace_ret 0x0000000b -#define regk_rt_trace_rw_cfg_default 0x00000000 -#define regk_rt_trace_trcfg 0x00000001 -#define regk_rt_trace_wp 0x00000001 -#define regk_rt_trace_wp0 0x00000001 -#define regk_rt_trace_wp1 0x00000002 -#define regk_rt_trace_wp2 0x00000004 -#define regk_rt_trace_wp3 0x00000008 -#define regk_rt_trace_wp4 0x00000010 -#define regk_rt_trace_wp5 0x00000020 -#define regk_rt_trace_wp6 0x00000040 -#define regk_rt_trace_wrmem 0x00000008 -#define regk_rt_trace_wrmemb 0x0000000a -#define regk_rt_trace_wrpreg 0x00000005 -#define regk_rt_trace_wrreg 0x00000004 -#define regk_rt_trace_wrsreg 0x00000006 -#define regk_rt_trace_yes 0x00000001 -#endif /* __rt_trace_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h deleted file mode 100644 index 4a2808bdf390..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h +++ /dev/null @@ -1,359 +0,0 @@ -#ifndef __ser_defs_asm_h -#define __ser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tr_ctrl, scope ser, type rw */ -#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 -#define reg_ser_rw_tr_ctrl___base_freq___width 3 -#define reg_ser_rw_tr_ctrl___en___lsb 3 -#define reg_ser_rw_tr_ctrl___en___width 1 -#define reg_ser_rw_tr_ctrl___en___bit 3 -#define reg_ser_rw_tr_ctrl___par___lsb 4 -#define reg_ser_rw_tr_ctrl___par___width 2 -#define reg_ser_rw_tr_ctrl___par_en___lsb 6 -#define reg_ser_rw_tr_ctrl___par_en___width 1 -#define reg_ser_rw_tr_ctrl___par_en___bit 6 -#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 -#define reg_ser_rw_tr_ctrl___data_bits___width 1 -#define reg_ser_rw_tr_ctrl___data_bits___bit 7 -#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 -#define reg_ser_rw_tr_ctrl___stop_bits___width 1 -#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 -#define reg_ser_rw_tr_ctrl___stop___lsb 9 -#define reg_ser_rw_tr_ctrl___stop___width 1 -#define reg_ser_rw_tr_ctrl___stop___bit 9 -#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 -#define reg_ser_rw_tr_ctrl___rts_delay___width 3 -#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 -#define reg_ser_rw_tr_ctrl___rts_setup___width 1 -#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 -#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 -#define reg_ser_rw_tr_ctrl___auto_rts___width 1 -#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 -#define reg_ser_rw_tr_ctrl___txd___lsb 15 -#define reg_ser_rw_tr_ctrl___txd___width 1 -#define reg_ser_rw_tr_ctrl___txd___bit 15 -#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 -#define reg_ser_rw_tr_ctrl___auto_cts___width 1 -#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 -#define reg_ser_rw_tr_ctrl_offset 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -#define reg_ser_rw_tr_dma_en___en___lsb 0 -#define reg_ser_rw_tr_dma_en___en___width 1 -#define reg_ser_rw_tr_dma_en___en___bit 0 -#define reg_ser_rw_tr_dma_en_offset 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 -#define reg_ser_rw_rec_ctrl___base_freq___width 3 -#define reg_ser_rw_rec_ctrl___en___lsb 3 -#define reg_ser_rw_rec_ctrl___en___width 1 -#define reg_ser_rw_rec_ctrl___en___bit 3 -#define reg_ser_rw_rec_ctrl___par___lsb 4 -#define reg_ser_rw_rec_ctrl___par___width 2 -#define reg_ser_rw_rec_ctrl___par_en___lsb 6 -#define reg_ser_rw_rec_ctrl___par_en___width 1 -#define reg_ser_rw_rec_ctrl___par_en___bit 6 -#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 -#define reg_ser_rw_rec_ctrl___data_bits___width 1 -#define reg_ser_rw_rec_ctrl___data_bits___bit 7 -#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 -#define reg_ser_rw_rec_ctrl___dma_mode___width 1 -#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 -#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 -#define reg_ser_rw_rec_ctrl___dma_err___width 1 -#define reg_ser_rw_rec_ctrl___dma_err___bit 9 -#define reg_ser_rw_rec_ctrl___sampling___lsb 10 -#define reg_ser_rw_rec_ctrl___sampling___width 1 -#define reg_ser_rw_rec_ctrl___sampling___bit 10 -#define reg_ser_rw_rec_ctrl___timeout___lsb 11 -#define reg_ser_rw_rec_ctrl___timeout___width 3 -#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 -#define reg_ser_rw_rec_ctrl___auto_eop___width 1 -#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 -#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 -#define reg_ser_rw_rec_ctrl___half_duplex___width 1 -#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 -#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 -#define reg_ser_rw_rec_ctrl___rts_n___width 1 -#define reg_ser_rw_rec_ctrl___rts_n___bit 16 -#define reg_ser_rw_rec_ctrl___loopback___lsb 17 -#define reg_ser_rw_rec_ctrl___loopback___width 1 -#define reg_ser_rw_rec_ctrl___loopback___bit 17 -#define reg_ser_rw_rec_ctrl_offset 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -#define reg_ser_rw_tr_baud_div___div___lsb 0 -#define reg_ser_rw_tr_baud_div___div___width 16 -#define reg_ser_rw_tr_baud_div_offset 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -#define reg_ser_rw_rec_baud_div___div___lsb 0 -#define reg_ser_rw_rec_baud_div___div___width 16 -#define reg_ser_rw_rec_baud_div_offset 16 - -/* Register rw_xoff, scope ser, type rw */ -#define reg_ser_rw_xoff___chr___lsb 0 -#define reg_ser_rw_xoff___chr___width 8 -#define reg_ser_rw_xoff___automatic___lsb 8 -#define reg_ser_rw_xoff___automatic___width 1 -#define reg_ser_rw_xoff___automatic___bit 8 -#define reg_ser_rw_xoff_offset 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -#define reg_ser_rw_xoff_clr___clr___lsb 0 -#define reg_ser_rw_xoff_clr___clr___width 1 -#define reg_ser_rw_xoff_clr___clr___bit 0 -#define reg_ser_rw_xoff_clr_offset 24 - -/* Register rw_dout, scope ser, type rw */ -#define reg_ser_rw_dout___data___lsb 0 -#define reg_ser_rw_dout___data___width 8 -#define reg_ser_rw_dout_offset 28 - -/* Register rs_stat_din, scope ser, type rs */ -#define reg_ser_rs_stat_din___data___lsb 0 -#define reg_ser_rs_stat_din___data___width 8 -#define reg_ser_rs_stat_din___dav___lsb 16 -#define reg_ser_rs_stat_din___dav___width 1 -#define reg_ser_rs_stat_din___dav___bit 16 -#define reg_ser_rs_stat_din___framing_err___lsb 17 -#define reg_ser_rs_stat_din___framing_err___width 1 -#define reg_ser_rs_stat_din___framing_err___bit 17 -#define reg_ser_rs_stat_din___par_err___lsb 18 -#define reg_ser_rs_stat_din___par_err___width 1 -#define reg_ser_rs_stat_din___par_err___bit 18 -#define reg_ser_rs_stat_din___orun___lsb 19 -#define reg_ser_rs_stat_din___orun___width 1 -#define reg_ser_rs_stat_din___orun___bit 19 -#define reg_ser_rs_stat_din___rec_err___lsb 20 -#define reg_ser_rs_stat_din___rec_err___width 1 -#define reg_ser_rs_stat_din___rec_err___bit 20 -#define reg_ser_rs_stat_din___rxd___lsb 21 -#define reg_ser_rs_stat_din___rxd___width 1 -#define reg_ser_rs_stat_din___rxd___bit 21 -#define reg_ser_rs_stat_din___tr_idle___lsb 22 -#define reg_ser_rs_stat_din___tr_idle___width 1 -#define reg_ser_rs_stat_din___tr_idle___bit 22 -#define reg_ser_rs_stat_din___tr_empty___lsb 23 -#define reg_ser_rs_stat_din___tr_empty___width 1 -#define reg_ser_rs_stat_din___tr_empty___bit 23 -#define reg_ser_rs_stat_din___tr_rdy___lsb 24 -#define reg_ser_rs_stat_din___tr_rdy___width 1 -#define reg_ser_rs_stat_din___tr_rdy___bit 24 -#define reg_ser_rs_stat_din___cts_n___lsb 25 -#define reg_ser_rs_stat_din___cts_n___width 1 -#define reg_ser_rs_stat_din___cts_n___bit 25 -#define reg_ser_rs_stat_din___xoff_detect___lsb 26 -#define reg_ser_rs_stat_din___xoff_detect___width 1 -#define reg_ser_rs_stat_din___xoff_detect___bit 26 -#define reg_ser_rs_stat_din___rts_n___lsb 27 -#define reg_ser_rs_stat_din___rts_n___width 1 -#define reg_ser_rs_stat_din___rts_n___bit 27 -#define reg_ser_rs_stat_din___txd___lsb 28 -#define reg_ser_rs_stat_din___txd___width 1 -#define reg_ser_rs_stat_din___txd___bit 28 -#define reg_ser_rs_stat_din_offset 32 - -/* Register r_stat_din, scope ser, type r */ -#define reg_ser_r_stat_din___data___lsb 0 -#define reg_ser_r_stat_din___data___width 8 -#define reg_ser_r_stat_din___dav___lsb 16 -#define reg_ser_r_stat_din___dav___width 1 -#define reg_ser_r_stat_din___dav___bit 16 -#define reg_ser_r_stat_din___framing_err___lsb 17 -#define reg_ser_r_stat_din___framing_err___width 1 -#define reg_ser_r_stat_din___framing_err___bit 17 -#define reg_ser_r_stat_din___par_err___lsb 18 -#define reg_ser_r_stat_din___par_err___width 1 -#define reg_ser_r_stat_din___par_err___bit 18 -#define reg_ser_r_stat_din___orun___lsb 19 -#define reg_ser_r_stat_din___orun___width 1 -#define reg_ser_r_stat_din___orun___bit 19 -#define reg_ser_r_stat_din___rec_err___lsb 20 -#define reg_ser_r_stat_din___rec_err___width 1 -#define reg_ser_r_stat_din___rec_err___bit 20 -#define reg_ser_r_stat_din___rxd___lsb 21 -#define reg_ser_r_stat_din___rxd___width 1 -#define reg_ser_r_stat_din___rxd___bit 21 -#define reg_ser_r_stat_din___tr_idle___lsb 22 -#define reg_ser_r_stat_din___tr_idle___width 1 -#define reg_ser_r_stat_din___tr_idle___bit 22 -#define reg_ser_r_stat_din___tr_empty___lsb 23 -#define reg_ser_r_stat_din___tr_empty___width 1 -#define reg_ser_r_stat_din___tr_empty___bit 23 -#define reg_ser_r_stat_din___tr_rdy___lsb 24 -#define reg_ser_r_stat_din___tr_rdy___width 1 -#define reg_ser_r_stat_din___tr_rdy___bit 24 -#define reg_ser_r_stat_din___cts_n___lsb 25 -#define reg_ser_r_stat_din___cts_n___width 1 -#define reg_ser_r_stat_din___cts_n___bit 25 -#define reg_ser_r_stat_din___xoff_detect___lsb 26 -#define reg_ser_r_stat_din___xoff_detect___width 1 -#define reg_ser_r_stat_din___xoff_detect___bit 26 -#define reg_ser_r_stat_din___rts_n___lsb 27 -#define reg_ser_r_stat_din___rts_n___width 1 -#define reg_ser_r_stat_din___rts_n___bit 27 -#define reg_ser_r_stat_din___txd___lsb 28 -#define reg_ser_r_stat_din___txd___width 1 -#define reg_ser_r_stat_din___txd___bit 28 -#define reg_ser_r_stat_din_offset 36 - -/* Register rw_rec_eop, scope ser, type rw */ -#define reg_ser_rw_rec_eop___set___lsb 0 -#define reg_ser_rw_rec_eop___set___width 1 -#define reg_ser_rw_rec_eop___set___bit 0 -#define reg_ser_rw_rec_eop_offset 40 - -/* Register rw_intr_mask, scope ser, type rw */ -#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 -#define reg_ser_rw_intr_mask___tr_rdy___width 1 -#define reg_ser_rw_intr_mask___tr_rdy___bit 0 -#define reg_ser_rw_intr_mask___tr_empty___lsb 1 -#define reg_ser_rw_intr_mask___tr_empty___width 1 -#define reg_ser_rw_intr_mask___tr_empty___bit 1 -#define reg_ser_rw_intr_mask___tr_idle___lsb 2 -#define reg_ser_rw_intr_mask___tr_idle___width 1 -#define reg_ser_rw_intr_mask___tr_idle___bit 2 -#define reg_ser_rw_intr_mask___dav___lsb 3 -#define reg_ser_rw_intr_mask___dav___width 1 -#define reg_ser_rw_intr_mask___dav___bit 3 -#define reg_ser_rw_intr_mask_offset 44 - -/* Register rw_ack_intr, scope ser, type rw */ -#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 -#define reg_ser_rw_ack_intr___tr_rdy___width 1 -#define reg_ser_rw_ack_intr___tr_rdy___bit 0 -#define reg_ser_rw_ack_intr___tr_empty___lsb 1 -#define reg_ser_rw_ack_intr___tr_empty___width 1 -#define reg_ser_rw_ack_intr___tr_empty___bit 1 -#define reg_ser_rw_ack_intr___tr_idle___lsb 2 -#define reg_ser_rw_ack_intr___tr_idle___width 1 -#define reg_ser_rw_ack_intr___tr_idle___bit 2 -#define reg_ser_rw_ack_intr___dav___lsb 3 -#define reg_ser_rw_ack_intr___dav___width 1 -#define reg_ser_rw_ack_intr___dav___bit 3 -#define reg_ser_rw_ack_intr_offset 48 - -/* Register r_intr, scope ser, type r */ -#define reg_ser_r_intr___tr_rdy___lsb 0 -#define reg_ser_r_intr___tr_rdy___width 1 -#define reg_ser_r_intr___tr_rdy___bit 0 -#define reg_ser_r_intr___tr_empty___lsb 1 -#define reg_ser_r_intr___tr_empty___width 1 -#define reg_ser_r_intr___tr_empty___bit 1 -#define reg_ser_r_intr___tr_idle___lsb 2 -#define reg_ser_r_intr___tr_idle___width 1 -#define reg_ser_r_intr___tr_idle___bit 2 -#define reg_ser_r_intr___dav___lsb 3 -#define reg_ser_r_intr___dav___width 1 -#define reg_ser_r_intr___dav___bit 3 -#define reg_ser_r_intr_offset 52 - -/* Register r_masked_intr, scope ser, type r */ -#define reg_ser_r_masked_intr___tr_rdy___lsb 0 -#define reg_ser_r_masked_intr___tr_rdy___width 1 -#define reg_ser_r_masked_intr___tr_rdy___bit 0 -#define reg_ser_r_masked_intr___tr_empty___lsb 1 -#define reg_ser_r_masked_intr___tr_empty___width 1 -#define reg_ser_r_masked_intr___tr_empty___bit 1 -#define reg_ser_r_masked_intr___tr_idle___lsb 2 -#define reg_ser_r_masked_intr___tr_idle___width 1 -#define reg_ser_r_masked_intr___tr_idle___bit 2 -#define reg_ser_r_masked_intr___dav___lsb 3 -#define reg_ser_r_masked_intr___dav___width 1 -#define reg_ser_r_masked_intr___dav___bit 3 -#define reg_ser_r_masked_intr_offset 56 - - -/* Constants */ -#define regk_ser_active 0x00000000 -#define regk_ser_bits1 0x00000000 -#define regk_ser_bits2 0x00000001 -#define regk_ser_bits7 0x00000001 -#define regk_ser_bits8 0x00000000 -#define regk_ser_del0_5 0x00000000 -#define regk_ser_del1 0x00000001 -#define regk_ser_del1_5 0x00000002 -#define regk_ser_del2 0x00000003 -#define regk_ser_del2_5 0x00000004 -#define regk_ser_del3 0x00000005 -#define regk_ser_del3_5 0x00000006 -#define regk_ser_del4 0x00000007 -#define regk_ser_even 0x00000000 -#define regk_ser_ext 0x00000001 -#define regk_ser_f100 0x00000007 -#define regk_ser_f29_493 0x00000004 -#define regk_ser_f32 0x00000005 -#define regk_ser_f32_768 0x00000006 -#define regk_ser_ignore 0x00000001 -#define regk_ser_inactive 0x00000001 -#define regk_ser_majority 0x00000001 -#define regk_ser_mark 0x00000002 -#define regk_ser_middle 0x00000000 -#define regk_ser_no 0x00000000 -#define regk_ser_odd 0x00000001 -#define regk_ser_off 0x00000000 -#define regk_ser_rw_intr_mask_default 0x00000000 -#define regk_ser_rw_rec_baud_div_default 0x00000000 -#define regk_ser_rw_rec_ctrl_default 0x00010000 -#define regk_ser_rw_tr_baud_div_default 0x00000000 -#define regk_ser_rw_tr_ctrl_default 0x00008000 -#define regk_ser_rw_tr_dma_en_default 0x00000000 -#define regk_ser_rw_xoff_default 0x00000000 -#define regk_ser_space 0x00000003 -#define regk_ser_stop 0x00000000 -#define regk_ser_yes 0x00000001 -#endif /* __ser_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h deleted file mode 100644 index 27d4d91b3abd..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h +++ /dev/null @@ -1,462 +0,0 @@ -#ifndef __sser_defs_asm_h -#define __sser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope sser, type rw */ -#define reg_sser_rw_cfg___clk_div___lsb 0 -#define reg_sser_rw_cfg___clk_div___width 16 -#define reg_sser_rw_cfg___base_freq___lsb 16 -#define reg_sser_rw_cfg___base_freq___width 3 -#define reg_sser_rw_cfg___gate_clk___lsb 19 -#define reg_sser_rw_cfg___gate_clk___width 1 -#define reg_sser_rw_cfg___gate_clk___bit 19 -#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 -#define reg_sser_rw_cfg___clkgate_ctrl___width 1 -#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 -#define reg_sser_rw_cfg___clkgate_in___lsb 21 -#define reg_sser_rw_cfg___clkgate_in___width 1 -#define reg_sser_rw_cfg___clkgate_in___bit 21 -#define reg_sser_rw_cfg___clk_dir___lsb 22 -#define reg_sser_rw_cfg___clk_dir___width 1 -#define reg_sser_rw_cfg___clk_dir___bit 22 -#define reg_sser_rw_cfg___clk_od_mode___lsb 23 -#define reg_sser_rw_cfg___clk_od_mode___width 1 -#define reg_sser_rw_cfg___clk_od_mode___bit 23 -#define reg_sser_rw_cfg___out_clk_pol___lsb 24 -#define reg_sser_rw_cfg___out_clk_pol___width 1 -#define reg_sser_rw_cfg___out_clk_pol___bit 24 -#define reg_sser_rw_cfg___out_clk_src___lsb 25 -#define reg_sser_rw_cfg___out_clk_src___width 2 -#define reg_sser_rw_cfg___clk_in_sel___lsb 27 -#define reg_sser_rw_cfg___clk_in_sel___width 1 -#define reg_sser_rw_cfg___clk_in_sel___bit 27 -#define reg_sser_rw_cfg___hold_pol___lsb 28 -#define reg_sser_rw_cfg___hold_pol___width 1 -#define reg_sser_rw_cfg___hold_pol___bit 28 -#define reg_sser_rw_cfg___prepare___lsb 29 -#define reg_sser_rw_cfg___prepare___width 1 -#define reg_sser_rw_cfg___prepare___bit 29 -#define reg_sser_rw_cfg___en___lsb 30 -#define reg_sser_rw_cfg___en___width 1 -#define reg_sser_rw_cfg___en___bit 30 -#define reg_sser_rw_cfg_offset 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -#define reg_sser_rw_frm_cfg___wordrate___lsb 0 -#define reg_sser_rw_frm_cfg___wordrate___width 10 -#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 -#define reg_sser_rw_frm_cfg___rec_delay___width 3 -#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 -#define reg_sser_rw_frm_cfg___tr_delay___width 3 -#define reg_sser_rw_frm_cfg___early_wend___lsb 16 -#define reg_sser_rw_frm_cfg___early_wend___width 1 -#define reg_sser_rw_frm_cfg___early_wend___bit 16 -#define reg_sser_rw_frm_cfg___level___lsb 17 -#define reg_sser_rw_frm_cfg___level___width 2 -#define reg_sser_rw_frm_cfg___type___lsb 19 -#define reg_sser_rw_frm_cfg___type___width 1 -#define reg_sser_rw_frm_cfg___type___bit 19 -#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 -#define reg_sser_rw_frm_cfg___clk_pol___width 1 -#define reg_sser_rw_frm_cfg___clk_pol___bit 20 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 -#define reg_sser_rw_frm_cfg___clk_src___lsb 22 -#define reg_sser_rw_frm_cfg___clk_src___width 1 -#define reg_sser_rw_frm_cfg___clk_src___bit 22 -#define reg_sser_rw_frm_cfg___out_off___lsb 23 -#define reg_sser_rw_frm_cfg___out_off___width 1 -#define reg_sser_rw_frm_cfg___out_off___bit 23 -#define reg_sser_rw_frm_cfg___out_on___lsb 24 -#define reg_sser_rw_frm_cfg___out_on___width 1 -#define reg_sser_rw_frm_cfg___out_on___bit 24 -#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 -#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 -#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 -#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 -#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 -#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 -#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 -#define reg_sser_rw_frm_cfg___status_pin_use___width 2 -#define reg_sser_rw_frm_cfg_offset 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -#define reg_sser_rw_tr_cfg___tr_en___lsb 0 -#define reg_sser_rw_tr_cfg___tr_en___width 1 -#define reg_sser_rw_tr_cfg___tr_en___bit 0 -#define reg_sser_rw_tr_cfg___stop___lsb 1 -#define reg_sser_rw_tr_cfg___stop___width 1 -#define reg_sser_rw_tr_cfg___stop___bit 1 -#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 -#define reg_sser_rw_tr_cfg___urun_stop___width 1 -#define reg_sser_rw_tr_cfg___urun_stop___bit 2 -#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 -#define reg_sser_rw_tr_cfg___eop_stop___width 1 -#define reg_sser_rw_tr_cfg___eop_stop___bit 3 -#define reg_sser_rw_tr_cfg___sample_size___lsb 4 -#define reg_sser_rw_tr_cfg___sample_size___width 6 -#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 -#define reg_sser_rw_tr_cfg___sh_dir___width 1 -#define reg_sser_rw_tr_cfg___sh_dir___bit 10 -#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 -#define reg_sser_rw_tr_cfg___clk_pol___width 1 -#define reg_sser_rw_tr_cfg___clk_pol___bit 11 -#define reg_sser_rw_tr_cfg___clk_src___lsb 12 -#define reg_sser_rw_tr_cfg___clk_src___width 1 -#define reg_sser_rw_tr_cfg___clk_src___bit 12 -#define reg_sser_rw_tr_cfg___use_dma___lsb 13 -#define reg_sser_rw_tr_cfg___use_dma___width 1 -#define reg_sser_rw_tr_cfg___use_dma___bit 13 -#define reg_sser_rw_tr_cfg___mode___lsb 14 -#define reg_sser_rw_tr_cfg___mode___width 2 -#define reg_sser_rw_tr_cfg___frm_src___lsb 16 -#define reg_sser_rw_tr_cfg___frm_src___width 1 -#define reg_sser_rw_tr_cfg___frm_src___bit 16 -#define reg_sser_rw_tr_cfg___use60958___lsb 17 -#define reg_sser_rw_tr_cfg___use60958___width 1 -#define reg_sser_rw_tr_cfg___use60958___bit 17 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 -#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 -#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 -#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 -#define reg_sser_rw_tr_cfg___use_md___lsb 21 -#define reg_sser_rw_tr_cfg___use_md___width 1 -#define reg_sser_rw_tr_cfg___use_md___bit 21 -#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 -#define reg_sser_rw_tr_cfg___dual_i2s___width 1 -#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 -#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 -#define reg_sser_rw_tr_cfg___data_pin_use___width 2 -#define reg_sser_rw_tr_cfg___od_mode___lsb 25 -#define reg_sser_rw_tr_cfg___od_mode___width 1 -#define reg_sser_rw_tr_cfg___od_mode___bit 25 -#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 -#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 -#define reg_sser_rw_tr_cfg_offset 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -#define reg_sser_rw_rec_cfg___rec_en___lsb 0 -#define reg_sser_rw_rec_cfg___rec_en___width 1 -#define reg_sser_rw_rec_cfg___rec_en___bit 0 -#define reg_sser_rw_rec_cfg___force_eop___lsb 1 -#define reg_sser_rw_rec_cfg___force_eop___width 1 -#define reg_sser_rw_rec_cfg___force_eop___bit 1 -#define reg_sser_rw_rec_cfg___stop___lsb 2 -#define reg_sser_rw_rec_cfg___stop___width 1 -#define reg_sser_rw_rec_cfg___stop___bit 2 -#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 -#define reg_sser_rw_rec_cfg___orun_stop___width 1 -#define reg_sser_rw_rec_cfg___orun_stop___bit 3 -#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 -#define reg_sser_rw_rec_cfg___eop_stop___width 1 -#define reg_sser_rw_rec_cfg___eop_stop___bit 4 -#define reg_sser_rw_rec_cfg___sample_size___lsb 5 -#define reg_sser_rw_rec_cfg___sample_size___width 6 -#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 -#define reg_sser_rw_rec_cfg___sh_dir___width 1 -#define reg_sser_rw_rec_cfg___sh_dir___bit 11 -#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 -#define reg_sser_rw_rec_cfg___clk_pol___width 1 -#define reg_sser_rw_rec_cfg___clk_pol___bit 12 -#define reg_sser_rw_rec_cfg___clk_src___lsb 13 -#define reg_sser_rw_rec_cfg___clk_src___width 1 -#define reg_sser_rw_rec_cfg___clk_src___bit 13 -#define reg_sser_rw_rec_cfg___use_dma___lsb 14 -#define reg_sser_rw_rec_cfg___use_dma___width 1 -#define reg_sser_rw_rec_cfg___use_dma___bit 14 -#define reg_sser_rw_rec_cfg___mode___lsb 15 -#define reg_sser_rw_rec_cfg___mode___width 2 -#define reg_sser_rw_rec_cfg___frm_src___lsb 17 -#define reg_sser_rw_rec_cfg___frm_src___width 2 -#define reg_sser_rw_rec_cfg___use60958___lsb 19 -#define reg_sser_rw_rec_cfg___use60958___width 1 -#define reg_sser_rw_rec_cfg___use60958___bit 19 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 -#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 -#define reg_sser_rw_rec_cfg___slave2_en___width 1 -#define reg_sser_rw_rec_cfg___slave2_en___bit 25 -#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 -#define reg_sser_rw_rec_cfg___slave3_en___width 1 -#define reg_sser_rw_rec_cfg___slave3_en___bit 26 -#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 -#define reg_sser_rw_rec_cfg___fifo_thr___width 2 -#define reg_sser_rw_rec_cfg_offset 12 - -/* Register rw_tr_data, scope sser, type rw */ -#define reg_sser_rw_tr_data___data___lsb 0 -#define reg_sser_rw_tr_data___data___width 16 -#define reg_sser_rw_tr_data___md___lsb 16 -#define reg_sser_rw_tr_data___md___width 1 -#define reg_sser_rw_tr_data___md___bit 16 -#define reg_sser_rw_tr_data_offset 16 - -/* Register r_rec_data, scope sser, type r */ -#define reg_sser_r_rec_data___data___lsb 0 -#define reg_sser_r_rec_data___data___width 16 -#define reg_sser_r_rec_data___md___lsb 16 -#define reg_sser_r_rec_data___md___width 1 -#define reg_sser_r_rec_data___md___bit 16 -#define reg_sser_r_rec_data___ext_clk___lsb 17 -#define reg_sser_r_rec_data___ext_clk___width 1 -#define reg_sser_r_rec_data___ext_clk___bit 17 -#define reg_sser_r_rec_data___status_in___lsb 18 -#define reg_sser_r_rec_data___status_in___width 1 -#define reg_sser_r_rec_data___status_in___bit 18 -#define reg_sser_r_rec_data___frame_in___lsb 19 -#define reg_sser_r_rec_data___frame_in___width 1 -#define reg_sser_r_rec_data___frame_in___bit 19 -#define reg_sser_r_rec_data___din___lsb 20 -#define reg_sser_r_rec_data___din___width 1 -#define reg_sser_r_rec_data___din___bit 20 -#define reg_sser_r_rec_data___data_in___lsb 21 -#define reg_sser_r_rec_data___data_in___width 1 -#define reg_sser_r_rec_data___data_in___bit 21 -#define reg_sser_r_rec_data___clk_in___lsb 22 -#define reg_sser_r_rec_data___clk_in___width 1 -#define reg_sser_r_rec_data___clk_in___bit 22 -#define reg_sser_r_rec_data_offset 20 - -/* Register rw_extra, scope sser, type rw */ -#define reg_sser_rw_extra___clkoff_cycles___lsb 0 -#define reg_sser_rw_extra___clkoff_cycles___width 20 -#define reg_sser_rw_extra___clkoff_en___lsb 20 -#define reg_sser_rw_extra___clkoff_en___width 1 -#define reg_sser_rw_extra___clkoff_en___bit 20 -#define reg_sser_rw_extra___clkon_en___lsb 21 -#define reg_sser_rw_extra___clkon_en___width 1 -#define reg_sser_rw_extra___clkon_en___bit 21 -#define reg_sser_rw_extra___dout_delay___lsb 22 -#define reg_sser_rw_extra___dout_delay___width 5 -#define reg_sser_rw_extra_offset 24 - -/* Register rw_intr_mask, scope sser, type rw */ -#define reg_sser_rw_intr_mask___trdy___lsb 0 -#define reg_sser_rw_intr_mask___trdy___width 1 -#define reg_sser_rw_intr_mask___trdy___bit 0 -#define reg_sser_rw_intr_mask___rdav___lsb 1 -#define reg_sser_rw_intr_mask___rdav___width 1 -#define reg_sser_rw_intr_mask___rdav___bit 1 -#define reg_sser_rw_intr_mask___tidle___lsb 2 -#define reg_sser_rw_intr_mask___tidle___width 1 -#define reg_sser_rw_intr_mask___tidle___bit 2 -#define reg_sser_rw_intr_mask___rstop___lsb 3 -#define reg_sser_rw_intr_mask___rstop___width 1 -#define reg_sser_rw_intr_mask___rstop___bit 3 -#define reg_sser_rw_intr_mask___urun___lsb 4 -#define reg_sser_rw_intr_mask___urun___width 1 -#define reg_sser_rw_intr_mask___urun___bit 4 -#define reg_sser_rw_intr_mask___orun___lsb 5 -#define reg_sser_rw_intr_mask___orun___width 1 -#define reg_sser_rw_intr_mask___orun___bit 5 -#define reg_sser_rw_intr_mask___md_rec___lsb 6 -#define reg_sser_rw_intr_mask___md_rec___width 1 -#define reg_sser_rw_intr_mask___md_rec___bit 6 -#define reg_sser_rw_intr_mask___md_sent___lsb 7 -#define reg_sser_rw_intr_mask___md_sent___width 1 -#define reg_sser_rw_intr_mask___md_sent___bit 7 -#define reg_sser_rw_intr_mask___r958err___lsb 8 -#define reg_sser_rw_intr_mask___r958err___width 1 -#define reg_sser_rw_intr_mask___r958err___bit 8 -#define reg_sser_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope sser, type rw */ -#define reg_sser_rw_ack_intr___trdy___lsb 0 -#define reg_sser_rw_ack_intr___trdy___width 1 -#define reg_sser_rw_ack_intr___trdy___bit 0 -#define reg_sser_rw_ack_intr___rdav___lsb 1 -#define reg_sser_rw_ack_intr___rdav___width 1 -#define reg_sser_rw_ack_intr___rdav___bit 1 -#define reg_sser_rw_ack_intr___tidle___lsb 2 -#define reg_sser_rw_ack_intr___tidle___width 1 -#define reg_sser_rw_ack_intr___tidle___bit 2 -#define reg_sser_rw_ack_intr___rstop___lsb 3 -#define reg_sser_rw_ack_intr___rstop___width 1 -#define reg_sser_rw_ack_intr___rstop___bit 3 -#define reg_sser_rw_ack_intr___urun___lsb 4 -#define reg_sser_rw_ack_intr___urun___width 1 -#define reg_sser_rw_ack_intr___urun___bit 4 -#define reg_sser_rw_ack_intr___orun___lsb 5 -#define reg_sser_rw_ack_intr___orun___width 1 -#define reg_sser_rw_ack_intr___orun___bit 5 -#define reg_sser_rw_ack_intr___md_rec___lsb 6 -#define reg_sser_rw_ack_intr___md_rec___width 1 -#define reg_sser_rw_ack_intr___md_rec___bit 6 -#define reg_sser_rw_ack_intr___md_sent___lsb 7 -#define reg_sser_rw_ack_intr___md_sent___width 1 -#define reg_sser_rw_ack_intr___md_sent___bit 7 -#define reg_sser_rw_ack_intr___r958err___lsb 8 -#define reg_sser_rw_ack_intr___r958err___width 1 -#define reg_sser_rw_ack_intr___r958err___bit 8 -#define reg_sser_rw_ack_intr_offset 32 - -/* Register r_intr, scope sser, type r */ -#define reg_sser_r_intr___trdy___lsb 0 -#define reg_sser_r_intr___trdy___width 1 -#define reg_sser_r_intr___trdy___bit 0 -#define reg_sser_r_intr___rdav___lsb 1 -#define reg_sser_r_intr___rdav___width 1 -#define reg_sser_r_intr___rdav___bit 1 -#define reg_sser_r_intr___tidle___lsb 2 -#define reg_sser_r_intr___tidle___width 1 -#define reg_sser_r_intr___tidle___bit 2 -#define reg_sser_r_intr___rstop___lsb 3 -#define reg_sser_r_intr___rstop___width 1 -#define reg_sser_r_intr___rstop___bit 3 -#define reg_sser_r_intr___urun___lsb 4 -#define reg_sser_r_intr___urun___width 1 -#define reg_sser_r_intr___urun___bit 4 -#define reg_sser_r_intr___orun___lsb 5 -#define reg_sser_r_intr___orun___width 1 -#define reg_sser_r_intr___orun___bit 5 -#define reg_sser_r_intr___md_rec___lsb 6 -#define reg_sser_r_intr___md_rec___width 1 -#define reg_sser_r_intr___md_rec___bit 6 -#define reg_sser_r_intr___md_sent___lsb 7 -#define reg_sser_r_intr___md_sent___width 1 -#define reg_sser_r_intr___md_sent___bit 7 -#define reg_sser_r_intr___r958err___lsb 8 -#define reg_sser_r_intr___r958err___width 1 -#define reg_sser_r_intr___r958err___bit 8 -#define reg_sser_r_intr_offset 36 - -/* Register r_masked_intr, scope sser, type r */ -#define reg_sser_r_masked_intr___trdy___lsb 0 -#define reg_sser_r_masked_intr___trdy___width 1 -#define reg_sser_r_masked_intr___trdy___bit 0 -#define reg_sser_r_masked_intr___rdav___lsb 1 -#define reg_sser_r_masked_intr___rdav___width 1 -#define reg_sser_r_masked_intr___rdav___bit 1 -#define reg_sser_r_masked_intr___tidle___lsb 2 -#define reg_sser_r_masked_intr___tidle___width 1 -#define reg_sser_r_masked_intr___tidle___bit 2 -#define reg_sser_r_masked_intr___rstop___lsb 3 -#define reg_sser_r_masked_intr___rstop___width 1 -#define reg_sser_r_masked_intr___rstop___bit 3 -#define reg_sser_r_masked_intr___urun___lsb 4 -#define reg_sser_r_masked_intr___urun___width 1 -#define reg_sser_r_masked_intr___urun___bit 4 -#define reg_sser_r_masked_intr___orun___lsb 5 -#define reg_sser_r_masked_intr___orun___width 1 -#define reg_sser_r_masked_intr___orun___bit 5 -#define reg_sser_r_masked_intr___md_rec___lsb 6 -#define reg_sser_r_masked_intr___md_rec___width 1 -#define reg_sser_r_masked_intr___md_rec___bit 6 -#define reg_sser_r_masked_intr___md_sent___lsb 7 -#define reg_sser_r_masked_intr___md_sent___width 1 -#define reg_sser_r_masked_intr___md_sent___bit 7 -#define reg_sser_r_masked_intr___r958err___lsb 8 -#define reg_sser_r_masked_intr___r958err___width 1 -#define reg_sser_r_masked_intr___r958err___bit 8 -#define reg_sser_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_sser_both 0x00000002 -#define regk_sser_bulk 0x00000001 -#define regk_sser_clk100 0x00000000 -#define regk_sser_clk_in 0x00000000 -#define regk_sser_const0 0x00000003 -#define regk_sser_dout 0x00000002 -#define regk_sser_edge 0x00000000 -#define regk_sser_ext 0x00000001 -#define regk_sser_ext_clk 0x00000001 -#define regk_sser_f100 0x00000000 -#define regk_sser_f29_493 0x00000004 -#define regk_sser_f32 0x00000005 -#define regk_sser_f32_768 0x00000006 -#define regk_sser_frm 0x00000003 -#define regk_sser_gio0 0x00000000 -#define regk_sser_gio1 0x00000001 -#define regk_sser_hispeed 0x00000001 -#define regk_sser_hold 0x00000002 -#define regk_sser_in 0x00000000 -#define regk_sser_inf 0x00000003 -#define regk_sser_intern 0x00000000 -#define regk_sser_intern_clk 0x00000001 -#define regk_sser_intern_tb 0x00000000 -#define regk_sser_iso 0x00000000 -#define regk_sser_level 0x00000001 -#define regk_sser_lospeed 0x00000000 -#define regk_sser_lsbfirst 0x00000000 -#define regk_sser_msbfirst 0x00000001 -#define regk_sser_neg 0x00000001 -#define regk_sser_neg_lo 0x00000000 -#define regk_sser_no 0x00000000 -#define regk_sser_no_clk 0x00000007 -#define regk_sser_nojitter 0x00000002 -#define regk_sser_out 0x00000001 -#define regk_sser_pos 0x00000000 -#define regk_sser_pos_hi 0x00000001 -#define regk_sser_rec 0x00000000 -#define regk_sser_rw_cfg_default 0x00000000 -#define regk_sser_rw_extra_default 0x00000000 -#define regk_sser_rw_frm_cfg_default 0x00000000 -#define regk_sser_rw_intr_mask_default 0x00000000 -#define regk_sser_rw_rec_cfg_default 0x00000000 -#define regk_sser_rw_tr_cfg_default 0x01800000 -#define regk_sser_rw_tr_data_default 0x00000000 -#define regk_sser_thr16 0x00000001 -#define regk_sser_thr32 0x00000002 -#define regk_sser_thr8 0x00000000 -#define regk_sser_tr 0x00000001 -#define regk_sser_ts_out 0x00000003 -#define regk_sser_tx_bulk 0x00000002 -#define regk_sser_wiresave 0x00000002 -#define regk_sser_yes 0x00000001 -#endif /* __sser_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h deleted file mode 100644 index 55083e6aec93..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef __strcop_defs_asm_h -#define __strcop_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strcop, type rw */ -#define reg_strcop_rw_cfg___td3___lsb 0 -#define reg_strcop_rw_cfg___td3___width 1 -#define reg_strcop_rw_cfg___td3___bit 0 -#define reg_strcop_rw_cfg___td2___lsb 1 -#define reg_strcop_rw_cfg___td2___width 1 -#define reg_strcop_rw_cfg___td2___bit 1 -#define reg_strcop_rw_cfg___td1___lsb 2 -#define reg_strcop_rw_cfg___td1___width 1 -#define reg_strcop_rw_cfg___td1___bit 2 -#define reg_strcop_rw_cfg___ipend___lsb 3 -#define reg_strcop_rw_cfg___ipend___width 1 -#define reg_strcop_rw_cfg___ipend___bit 3 -#define reg_strcop_rw_cfg___ignore_sync___lsb 4 -#define reg_strcop_rw_cfg___ignore_sync___width 1 -#define reg_strcop_rw_cfg___ignore_sync___bit 4 -#define reg_strcop_rw_cfg___en___lsb 5 -#define reg_strcop_rw_cfg___en___width 1 -#define reg_strcop_rw_cfg___en___bit 5 -#define reg_strcop_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strcop_big 0x00000001 -#define regk_strcop_d 0x00000001 -#define regk_strcop_e 0x00000000 -#define regk_strcop_little 0x00000000 -#define regk_strcop_rw_cfg_default 0x00000002 -#endif /* __strcop_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h deleted file mode 100644 index 69b299920f71..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h +++ /dev/null @@ -1,100 +0,0 @@ -#ifndef __strmux_defs_asm_h -#define __strmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strmux, type rw */ -#define reg_strmux_rw_cfg___dma0___lsb 0 -#define reg_strmux_rw_cfg___dma0___width 3 -#define reg_strmux_rw_cfg___dma1___lsb 3 -#define reg_strmux_rw_cfg___dma1___width 3 -#define reg_strmux_rw_cfg___dma2___lsb 6 -#define reg_strmux_rw_cfg___dma2___width 3 -#define reg_strmux_rw_cfg___dma3___lsb 9 -#define reg_strmux_rw_cfg___dma3___width 3 -#define reg_strmux_rw_cfg___dma4___lsb 12 -#define reg_strmux_rw_cfg___dma4___width 3 -#define reg_strmux_rw_cfg___dma5___lsb 15 -#define reg_strmux_rw_cfg___dma5___width 3 -#define reg_strmux_rw_cfg___dma6___lsb 18 -#define reg_strmux_rw_cfg___dma6___width 3 -#define reg_strmux_rw_cfg___dma7___lsb 21 -#define reg_strmux_rw_cfg___dma7___width 3 -#define reg_strmux_rw_cfg___dma8___lsb 24 -#define reg_strmux_rw_cfg___dma8___width 3 -#define reg_strmux_rw_cfg___dma9___lsb 27 -#define reg_strmux_rw_cfg___dma9___width 3 -#define reg_strmux_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strmux_ata 0x00000003 -#define regk_strmux_eth0 0x00000001 -#define regk_strmux_eth1 0x00000004 -#define regk_strmux_ext0 0x00000001 -#define regk_strmux_ext1 0x00000001 -#define regk_strmux_ext2 0x00000001 -#define regk_strmux_ext3 0x00000001 -#define regk_strmux_iop0 0x00000002 -#define regk_strmux_iop1 0x00000001 -#define regk_strmux_off 0x00000000 -#define regk_strmux_p21 0x00000004 -#define regk_strmux_rw_cfg_default 0x00000000 -#define regk_strmux_ser0 0x00000002 -#define regk_strmux_ser1 0x00000002 -#define regk_strmux_ser2 0x00000004 -#define regk_strmux_ser3 0x00000003 -#define regk_strmux_sser0 0x00000003 -#define regk_strmux_sser1 0x00000003 -#define regk_strmux_strcop 0x00000002 -#endif /* __strmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 43146021fc16..000000000000 --- a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,229 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h deleted file mode 100644 index 43b6643ff0d3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/ata_defs.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef __ata_defs_h -#define __ata_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ata */ - -/* Register rw_ctrl0, scope ata, type rw */ -typedef struct { - unsigned int pio_hold : 6; - unsigned int pio_strb : 6; - unsigned int pio_setup : 6; - unsigned int dma_hold : 6; - unsigned int dma_strb : 6; - unsigned int rst : 1; - unsigned int en : 1; -} reg_ata_rw_ctrl0; -#define REG_RD_ADDR_ata_rw_ctrl0 12 -#define REG_WR_ADDR_ata_rw_ctrl0 12 - -/* Register rw_ctrl1, scope ata, type rw */ -typedef struct { - unsigned int udma_tcyc : 4; - unsigned int udma_tdvs : 4; - unsigned int dummy1 : 24; -} reg_ata_rw_ctrl1; -#define REG_RD_ADDR_ata_rw_ctrl1 16 -#define REG_WR_ADDR_ata_rw_ctrl1 16 - -/* Register rw_ctrl2, scope ata, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 3; - unsigned int dma_size : 1; - unsigned int multi : 1; - unsigned int hsh : 2; - unsigned int trf_mode : 1; - unsigned int rw : 1; - unsigned int addr : 3; - unsigned int cs0 : 1; - unsigned int cs1 : 1; - unsigned int sel : 2; -} reg_ata_rw_ctrl2; -#define REG_RD_ADDR_ata_rw_ctrl2 0 -#define REG_WR_ADDR_ata_rw_ctrl2 0 - -/* Register rs_stat_data, scope ata, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_rs_stat_data; -#define REG_RD_ADDR_ata_rs_stat_data 4 - -/* Register r_stat_data, scope ata, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_r_stat_data; -#define REG_RD_ADDR_ata_r_stat_data 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -typedef struct { - unsigned int cnt : 17; - unsigned int dummy1 : 15; -} reg_ata_rw_trf_cnt; -#define REG_RD_ADDR_ata_rw_trf_cnt 20 -#define REG_WR_ADDR_ata_rw_trf_cnt 20 - -/* Register r_stat_misc, scope ata, type r */ -typedef struct { - unsigned int crc : 16; - unsigned int dummy1 : 16; -} reg_ata_r_stat_misc; -#define REG_RD_ADDR_ata_r_stat_misc 24 - -/* Register rw_intr_mask, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_intr_mask; -#define REG_RD_ADDR_ata_rw_intr_mask 28 -#define REG_WR_ADDR_ata_rw_intr_mask 28 - -/* Register rw_ack_intr, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_ack_intr; -#define REG_RD_ADDR_ata_rw_ack_intr 32 -#define REG_WR_ADDR_ata_rw_ack_intr 32 - -/* Register r_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_intr; -#define REG_RD_ADDR_ata_r_intr 36 - -/* Register r_masked_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_masked_intr; -#define REG_RD_ADDR_ata_r_masked_intr 40 - - -/* Constants */ -enum { - regk_ata_active = 0x00000001, - regk_ata_byte = 0x00000001, - regk_ata_data = 0x00000001, - regk_ata_dma = 0x00000001, - regk_ata_inactive = 0x00000000, - regk_ata_no = 0x00000000, - regk_ata_nodata = 0x00000000, - regk_ata_pio = 0x00000000, - regk_ata_rd = 0x00000001, - regk_ata_reg = 0x00000000, - regk_ata_rw_ctrl0_default = 0x00000000, - regk_ata_rw_ctrl2_default = 0x00000000, - regk_ata_rw_intr_mask_default = 0x00000000, - regk_ata_udma = 0x00000002, - regk_ata_word = 0x00000000, - regk_ata_wr = 0x00000000, - regk_ata_yes = 0x00000001 -}; -#endif /* __ata_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h deleted file mode 100644 index a56608b50359..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h +++ /dev/null @@ -1,284 +0,0 @@ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h deleted file mode 100644 index b931c1aab679..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,473 +0,0 @@ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h deleted file mode 100644 index d18fc3c9f569..000000000000 --- a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h deleted file mode 100644 index 45457a4e3817..000000000000 --- a/include/asm-cris/arch-v32/hwregs/config_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/include/asm-cris/arch-v32/hwregs/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h deleted file mode 100644 index 3ce322b5c731..000000000000 --- a/include/asm-cris/arch-v32/hwregs/dma.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * DMA C definitions and help macros - * - */ - -#ifndef dma_h -#define dma_h - -/* registers */ /* Really needed, since both are listed in sw.list? */ -#include "dma_defs.h" - - -/* descriptors */ - -// ------------------------------------------------------------ dma_descr_group -typedef struct dma_descr_group { - struct dma_descr_group *next; - unsigned eol : 1; - unsigned tol : 1; - unsigned bol : 1; - unsigned : 1; - unsigned intr : 1; - unsigned : 2; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md : 16; - struct dma_descr_group *up; - union { - struct dma_descr_context *context; - struct dma_descr_group *group; - } down; -} dma_descr_group; - -// ---------------------------------------------------------- dma_descr_context -typedef struct dma_descr_context { - struct dma_descr_context *next; - unsigned eol : 1; - unsigned : 3; - unsigned intr : 1; - unsigned : 1; - unsigned store_mode : 1; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md0 : 16; - unsigned md1; - unsigned md2; - unsigned md3; - unsigned md4; - struct dma_descr_data *saved_data; - char *saved_data_buf; -} dma_descr_context; - -// ------------------------------------------------------------- dma_descr_data -typedef struct dma_descr_data { - struct dma_descr_data *next; - char *buf; - unsigned eol : 1; - unsigned : 2; - unsigned out_eop : 1; - unsigned intr : 1; - unsigned wait : 1; - unsigned : 2; - unsigned : 3; - unsigned in_eop : 1; - unsigned : 4; - unsigned md : 16; - char *after; -} dma_descr_data; - -// --------------------------------------------------------------------- macros - -// enable DMA channel -#define DMA_ENABLE( inst ) \ - do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ - e.en = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, e); } while( 0 ) - -// reset DMA channel -#define DMA_RESET( inst ) \ - do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ - r.en = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, r); } while( 0 ) - -// stop DMA channel -#define DMA_STOP( inst ) \ - do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ - s.stop = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, s); } while( 0 ) - -// continue DMA channel operation -#define DMA_CONTINUE( inst ) \ - do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ - c.stop = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, c); } while( 0 ) - -// give stream command -#define DMA_WR_CMD( inst, cmd_par ) \ - do { reg_dma_rw_stream_cmd __x = {0}; \ - do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ - __x.cmd = (cmd_par); \ - REG_WR(dma, inst, rw_stream_cmd, __x); \ - } while (0) - -// load: g,c,d:burst -#define DMA_START_GROUP( inst, group_descr ) \ - do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_g ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// load: c,d:burst -#define DMA_START_CONTEXT( inst, ctx_descr ) \ - do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// if the DMA is at the end of the data list, the last data descr is reloaded -#define DMA_CONTINUE_DATA( inst ) \ -do { reg_dma_rw_cmd c = {0}; \ - c.cont_data = regk_dma_yes;\ - REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h deleted file mode 100644 index 48ac8cef7ebe..000000000000 --- a/include/asm-cris/arch-v32/hwregs/dma_defs.h +++ /dev/null @@ -1,436 +0,0 @@ -#ifndef __dma_defs_h -#define __dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope dma */ - -/* Register rw_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data; -#define REG_RD_ADDR_dma_rw_data 0 -#define REG_WR_ADDR_dma_rw_data 0 - -/* Register rw_data_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_next; -#define REG_RD_ADDR_dma_rw_data_next 4 -#define REG_WR_ADDR_dma_rw_data_next 4 - -/* Register rw_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_buf; -#define REG_RD_ADDR_dma_rw_data_buf 8 -#define REG_WR_ADDR_dma_rw_data_buf 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 2; - unsigned int out_eop : 1; - unsigned int intr : 1; - unsigned int wait : 1; - unsigned int dummy2 : 26; -} reg_dma_rw_data_ctrl; -#define REG_RD_ADDR_dma_rw_data_ctrl 12 -#define REG_WR_ADDR_dma_rw_data_ctrl 12 - -/* Register rw_data_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 3; - unsigned int in_eop : 1; - unsigned int dummy2 : 28; -} reg_dma_rw_data_stat; -#define REG_RD_ADDR_dma_rw_data_stat 16 -#define REG_WR_ADDR_dma_rw_data_stat 16 - -/* Register rw_data_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md; -#define REG_RD_ADDR_dma_rw_data_md 20 -#define REG_WR_ADDR_dma_rw_data_md 20 - -/* Register rw_data_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md_s; -#define REG_RD_ADDR_dma_rw_data_md_s 24 -#define REG_WR_ADDR_dma_rw_data_md_s 24 - -/* Register rw_data_after, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_after; -#define REG_RD_ADDR_dma_rw_data_after 28 -#define REG_WR_ADDR_dma_rw_data_after 28 - -/* Register rw_ctxt, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt; -#define REG_RD_ADDR_dma_rw_ctxt 32 -#define REG_WR_ADDR_dma_rw_ctxt 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_next; -#define REG_RD_ADDR_dma_rw_ctxt_next 36 -#define REG_WR_ADDR_dma_rw_ctxt_next 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 3; - unsigned int intr : 1; - unsigned int dummy2 : 1; - unsigned int store_mode : 1; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_ctxt_ctrl; -#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 -#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_ctxt_stat; -#define REG_RD_ADDR_dma_rw_ctxt_stat 44 -#define REG_WR_ADDR_dma_rw_ctxt_stat 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -typedef struct { - unsigned int md0 : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0; -#define REG_RD_ADDR_dma_rw_ctxt_md0 48 -#define REG_WR_ADDR_dma_rw_ctxt_md0 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -typedef struct { - unsigned int md0_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0_s; -#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 -#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1; -#define REG_RD_ADDR_dma_rw_ctxt_md1 56 -#define REG_WR_ADDR_dma_rw_ctxt_md1 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1_s; -#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 -#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2; -#define REG_RD_ADDR_dma_rw_ctxt_md2 64 -#define REG_WR_ADDR_dma_rw_ctxt_md2 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2_s; -#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 -#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3; -#define REG_RD_ADDR_dma_rw_ctxt_md3 72 -#define REG_WR_ADDR_dma_rw_ctxt_md3 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3_s; -#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 -#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4; -#define REG_RD_ADDR_dma_rw_ctxt_md4 80 -#define REG_WR_ADDR_dma_rw_ctxt_md4 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4_s; -#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 -#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 - -/* Register rw_saved_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data; -#define REG_RD_ADDR_dma_rw_saved_data 88 -#define REG_WR_ADDR_dma_rw_saved_data 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data_buf; -#define REG_RD_ADDR_dma_rw_saved_data_buf 92 -#define REG_WR_ADDR_dma_rw_saved_data_buf 92 - -/* Register rw_group, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group; -#define REG_RD_ADDR_dma_rw_group 96 -#define REG_WR_ADDR_dma_rw_group 96 - -/* Register rw_group_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_next; -#define REG_RD_ADDR_dma_rw_group_next 100 -#define REG_WR_ADDR_dma_rw_group_next 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int tol : 1; - unsigned int bol : 1; - unsigned int dummy1 : 1; - unsigned int intr : 1; - unsigned int dummy2 : 2; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_group_ctrl; -#define REG_RD_ADDR_dma_rw_group_ctrl 104 -#define REG_WR_ADDR_dma_rw_group_ctrl 104 - -/* Register rw_group_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_group_stat; -#define REG_RD_ADDR_dma_rw_group_stat 108 -#define REG_WR_ADDR_dma_rw_group_stat 108 - -/* Register rw_group_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md; -#define REG_RD_ADDR_dma_rw_group_md 112 -#define REG_WR_ADDR_dma_rw_group_md 112 - -/* Register rw_group_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md_s; -#define REG_RD_ADDR_dma_rw_group_md_s 116 -#define REG_WR_ADDR_dma_rw_group_md_s 116 - -/* Register rw_group_up, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_up; -#define REG_RD_ADDR_dma_rw_group_up 120 -#define REG_WR_ADDR_dma_rw_group_up 120 - -/* Register rw_group_down, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_down; -#define REG_RD_ADDR_dma_rw_group_down 124 -#define REG_WR_ADDR_dma_rw_group_down 124 - -/* Register rw_cmd, scope dma, type rw */ -typedef struct { - unsigned int cont_data : 1; - unsigned int dummy1 : 31; -} reg_dma_rw_cmd; -#define REG_RD_ADDR_dma_rw_cmd 128 -#define REG_WR_ADDR_dma_rw_cmd 128 - -/* Register rw_cfg, scope dma, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int stop : 1; - unsigned int dummy1 : 30; -} reg_dma_rw_cfg; -#define REG_RD_ADDR_dma_rw_cfg 132 -#define REG_WR_ADDR_dma_rw_cfg 132 - -/* Register rw_stat, scope dma, type rw */ -typedef struct { - unsigned int mode : 5; - unsigned int list_state : 3; - unsigned int stream_cmd_src : 8; - unsigned int dummy1 : 8; - unsigned int buf : 8; -} reg_dma_rw_stat; -#define REG_RD_ADDR_dma_rw_stat 136 -#define REG_WR_ADDR_dma_rw_stat 136 - -/* Register rw_intr_mask, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_intr_mask; -#define REG_RD_ADDR_dma_rw_intr_mask 140 -#define REG_WR_ADDR_dma_rw_intr_mask 140 - -/* Register rw_ack_intr, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_ack_intr; -#define REG_RD_ADDR_dma_rw_ack_intr 144 -#define REG_WR_ADDR_dma_rw_ack_intr 144 - -/* Register r_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_intr; -#define REG_RD_ADDR_dma_r_intr 148 - -/* Register r_masked_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_masked_intr; -#define REG_RD_ADDR_dma_r_masked_intr 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 7; - unsigned int busy : 1; -} reg_dma_rw_stream_cmd; -#define REG_RD_ADDR_dma_rw_stream_cmd 156 -#define REG_WR_ADDR_dma_rw_stream_cmd 156 - - -/* Constants */ -enum { - regk_dma_ack_pkt = 0x00000100, - regk_dma_anytime = 0x00000001, - regk_dma_array = 0x00000008, - regk_dma_burst = 0x00000020, - regk_dma_client = 0x00000002, - regk_dma_copy_next = 0x00000010, - regk_dma_copy_up = 0x00000020, - regk_dma_data_at_eol = 0x00000001, - regk_dma_dis_c = 0x00000010, - regk_dma_dis_g = 0x00000020, - regk_dma_idle = 0x00000001, - regk_dma_intern = 0x00000004, - regk_dma_load_c = 0x00000200, - regk_dma_load_c_n = 0x00000280, - regk_dma_load_c_next = 0x00000240, - regk_dma_load_d = 0x00000140, - regk_dma_load_g = 0x00000300, - regk_dma_load_g_down = 0x000003c0, - regk_dma_load_g_next = 0x00000340, - regk_dma_load_g_up = 0x00000380, - regk_dma_next_en = 0x00000010, - regk_dma_next_pkt = 0x00000010, - regk_dma_no = 0x00000000, - regk_dma_only_at_wait = 0x00000000, - regk_dma_restore = 0x00000020, - regk_dma_rst = 0x00000001, - regk_dma_running = 0x00000004, - regk_dma_rw_cfg_default = 0x00000000, - regk_dma_rw_cmd_default = 0x00000000, - regk_dma_rw_intr_mask_default = 0x00000000, - regk_dma_rw_stat_default = 0x00000101, - regk_dma_rw_stream_cmd_default = 0x00000000, - regk_dma_save_down = 0x00000020, - regk_dma_save_up = 0x00000020, - regk_dma_set_reg = 0x00000050, - regk_dma_set_w_size1 = 0x00000190, - regk_dma_set_w_size2 = 0x000001a0, - regk_dma_set_w_size4 = 0x000001c0, - regk_dma_stopped = 0x00000002, - regk_dma_store_c = 0x00000002, - regk_dma_store_descr = 0x00000000, - regk_dma_store_g = 0x00000004, - regk_dma_store_md = 0x00000001, - regk_dma_sw = 0x00000008, - regk_dma_update_down = 0x00000020, - regk_dma_yes = 0x00000001 -}; -#endif /* __dma_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h deleted file mode 100644 index 90fe8a28894f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ /dev/null @@ -1,378 +0,0 @@ -#ifndef __eth_defs_h -#define __eth_defs_h - -/* - * This file is autogenerated from - * file: eth.r - * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp - * last modfied: Mon Jan 9 06:06:41 2006 - * - * by /n/asic/design/tools/rdesc/rdes2c eth.r - * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope eth */ - -/* Register rw_ma0_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma0_lo; -#define REG_RD_ADDR_eth_rw_ma0_lo 0 -#define REG_WR_ADDR_eth_rw_ma0_lo 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma0_hi; -#define REG_RD_ADDR_eth_rw_ma0_hi 4 -#define REG_WR_ADDR_eth_rw_ma0_hi 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma1_lo; -#define REG_RD_ADDR_eth_rw_ma1_lo 8 -#define REG_WR_ADDR_eth_rw_ma1_lo 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma1_hi; -#define REG_RD_ADDR_eth_rw_ma1_hi 12 -#define REG_WR_ADDR_eth_rw_ma1_hi 12 - -/* Register rw_ga_lo, scope eth, type rw */ -typedef struct { - unsigned int tbl : 32; -} reg_eth_rw_ga_lo; -#define REG_RD_ADDR_eth_rw_ga_lo 16 -#define REG_WR_ADDR_eth_rw_ga_lo 16 - -/* Register rw_ga_hi, scope eth, type rw */ -typedef struct { - unsigned int tbl : 32; -} reg_eth_rw_ga_hi; -#define REG_RD_ADDR_eth_rw_ga_hi 20 -#define REG_WR_ADDR_eth_rw_ga_hi 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int phy : 2; - unsigned int protocol : 1; - unsigned int loopback : 1; - unsigned int flow_ctrl : 1; - unsigned int gtxclk_out : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 24; -} reg_eth_rw_gen_ctrl; -#define REG_RD_ADDR_eth_rw_gen_ctrl 24 -#define REG_WR_ADDR_eth_rw_gen_ctrl 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -typedef struct { - unsigned int ma0 : 1; - unsigned int ma1 : 1; - unsigned int individual : 1; - unsigned int broadcast : 1; - unsigned int undersize : 1; - unsigned int oversize : 1; - unsigned int bad_crc : 1; - unsigned int duplex : 1; - unsigned int max_size : 16; - unsigned int dummy1 : 8; -} reg_eth_rw_rec_ctrl; -#define REG_RD_ADDR_eth_rw_rec_ctrl 28 -#define REG_WR_ADDR_eth_rw_rec_ctrl 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int pad : 1; - unsigned int retry : 1; - unsigned int ignore_col : 1; - unsigned int cancel : 1; - unsigned int hsh_delay : 1; - unsigned int ignore_crs : 1; - unsigned int carrier_ext : 1; - unsigned int dummy1 : 24; -} reg_eth_rw_tr_ctrl; -#define REG_RD_ADDR_eth_rw_tr_ctrl 32 -#define REG_WR_ADDR_eth_rw_tr_ctrl 32 - -/* Register rw_clr_err, scope eth, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_eth_rw_clr_err; -#define REG_RD_ADDR_eth_rw_clr_err 36 -#define REG_WR_ADDR_eth_rw_clr_err 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -typedef struct { - unsigned int mdio : 1; - unsigned int mdoe : 1; - unsigned int mdc : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_mgm_ctrl; -#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 -#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 - -/* Register r_stat, scope eth, type r */ -typedef struct { - unsigned int mdio : 1; - unsigned int exc_col : 1; - unsigned int urun : 1; - unsigned int clk_125 : 1; - unsigned int dummy1 : 28; -} reg_eth_r_stat; -#define REG_RD_ADDR_eth_r_stat 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_rs_rec_cnt; -#define REG_RD_ADDR_eth_rs_rec_cnt 48 - -/* Register r_rec_cnt, scope eth, type r */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_r_rec_cnt; -#define REG_RD_ADDR_eth_r_rec_cnt 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_rs_tr_cnt; -#define REG_RD_ADDR_eth_rs_tr_cnt 56 - -/* Register r_tr_cnt, scope eth, type r */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_r_tr_cnt; -#define REG_RD_ADDR_eth_r_tr_cnt 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_rs_phy_cnt; -#define REG_RD_ADDR_eth_rs_phy_cnt 64 - -/* Register r_phy_cnt, scope eth, type r */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_r_phy_cnt; -#define REG_RD_ADDR_eth_r_phy_cnt 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -typedef struct { - unsigned int snmp_inc : 1; - unsigned int snmp : 1; - unsigned int backoff : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_test_ctrl; -#define REG_RD_ADDR_eth_rw_test_ctrl 72 -#define REG_WR_ADDR_eth_rw_test_ctrl 72 - -/* Register rw_intr_mask, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_intr_mask; -#define REG_RD_ADDR_eth_rw_intr_mask 76 -#define REG_WR_ADDR_eth_rw_intr_mask 76 - -/* Register rw_ack_intr, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_ack_intr; -#define REG_RD_ADDR_eth_rw_ack_intr 80 -#define REG_WR_ADDR_eth_rw_ack_intr 80 - -/* Register r_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_intr; -#define REG_RD_ADDR_eth_r_intr 84 - -/* Register r_masked_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_masked_intr; -#define REG_RD_ADDR_eth_r_masked_intr 88 - - -/* Constants */ -enum { - regk_eth_discard = 0x00000000, - regk_eth_ether = 0x00000000, - regk_eth_full = 0x00000001, - regk_eth_gmii = 0x00000003, - regk_eth_gtxclk = 0x00000001, - regk_eth_half = 0x00000000, - regk_eth_hsh = 0x00000001, - regk_eth_mii = 0x00000001, - regk_eth_mii_arec = 0x00000002, - regk_eth_mii_clk = 0x00000000, - regk_eth_no = 0x00000000, - regk_eth_phyrst = 0x00000000, - regk_eth_rec = 0x00000001, - regk_eth_rw_ga_hi_default = 0x00000000, - regk_eth_rw_ga_lo_default = 0x00000000, - regk_eth_rw_gen_ctrl_default = 0x00000000, - regk_eth_rw_intr_mask_default = 0x00000000, - regk_eth_rw_ma0_hi_default = 0x00000000, - regk_eth_rw_ma0_lo_default = 0x00000000, - regk_eth_rw_ma1_hi_default = 0x00000000, - regk_eth_rw_ma1_lo_default = 0x00000000, - regk_eth_rw_mgm_ctrl_default = 0x00000000, - regk_eth_rw_test_ctrl_default = 0x00000000, - regk_eth_size1518 = 0x000005ee, - regk_eth_size1522 = 0x000005f2, - regk_eth_yes = 0x00000001 -}; -#endif /* __eth_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h deleted file mode 100644 index c47b5ca48ece..000000000000 --- a/include/asm-cris/arch-v32/hwregs/extmem_defs.h +++ /dev/null @@ -1,369 +0,0 @@ -#ifndef __extmem_defs_h -#define __extmem_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ext_mem/mod/extmem_regs.r - * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp - * last modfied: Tue Mar 30 22:26:21 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r - * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope extmem */ - -/* Register rw_cse0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse0_cfg; -#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 -#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 - -/* Register rw_cse1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse1_cfg; -#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 -#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 - -/* Register rw_csr0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr0_cfg; -#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 -#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 - -/* Register rw_csr1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr1_cfg; -#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 -#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 - -/* Register rw_csp0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp0_cfg; -#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 -#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 - -/* Register rw_csp1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp1_cfg; -#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 -#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 - -/* Register rw_csp2_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp2_cfg; -#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 -#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 - -/* Register rw_csp3_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp3_cfg; -#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 -#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 - -/* Register rw_csp4_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp4_cfg; -#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 -#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 - -/* Register rw_csp5_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp5_cfg; -#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 -#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 - -/* Register rw_csp6_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp6_cfg; -#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 -#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 - -/* Register rw_css_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_css_cfg; -#define REG_RD_ADDR_extmem_rw_css_cfg 44 -#define REG_WR_ADDR_extmem_rw_css_cfg 44 - -/* Register rw_status_handle, scope extmem, type rw */ -typedef struct { - unsigned int h : 32; -} reg_extmem_rw_status_handle; -#define REG_RD_ADDR_extmem_rw_status_handle 48 -#define REG_WR_ADDR_extmem_rw_status_handle 48 - -/* Register rw_wait_pin, scope extmem, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 15; - unsigned int start : 1; -} reg_extmem_rw_wait_pin; -#define REG_RD_ADDR_extmem_rw_wait_pin 52 -#define REG_WR_ADDR_extmem_rw_wait_pin 52 - -/* Register rw_gated_csp, scope extmem, type rw */ -typedef struct { - unsigned int dummy1 : 31; - unsigned int en : 1; -} reg_extmem_rw_gated_csp; -#define REG_RD_ADDR_extmem_rw_gated_csp 56 -#define REG_WR_ADDR_extmem_rw_gated_csp 56 - - -/* Constants */ -enum { - regk_extmem_b16 = 0x00000001, - regk_extmem_b32 = 0x00000000, - regk_extmem_bwe = 0x00000000, - regk_extmem_cwe = 0x00000001, - regk_extmem_no = 0x00000000, - regk_extmem_rw_cse0_cfg_default = 0x000006cf, - regk_extmem_rw_cse1_cfg_default = 0x000006cf, - regk_extmem_rw_csp0_cfg_default = 0x000006cf, - regk_extmem_rw_csp1_cfg_default = 0x000006cf, - regk_extmem_rw_csp2_cfg_default = 0x000006cf, - regk_extmem_rw_csp3_cfg_default = 0x000006cf, - regk_extmem_rw_csp4_cfg_default = 0x000006cf, - regk_extmem_rw_csp5_cfg_default = 0x000006cf, - regk_extmem_rw_csp6_cfg_default = 0x000006cf, - regk_extmem_rw_csr0_cfg_default = 0x000006cf, - regk_extmem_rw_csr1_cfg_default = 0x000006cf, - regk_extmem_rw_css_cfg_default = 0x000006cf, - regk_extmem_s128KB = 0x00000000, - regk_extmem_s16MB = 0x00000005, - regk_extmem_s1MB = 0x00000001, - regk_extmem_s2MB = 0x00000002, - regk_extmem_s32MB = 0x00000006, - regk_extmem_s4MB = 0x00000003, - regk_extmem_s64MB = 0x00000007, - regk_extmem_s8MB = 0x00000004, - regk_extmem_yes = 0x00000001 -}; -#endif /* __extmem_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h deleted file mode 100644 index 3e9a0b25366f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/gio_defs.h +++ /dev/null @@ -1,295 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h deleted file mode 100644 index 5c1b28fb205d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/intr_vect.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile deleted file mode 100644 index a90056a095e3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/Makefile +++ /dev/null @@ -1,146 +0,0 @@ -# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The offical place for these files is probably at: -RELEASE ?= r1_alfa5 -IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -IOPROCDIR = /n/asic/design/io/io_proc/rtl - -IOPROCINCL_FILES = -IOPROCINCL_FILES2= -IOPROCINCL_FILES += iop_crc_par_defs.h -IOPROCINCL_FILES += iop_dmc_in_defs.h -IOPROCINCL_FILES += iop_dmc_out_defs.h -IOPROCINCL_FILES += iop_fifo_in_defs.h -IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h -IOPROCINCL_FILES += iop_fifo_out_defs.h -IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h -IOPROCINCL_FILES += iop_mpu_defs.h -IOPROCINCL_FILES2+= iop_mpu_macros.h -IOPROCINCL_FILES2+= iop_reg_space.h -IOPROCINCL_FILES += iop_sap_in_defs.h -IOPROCINCL_FILES += iop_sap_out_defs.h -IOPROCINCL_FILES += iop_scrc_in_defs.h -IOPROCINCL_FILES += iop_scrc_out_defs.h -IOPROCINCL_FILES += iop_spu_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_sw_cfg_defs.h -IOPROCINCL_FILES += iop_sw_cpu_defs.h -IOPROCINCL_FILES += iop_sw_mpu_defs.h -IOPROCINCL_FILES += iop_sw_spu_defs.h -# -IOPROCINCL_FILES += iop_timer_grp_defs.h -IOPROCINCL_FILES += iop_trigger_grp_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_version_defs.h - -IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) -IOPROCASMINCL_FILES+= iop_reg_space_asm.h - - -IOPROCREGDESC = -IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r -#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r -IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r - - -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) - echo "INCL: $(IOPROCINCL_FILES)" - echo "INCL2: $(IOPROCINCL_FILES2)" - echo "ASMINCL: $(IOPROCASMINCL_FILES)" - -# From the official location... -iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -## copy - Copy files from official location -copy: - @echo "## Copying and fixing iop files ##" - @for HFILE in $(IOPROCINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(IOPROCINCL_FILES2); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @echo "## Copying and fixing iop asm files ##" - @for HFILE in $(IOPROCASMINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ - done - -# I/O processor files: -## iop - Generate I/O processor include files -iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) -iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r - $(RDES2C) $< -iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) $< -%_defs.h: $(IOPROCDIR)/%.r - $(RDES2C) $< -%_defs_asm.h: $(IOPROCDIR)/%.r - $(RDES2C) -asm $< -iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) -asm $< - -## doc - Generate .axw files from register description. -doc: $(IOPROCREGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming of .r files. -%.axw: axw - @for RDES in $(IOPROCREGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(IOPROCINCL_FILES) *.axw - -.PHONY: cleandoc -## cleandoc - Remove .axw files. -cleandoc: - rm -rf *.axw - diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h deleted file mode 100644 index a4b58000c164..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h +++ /dev/null @@ -1,171 +0,0 @@ -#ifndef __iop_crc_par_defs_asm_h -#define __iop_crc_par_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_cfg___mode___lsb 0 -#define reg_iop_crc_par_rw_cfg___mode___width 1 -#define reg_iop_crc_par_rw_cfg___mode___bit 0 -#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 -#define reg_iop_crc_par_rw_cfg___crc_out___width 1 -#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 -#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 -#define reg_iop_crc_par_rw_cfg___rev_out___width 1 -#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 -#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 -#define reg_iop_crc_par_rw_cfg___inv_out___width 1 -#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 -#define reg_iop_crc_par_rw_cfg___trig___lsb 4 -#define reg_iop_crc_par_rw_cfg___trig___width 2 -#define reg_iop_crc_par_rw_cfg___poly___lsb 6 -#define reg_iop_crc_par_rw_cfg___poly___width 3 -#define reg_iop_crc_par_rw_cfg_offset 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_init_crc_offset 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_correct_crc_offset 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_ctrl___en___lsb 0 -#define reg_iop_crc_par_rw_ctrl___en___width 1 -#define reg_iop_crc_par_rw_ctrl___en___bit 0 -#define reg_iop_crc_par_rw_ctrl_offset 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 -#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 -#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 -#define reg_iop_crc_par_rw_set_last_offset 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_offset 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_offset 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_offset 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_offset 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_last_offset 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_last_offset 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_last_offset 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_last_offset 48 - -/* Register r_stat, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_stat___err___lsb 0 -#define reg_iop_crc_par_r_stat___err___width 1 -#define reg_iop_crc_par_r_stat___err___bit 0 -#define reg_iop_crc_par_r_stat___busy___lsb 1 -#define reg_iop_crc_par_r_stat___busy___width 1 -#define reg_iop_crc_par_r_stat___busy___bit 1 -#define reg_iop_crc_par_r_stat_offset 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_sh_reg_offset 56 - -/* Register r_crc, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_crc_offset 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 -#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 - - -/* Constants */ -#define regk_iop_crc_par_calc 0x00000001 -#define regk_iop_crc_par_ccitt 0x00000002 -#define regk_iop_crc_par_check 0x00000000 -#define regk_iop_crc_par_crc16 0x00000001 -#define regk_iop_crc_par_crc32 0x00000000 -#define regk_iop_crc_par_crc5 0x00000003 -#define regk_iop_crc_par_crc5_11 0x00000004 -#define regk_iop_crc_par_dif_in 0x00000002 -#define regk_iop_crc_par_hi 0x00000000 -#define regk_iop_crc_par_neg 0x00000002 -#define regk_iop_crc_par_no 0x00000000 -#define regk_iop_crc_par_pos 0x00000001 -#define regk_iop_crc_par_pos_neg 0x00000003 -#define regk_iop_crc_par_rw_cfg_default 0x00000000 -#define regk_iop_crc_par_rw_ctrl_default 0x00000000 -#define regk_iop_crc_par_yes 0x00000001 -#endif /* __iop_crc_par_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h deleted file mode 100644 index e7d539feccb1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef __iop_dmc_in_defs_asm_h -#define __iop_dmc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 -#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 -#define reg_iop_dmc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 -#define reg_iop_dmc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_in_r_stat___dif_en___width 1 -#define reg_iop_dmc_in_r_stat___dif_en___bit 0 -#define reg_iop_dmc_in_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_in_rw_stream_cmd_offset 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 -#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 -#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 -#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 -#define reg_iop_dmc_in_r_stream_stat___sth___width 7 -#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 -#define reg_iop_dmc_in_r_stream_stat___full___width 1 -#define reg_iop_dmc_in_r_stream_stat___full___bit 16 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 -#define reg_iop_dmc_in_r_stream_stat_offset 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_data_descr___stat___width 8 -#define reg_iop_dmc_in_r_data_descr___md___lsb 16 -#define reg_iop_dmc_in_r_data_descr___md___width 16 -#define reg_iop_dmc_in_r_data_descr_offset 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_r_ctxt_descr_offset 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_group_descr___stat___width 8 -#define reg_iop_dmc_in_r_group_descr___md___lsb 16 -#define reg_iop_dmc_in_r_group_descr___md___width 16 -#define reg_iop_dmc_in_r_group_descr_offset 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_data_descr___md___width 16 -#define reg_iop_dmc_in_rw_data_descr_offset 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_group_descr___md___width 16 -#define reg_iop_dmc_in_rw_group_descr_offset 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 -#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 -#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 -#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 -#define reg_iop_dmc_in_rw_intr_mask___full___width 1 -#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 -#define reg_iop_dmc_in_rw_intr_mask_offset 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 -#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 -#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 -#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 -#define reg_iop_dmc_in_rw_ack_intr___full___width 1 -#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 -#define reg_iop_dmc_in_rw_ack_intr_offset 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_intr___data_md___width 1 -#define reg_iop_dmc_in_r_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_intr___group_md___width 1 -#define reg_iop_dmc_in_r_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_intr___sth___width 1 -#define reg_iop_dmc_in_r_intr___sth___bit 4 -#define reg_iop_dmc_in_r_intr___full___lsb 5 -#define reg_iop_dmc_in_r_intr___full___width 1 -#define reg_iop_dmc_in_r_intr___full___bit 5 -#define reg_iop_dmc_in_r_intr_offset 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_masked_intr___sth___width 1 -#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 -#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 -#define reg_iop_dmc_in_r_masked_intr___full___width 1 -#define reg_iop_dmc_in_r_masked_intr___full___bit 5 -#define reg_iop_dmc_in_r_masked_intr_offset 100 - - -/* Constants */ -#define regk_iop_dmc_in_ack_pkt 0x00000100 -#define regk_iop_dmc_in_array 0x00000008 -#define regk_iop_dmc_in_burst 0x00000020 -#define regk_iop_dmc_in_copy_next 0x00000010 -#define regk_iop_dmc_in_copy_up 0x00000020 -#define regk_iop_dmc_in_dis_c 0x00000010 -#define regk_iop_dmc_in_dis_g 0x00000020 -#define regk_iop_dmc_in_lim1 0x00000000 -#define regk_iop_dmc_in_lim16 0x00000004 -#define regk_iop_dmc_in_lim2 0x00000001 -#define regk_iop_dmc_in_lim32 0x00000005 -#define regk_iop_dmc_in_lim4 0x00000002 -#define regk_iop_dmc_in_lim64 0x00000006 -#define regk_iop_dmc_in_lim8 0x00000003 -#define regk_iop_dmc_in_load_c 0x00000200 -#define regk_iop_dmc_in_load_c_n 0x00000280 -#define regk_iop_dmc_in_load_c_next 0x00000240 -#define regk_iop_dmc_in_load_d 0x00000140 -#define regk_iop_dmc_in_load_g 0x00000300 -#define regk_iop_dmc_in_load_g_down 0x000003c0 -#define regk_iop_dmc_in_load_g_next 0x00000340 -#define regk_iop_dmc_in_load_g_up 0x00000380 -#define regk_iop_dmc_in_next_en 0x00000010 -#define regk_iop_dmc_in_next_pkt 0x00000010 -#define regk_iop_dmc_in_no 0x00000000 -#define regk_iop_dmc_in_restore 0x00000020 -#define regk_iop_dmc_in_rw_cfg_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 -#define regk_iop_dmc_in_save_down 0x00000020 -#define regk_iop_dmc_in_save_up 0x00000020 -#define regk_iop_dmc_in_set_reg 0x00000050 -#define regk_iop_dmc_in_set_w_size1 0x00000190 -#define regk_iop_dmc_in_set_w_size2 0x000001a0 -#define regk_iop_dmc_in_set_w_size4 0x000001c0 -#define regk_iop_dmc_in_store_c 0x00000002 -#define regk_iop_dmc_in_store_descr 0x00000000 -#define regk_iop_dmc_in_store_g 0x00000004 -#define regk_iop_dmc_in_store_md 0x00000001 -#define regk_iop_dmc_in_update_down 0x00000020 -#define regk_iop_dmc_in_yes 0x00000001 -#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h deleted file mode 100644 index 9fe1a8054371..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h +++ /dev/null @@ -1,349 +0,0 @@ -#ifndef __iop_dmc_out_defs_asm_h -#define __iop_dmc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 -#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 -#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 -#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 -#define reg_iop_dmc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_out_r_stat___dif_en___width 1 -#define reg_iop_dmc_out_r_stat___dif_en___bit 0 -#define reg_iop_dmc_out_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_out_rw_stream_cmd_offset 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -#define reg_iop_dmc_out_rs_stream_data_offset 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_data_offset 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 -#define reg_iop_dmc_out_r_stream_stat___dth___width 7 -#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 -#define reg_iop_dmc_out_r_stream_stat___dv___width 1 -#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 -#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 -#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 -#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 -#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 -#define reg_iop_dmc_out_r_stream_stat___last___width 1 -#define reg_iop_dmc_out_r_stream_stat___last___bit 18 -#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 -#define reg_iop_dmc_out_r_stream_stat___size___width 3 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 -#define reg_iop_dmc_out_r_stream_stat_offset 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_data_descr___stat___width 8 -#define reg_iop_dmc_out_r_data_descr___md___lsb 16 -#define reg_iop_dmc_out_r_data_descr___md___width 16 -#define reg_iop_dmc_out_r_data_descr_offset 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_r_ctxt_descr_offset 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_group_descr___stat___width 8 -#define reg_iop_dmc_out_r_group_descr___md___lsb 16 -#define reg_iop_dmc_out_r_group_descr___md___width 16 -#define reg_iop_dmc_out_r_group_descr_offset 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_data_descr___md___width 16 -#define reg_iop_dmc_out_rw_data_descr_offset 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_group_descr___md___width 16 -#define reg_iop_dmc_out_rw_group_descr_offset 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 -#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 -#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 -#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 -#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 -#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 -#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_intr_mask_offset 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 -#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 -#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 -#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 -#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 -#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 -#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_ack_intr_offset 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_intr___data_md___width 1 -#define reg_iop_dmc_out_r_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_intr___group_md___width 1 -#define reg_iop_dmc_out_r_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_intr___dth___width 1 -#define reg_iop_dmc_out_r_intr___dth___bit 4 -#define reg_iop_dmc_out_r_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_intr___dv___width 1 -#define reg_iop_dmc_out_r_intr___dv___bit 5 -#define reg_iop_dmc_out_r_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_intr___last_data___width 1 -#define reg_iop_dmc_out_r_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_intr_offset 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_masked_intr___dth___width 1 -#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 -#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_masked_intr___dv___width 1 -#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 -#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 -#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_masked_intr_offset 96 - - -/* Constants */ -#define regk_iop_dmc_out_ack_pkt 0x00000100 -#define regk_iop_dmc_out_array 0x00000008 -#define regk_iop_dmc_out_burst 0x00000020 -#define regk_iop_dmc_out_copy_next 0x00000010 -#define regk_iop_dmc_out_copy_up 0x00000020 -#define regk_iop_dmc_out_dis_c 0x00000010 -#define regk_iop_dmc_out_dis_g 0x00000020 -#define regk_iop_dmc_out_lim1 0x00000000 -#define regk_iop_dmc_out_lim16 0x00000004 -#define regk_iop_dmc_out_lim2 0x00000001 -#define regk_iop_dmc_out_lim32 0x00000005 -#define regk_iop_dmc_out_lim4 0x00000002 -#define regk_iop_dmc_out_lim64 0x00000006 -#define regk_iop_dmc_out_lim8 0x00000003 -#define regk_iop_dmc_out_load_c 0x00000200 -#define regk_iop_dmc_out_load_c_n 0x00000280 -#define regk_iop_dmc_out_load_c_next 0x00000240 -#define regk_iop_dmc_out_load_d 0x00000140 -#define regk_iop_dmc_out_load_g 0x00000300 -#define regk_iop_dmc_out_load_g_down 0x000003c0 -#define regk_iop_dmc_out_load_g_next 0x00000340 -#define regk_iop_dmc_out_load_g_up 0x00000380 -#define regk_iop_dmc_out_next_en 0x00000010 -#define regk_iop_dmc_out_next_pkt 0x00000010 -#define regk_iop_dmc_out_no 0x00000000 -#define regk_iop_dmc_out_restore 0x00000020 -#define regk_iop_dmc_out_rw_cfg_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_out_save_down 0x00000020 -#define regk_iop_dmc_out_save_up 0x00000020 -#define regk_iop_dmc_out_set_reg 0x00000050 -#define regk_iop_dmc_out_set_w_size1 0x00000190 -#define regk_iop_dmc_out_set_w_size2 0x000001a0 -#define regk_iop_dmc_out_set_w_size4 0x000001c0 -#define regk_iop_dmc_out_store_c 0x00000002 -#define regk_iop_dmc_out_store_descr 0x00000000 -#define regk_iop_dmc_out_store_g 0x00000004 -#define regk_iop_dmc_out_store_md 0x00000001 -#define regk_iop_dmc_out_update_down 0x00000020 -#define regk_iop_dmc_out_yes 0x00000001 -#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h deleted file mode 100644 index 974dee082f9f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h +++ /dev/null @@ -1,234 +0,0 @@ -#ifndef __iop_fifo_in_defs_asm_h -#define __iop_fifo_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 -#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_in_rw_cfg___trig___width 2 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_in_rw_cfg___mode___width 2 -#define reg_iop_fifo_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_r_stat___last___lsb 4 -#define reg_iop_fifo_in_r_stat___last___width 8 -#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_r_stat_offset 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd1byte___data___width 8 -#define reg_iop_fifo_in_rs_rd1byte_offset 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd1byte___data___width 8 -#define reg_iop_fifo_in_r_rd1byte_offset 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd2byte___data___width 16 -#define reg_iop_fifo_in_rs_rd2byte_offset 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd2byte___data___width 16 -#define reg_iop_fifo_in_r_rd2byte_offset 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd3byte___data___width 24 -#define reg_iop_fifo_in_rs_rd3byte_offset 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd3byte___data___width 24 -#define reg_iop_fifo_in_r_rd3byte_offset 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd4byte___data___width 32 -#define reg_iop_fifo_in_rs_rd4byte_offset 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd4byte___data___width 32 -#define reg_iop_fifo_in_r_rd4byte_offset 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_set_last_offset 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_rw_intr_mask_offset 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_rw_ack_intr_offset 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_intr___urun___width 1 -#define reg_iop_fifo_in_r_intr___urun___bit 0 -#define reg_iop_fifo_in_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_intr___last_data___width 1 -#define reg_iop_fifo_in_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_intr___dav___width 1 -#define reg_iop_fifo_in_r_intr___dav___bit 2 -#define reg_iop_fifo_in_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_intr___avail___width 1 -#define reg_iop_fifo_in_r_intr___avail___bit 3 -#define reg_iop_fifo_in_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_intr___orun___width 1 -#define reg_iop_fifo_in_r_intr___orun___bit 4 -#define reg_iop_fifo_in_r_intr_offset 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_r_masked_intr_offset 64 - - -/* Constants */ -#define regk_iop_fifo_in_dif_in 0x00000002 -#define regk_iop_fifo_in_hi 0x00000000 -#define regk_iop_fifo_in_neg 0x00000002 -#define regk_iop_fifo_in_no 0x00000000 -#define regk_iop_fifo_in_order16 0x00000001 -#define regk_iop_fifo_in_order24 0x00000002 -#define regk_iop_fifo_in_order32 0x00000003 -#define regk_iop_fifo_in_order8 0x00000000 -#define regk_iop_fifo_in_pos 0x00000001 -#define regk_iop_fifo_in_pos_neg 0x00000003 -#define regk_iop_fifo_in_rw_cfg_default 0x00000024 -#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_rw_set_last_default 0x00000000 -#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 -#define regk_iop_fifo_in_size16 0x00000002 -#define regk_iop_fifo_in_size24 0x00000001 -#define regk_iop_fifo_in_size32 0x00000000 -#define regk_iop_fifo_in_size8 0x00000003 -#define regk_iop_fifo_in_yes 0x00000001 -#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h deleted file mode 100644 index e00fab0c9335..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __iop_fifo_in_extra_defs_asm_h -#define __iop_fifo_in_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_in_extra_r_stat___last___width 8 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_extra_r_stat_offset 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_intr_offset 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 - - -/* Constants */ -#define regk_iop_fifo_in_extra_fifo_in 0x00000002 -#define regk_iop_fifo_in_extra_no 0x00000000 -#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_extra_yes 0x00000001 -#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h deleted file mode 100644 index 9ec5f4a826df..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h +++ /dev/null @@ -1,254 +0,0 @@ -#ifndef __iop_fifo_out_defs_asm_h -#define __iop_fifo_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 -#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_out_rw_cfg___trig___width 2 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_out_rw_cfg___mode___width 2 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 -#define reg_iop_fifo_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_r_stat___last___lsb 4 -#define reg_iop_fifo_out_r_stat___last___width 8 -#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_r_stat_offset 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_offset 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_offset 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_offset 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_offset 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_set_last_offset 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -#define reg_iop_fifo_out_rs_rd_data_offset 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_rd_data_offset 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_rw_intr_mask_offset 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_rw_ack_intr_offset 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_intr___urun___width 1 -#define reg_iop_fifo_out_r_intr___urun___bit 0 -#define reg_iop_fifo_out_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_intr___last_data___width 1 -#define reg_iop_fifo_out_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_intr___dav___width 1 -#define reg_iop_fifo_out_r_intr___dav___bit 2 -#define reg_iop_fifo_out_r_intr___free___lsb 3 -#define reg_iop_fifo_out_r_intr___free___width 1 -#define reg_iop_fifo_out_r_intr___free___bit 3 -#define reg_iop_fifo_out_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_intr___orun___width 1 -#define reg_iop_fifo_out_r_intr___orun___bit 4 -#define reg_iop_fifo_out_r_intr_offset 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_r_masked_intr_offset 72 - - -/* Constants */ -#define regk_iop_fifo_out_hi 0x00000000 -#define regk_iop_fifo_out_neg 0x00000002 -#define regk_iop_fifo_out_no 0x00000000 -#define regk_iop_fifo_out_order16 0x00000001 -#define regk_iop_fifo_out_order24 0x00000002 -#define regk_iop_fifo_out_order32 0x00000003 -#define regk_iop_fifo_out_order8 0x00000000 -#define regk_iop_fifo_out_pos 0x00000001 -#define regk_iop_fifo_out_pos_neg 0x00000003 -#define regk_iop_fifo_out_rw_cfg_default 0x00000024 -#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_rw_set_last_default 0x00000000 -#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 -#define regk_iop_fifo_out_size16 0x00000002 -#define regk_iop_fifo_out_size24 0x00000001 -#define regk_iop_fifo_out_size32 0x00000000 -#define regk_iop_fifo_out_size8 0x00000003 -#define regk_iop_fifo_out_yes 0x00000001 -#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h deleted file mode 100644 index 0f84a50cf77c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h +++ /dev/null @@ -1,158 +0,0 @@ -#ifndef __iop_fifo_out_extra_defs_asm_h -#define __iop_fifo_out_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_rd_data_offset 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_out_extra_r_stat___last___width 8 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_extra_r_stat_offset 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_intr_offset 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 - - -/* Constants */ -#define regk_iop_fifo_out_extra_no 0x00000000 -#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_extra_yes 0x00000001 -#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h deleted file mode 100644 index 80490c82cc29..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h +++ /dev/null @@ -1,177 +0,0 @@ -#ifndef __iop_mpu_defs_asm_h -#define __iop_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_r_offset 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_ctrl___en___lsb 0 -#define reg_iop_mpu_rw_ctrl___en___width 1 -#define reg_iop_mpu_rw_ctrl___en___bit 0 -#define reg_iop_mpu_rw_ctrl_offset 128 - -/* Register r_pc, scope iop_mpu, type r */ -#define reg_iop_mpu_r_pc___addr___lsb 0 -#define reg_iop_mpu_r_pc___addr___width 12 -#define reg_iop_mpu_r_pc_offset 132 - -/* Register r_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 -#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 -#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 -#define reg_iop_mpu_r_stat___intr_busy___lsb 1 -#define reg_iop_mpu_r_stat___intr_busy___width 1 -#define reg_iop_mpu_r_stat___intr_busy___bit 1 -#define reg_iop_mpu_r_stat___intr_vect___lsb 2 -#define reg_iop_mpu_r_stat___intr_vect___width 16 -#define reg_iop_mpu_r_stat_offset 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_instr_offset 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_immediate_offset 144 - -/* Register r_trace, scope iop_mpu, type r */ -#define reg_iop_mpu_r_trace___intr_vect___lsb 0 -#define reg_iop_mpu_r_trace___intr_vect___width 16 -#define reg_iop_mpu_r_trace___pc___lsb 16 -#define reg_iop_mpu_r_trace___pc___width 12 -#define reg_iop_mpu_r_trace___en___lsb 28 -#define reg_iop_mpu_r_trace___en___width 1 -#define reg_iop_mpu_r_trace___en___bit 28 -#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 -#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 -#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 -#define reg_iop_mpu_r_trace___intr_busy___lsb 30 -#define reg_iop_mpu_r_trace___intr_busy___width 1 -#define reg_iop_mpu_r_trace___intr_busy___bit 30 -#define reg_iop_mpu_r_trace_offset 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_wr_stat___r0___lsb 0 -#define reg_iop_mpu_r_wr_stat___r0___width 1 -#define reg_iop_mpu_r_wr_stat___r0___bit 0 -#define reg_iop_mpu_r_wr_stat___r1___lsb 1 -#define reg_iop_mpu_r_wr_stat___r1___width 1 -#define reg_iop_mpu_r_wr_stat___r1___bit 1 -#define reg_iop_mpu_r_wr_stat___r2___lsb 2 -#define reg_iop_mpu_r_wr_stat___r2___width 1 -#define reg_iop_mpu_r_wr_stat___r2___bit 2 -#define reg_iop_mpu_r_wr_stat___r3___lsb 3 -#define reg_iop_mpu_r_wr_stat___r3___width 1 -#define reg_iop_mpu_r_wr_stat___r3___bit 3 -#define reg_iop_mpu_r_wr_stat___r4___lsb 4 -#define reg_iop_mpu_r_wr_stat___r4___width 1 -#define reg_iop_mpu_r_wr_stat___r4___bit 4 -#define reg_iop_mpu_r_wr_stat___r5___lsb 5 -#define reg_iop_mpu_r_wr_stat___r5___width 1 -#define reg_iop_mpu_r_wr_stat___r5___bit 5 -#define reg_iop_mpu_r_wr_stat___r6___lsb 6 -#define reg_iop_mpu_r_wr_stat___r6___width 1 -#define reg_iop_mpu_r_wr_stat___r6___bit 6 -#define reg_iop_mpu_r_wr_stat___r7___lsb 7 -#define reg_iop_mpu_r_wr_stat___r7___width 1 -#define reg_iop_mpu_r_wr_stat___r7___bit 7 -#define reg_iop_mpu_r_wr_stat___r8___lsb 8 -#define reg_iop_mpu_r_wr_stat___r8___width 1 -#define reg_iop_mpu_r_wr_stat___r8___bit 8 -#define reg_iop_mpu_r_wr_stat___r9___lsb 9 -#define reg_iop_mpu_r_wr_stat___r9___width 1 -#define reg_iop_mpu_r_wr_stat___r9___bit 9 -#define reg_iop_mpu_r_wr_stat___r10___lsb 10 -#define reg_iop_mpu_r_wr_stat___r10___width 1 -#define reg_iop_mpu_r_wr_stat___r10___bit 10 -#define reg_iop_mpu_r_wr_stat___r11___lsb 11 -#define reg_iop_mpu_r_wr_stat___r11___width 1 -#define reg_iop_mpu_r_wr_stat___r11___bit 11 -#define reg_iop_mpu_r_wr_stat___r12___lsb 12 -#define reg_iop_mpu_r_wr_stat___r12___width 1 -#define reg_iop_mpu_r_wr_stat___r12___bit 12 -#define reg_iop_mpu_r_wr_stat___r13___lsb 13 -#define reg_iop_mpu_r_wr_stat___r13___width 1 -#define reg_iop_mpu_r_wr_stat___r13___bit 13 -#define reg_iop_mpu_r_wr_stat___r14___lsb 14 -#define reg_iop_mpu_r_wr_stat___r14___width 1 -#define reg_iop_mpu_r_wr_stat___r14___bit 14 -#define reg_iop_mpu_r_wr_stat___r15___lsb 15 -#define reg_iop_mpu_r_wr_stat___r15___width 1 -#define reg_iop_mpu_r_wr_stat___r15___bit 15 -#define reg_iop_mpu_r_wr_stat_offset 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_thread___addr___lsb 0 -#define reg_iop_mpu_rw_thread___addr___width 12 -#define reg_iop_mpu_rw_thread_offset 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_intr___addr___lsb 0 -#define reg_iop_mpu_rw_intr___addr___width 12 -#define reg_iop_mpu_rw_intr_offset 196 - - -/* Constants */ -#define regk_iop_mpu_no 0x00000000 -#define regk_iop_mpu_r_pc_default 0x00000000 -#define regk_iop_mpu_rw_ctrl_default 0x00000000 -#define regk_iop_mpu_rw_intr_size 0x00000010 -#define regk_iop_mpu_rw_r_size 0x00000010 -#define regk_iop_mpu_rw_thread_default 0x00000000 -#define regk_iop_mpu_rw_thread_size 0x00000004 -#define regk_iop_mpu_yes 0x00000001 -#endif /* __iop_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index a20b8857b4d0..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in0_extra 64 -#define iop_fifo_in1_extra 128 -#define iop_fifo_out0_extra 192 -#define iop_fifo_out1_extra 256 -#define iop_trigger_grp0 320 -#define iop_trigger_grp1 384 -#define iop_trigger_grp2 448 -#define iop_trigger_grp3 512 -#define iop_trigger_grp4 576 -#define iop_trigger_grp5 640 -#define iop_trigger_grp6 704 -#define iop_trigger_grp7 768 -#define iop_crc_par0 896 -#define iop_crc_par1 1024 -#define iop_dmc_in0 1152 -#define iop_dmc_in1 1280 -#define iop_dmc_out0 1408 -#define iop_dmc_out1 1536 -#define iop_fifo_in0 1664 -#define iop_fifo_in1 1792 -#define iop_fifo_out0 1920 -#define iop_fifo_out1 2048 -#define iop_scrc_in0 2176 -#define iop_scrc_in1 2304 -#define iop_scrc_out0 2432 -#define iop_scrc_out1 2560 -#define iop_timer_grp0 2688 -#define iop_timer_grp1 2816 -#define iop_timer_grp2 2944 -#define iop_timer_grp3 3072 -#define iop_sap_in 3328 -#define iop_sap_out 3584 -#define iop_spu0 3840 -#define iop_spu1 4096 -#define iop_sw_cfg 4352 -#define iop_sw_cpu 4608 -#define iop_sw_mpu 4864 -#define iop_sw_spu0 5120 -#define iop_sw_spu1 5376 -#define iop_mpu 5632 diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index a4a10ff300b3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,182 +0,0 @@ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus0_sync_offset 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus1_sync_offset 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 1 -#define reg_iop_sap_in_rw_gio___delay___bit 7 -#define reg_iop_sap_in_rw_gio___logic___lsb 8 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 8 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio1 0x00000000 -#define regk_iop_sap_in_gio13 0x00000005 -#define regk_iop_sap_in_gio18 0x00000003 -#define regk_iop_sap_in_gio19 0x00000004 -#define regk_iop_sap_in_gio21 0x00000006 -#define regk_iop_sap_in_gio23 0x00000005 -#define regk_iop_sap_in_gio29 0x00000007 -#define regk_iop_sap_in_gio5 0x00000004 -#define regk_iop_sap_in_gio6 0x00000001 -#define regk_iop_sap_in_gio7 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 -#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 -#define regk_iop_sap_in_rw_gio_default 0x00000002 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 -#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 -#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 -#define regk_iop_sap_in_tmr_clk200 0x00000000 -#define regk_iop_sap_in_two_clk200 0x00000002 -#define regk_iop_sap_in_yes 0x00000001 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 0ec727f92a25..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus0_offset 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus1_offset 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic___width 1 -#define reg_iop_sap_out_rw_gio___out_logic___bit 10 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio_offset 28 - - -/* Constants */ -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000002 -#define regk_iop_sap_out_clk2 0x00000002 -#define regk_iop_sap_out_clk200 0x00000001 -#define regk_iop_sap_out_clk3 0x00000003 -#define regk_iop_sap_out_ext 0x00000003 -#define regk_iop_sap_out_gated 0x00000004 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio13 0x00000002 -#define regk_iop_sap_out_gio13_clk 0x0000000c -#define regk_iop_sap_out_gio15 0x00000001 -#define regk_iop_sap_out_gio18 0x00000003 -#define regk_iop_sap_out_gio18_clk 0x0000000d -#define regk_iop_sap_out_gio1_clk 0x00000008 -#define regk_iop_sap_out_gio21_clk 0x0000000e -#define regk_iop_sap_out_gio23 0x00000002 -#define regk_iop_sap_out_gio29_clk 0x0000000f -#define regk_iop_sap_out_gio31 0x00000003 -#define regk_iop_sap_out_gio5 0x00000001 -#define regk_iop_sap_out_gio5_clk 0x00000009 -#define regk_iop_sap_out_gio6_clk 0x0000000a -#define regk_iop_sap_out_gio7 0x00000000 -#define regk_iop_sap_out_gio7_clk 0x0000000b -#define regk_iop_sap_out_gio_in13 0x00000001 -#define regk_iop_sap_out_gio_in21 0x00000002 -#define regk_iop_sap_out_gio_in29 0x00000003 -#define regk_iop_sap_out_gio_in5 0x00000000 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_rw_bus0_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu0_gio0 0x00000002 -#define regk_iop_sap_out_spu0_gio1 0x00000003 -#define regk_iop_sap_out_spu0_gio12 0x00000004 -#define regk_iop_sap_out_spu0_gio13 0x00000004 -#define regk_iop_sap_out_spu0_gio14 0x00000004 -#define regk_iop_sap_out_spu0_gio15 0x00000004 -#define regk_iop_sap_out_spu0_gio2 0x00000002 -#define regk_iop_sap_out_spu0_gio3 0x00000003 -#define regk_iop_sap_out_spu0_gio4 0x00000002 -#define regk_iop_sap_out_spu0_gio5 0x00000003 -#define regk_iop_sap_out_spu0_gio6 0x00000002 -#define regk_iop_sap_out_spu0_gio7 0x00000003 -#define regk_iop_sap_out_spu1_gio0 0x00000005 -#define regk_iop_sap_out_spu1_gio1 0x00000006 -#define regk_iop_sap_out_spu1_gio12 0x00000007 -#define regk_iop_sap_out_spu1_gio13 0x00000007 -#define regk_iop_sap_out_spu1_gio14 0x00000007 -#define regk_iop_sap_out_spu1_gio15 0x00000007 -#define regk_iop_sap_out_spu1_gio2 0x00000005 -#define regk_iop_sap_out_spu1_gio3 0x00000006 -#define regk_iop_sap_out_spu1_gio4 0x00000005 -#define regk_iop_sap_out_spu1_gio5 0x00000006 -#define regk_iop_sap_out_spu1_gio6 0x00000005 -#define regk_iop_sap_out_spu1_gio7 0x00000006 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 -#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 -#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 -#define regk_iop_sap_out_tmr 0x00000005 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h deleted file mode 100644 index 2cf5721597fc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef __iop_scrc_in_defs_asm_h -#define __iop_scrc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_in_rw_cfg___trig___width 2 -#define reg_iop_scrc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_scrc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_stat___err___lsb 0 -#define reg_iop_scrc_in_r_stat___err___width 1 -#define reg_iop_scrc_in_r_stat___err___bit 0 -#define reg_iop_scrc_in_r_stat_offset 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_init_crc_offset 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -#define reg_iop_scrc_in_rs_computed_crc_offset 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_computed_crc_offset 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_crc_offset 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_correct_crc_offset 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 -#define reg_iop_scrc_in_rw_wr1bit___data___width 2 -#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 -#define reg_iop_scrc_in_rw_wr1bit___last___width 2 -#define reg_iop_scrc_in_rw_wr1bit_offset 32 - - -/* Constants */ -#define regk_iop_scrc_in_dif_in 0x00000002 -#define regk_iop_scrc_in_hi 0x00000000 -#define regk_iop_scrc_in_neg 0x00000002 -#define regk_iop_scrc_in_no 0x00000000 -#define regk_iop_scrc_in_pos 0x00000001 -#define regk_iop_scrc_in_pos_neg 0x00000003 -#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rw_cfg_default 0x00000000 -#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_in_set0 0x00000000 -#define regk_iop_scrc_in_set1 0x00000001 -#define regk_iop_scrc_in_yes 0x00000001 -#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h deleted file mode 100644 index 640a25725f20..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifndef __iop_scrc_out_defs_asm_h -#define __iop_scrc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_out_rw_cfg___trig___width 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 -#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 -#define reg_iop_scrc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 -#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 -#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 -#define reg_iop_scrc_out_rw_ctrl_offset 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_init_crc_offset 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_crc_offset 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_data___val___lsb 0 -#define reg_iop_scrc_out_rw_data___val___width 1 -#define reg_iop_scrc_out_rw_data___val___bit 0 -#define reg_iop_scrc_out_rw_data_offset 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -#define reg_iop_scrc_out_r_computed_crc_offset 20 - - -/* Constants */ -#define regk_iop_scrc_out_crc 0x00000001 -#define regk_iop_scrc_out_data 0x00000000 -#define regk_iop_scrc_out_dif 0x00000001 -#define regk_iop_scrc_out_hi 0x00000000 -#define regk_iop_scrc_out_neg 0x00000002 -#define regk_iop_scrc_out_no 0x00000000 -#define regk_iop_scrc_out_pos 0x00000001 -#define regk_iop_scrc_out_pos_neg 0x00000003 -#define regk_iop_scrc_out_reg 0x00000000 -#define regk_iop_scrc_out_rw_cfg_default 0x00000000 -#define regk_iop_scrc_out_rw_crc_default 0x00000000 -#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_out_rw_data_default 0x00000000 -#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_out_yes 0x00000001 -#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h deleted file mode 100644 index bb402c1aa761..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h +++ /dev/null @@ -1,573 +0,0 @@ -#ifndef __iop_spu_defs_asm_h -#define __iop_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -#define reg_iop_spu_rw_r_offset 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_seq_pc___addr___lsb 0 -#define reg_iop_spu_rw_seq_pc___addr___width 12 -#define reg_iop_spu_rw_seq_pc_offset 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 -#define reg_iop_spu_rw_fsm_pc___addr___width 12 -#define reg_iop_spu_rw_fsm_pc_offset 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -#define reg_iop_spu_rw_ctrl___fsm___lsb 0 -#define reg_iop_spu_rw_ctrl___fsm___width 1 -#define reg_iop_spu_rw_ctrl___fsm___bit 0 -#define reg_iop_spu_rw_ctrl___en___lsb 1 -#define reg_iop_spu_rw_ctrl___en___width 1 -#define reg_iop_spu_rw_ctrl___en___bit 1 -#define reg_iop_spu_rw_ctrl_offset 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 -#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 -#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_offset 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus0_out_offset 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus1_out_offset 92 - -/* Register r_gio_in, scope iop_spu, type r */ -#define reg_iop_spu_r_gio_in_offset 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus0_in_offset 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus1_in_offset 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_set_offset 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_clr_offset 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -#define reg_iop_spu_rs_wr_stat___r0___lsb 0 -#define reg_iop_spu_rs_wr_stat___r0___width 1 -#define reg_iop_spu_rs_wr_stat___r0___bit 0 -#define reg_iop_spu_rs_wr_stat___r1___lsb 1 -#define reg_iop_spu_rs_wr_stat___r1___width 1 -#define reg_iop_spu_rs_wr_stat___r1___bit 1 -#define reg_iop_spu_rs_wr_stat___r2___lsb 2 -#define reg_iop_spu_rs_wr_stat___r2___width 1 -#define reg_iop_spu_rs_wr_stat___r2___bit 2 -#define reg_iop_spu_rs_wr_stat___r3___lsb 3 -#define reg_iop_spu_rs_wr_stat___r3___width 1 -#define reg_iop_spu_rs_wr_stat___r3___bit 3 -#define reg_iop_spu_rs_wr_stat___r4___lsb 4 -#define reg_iop_spu_rs_wr_stat___r4___width 1 -#define reg_iop_spu_rs_wr_stat___r4___bit 4 -#define reg_iop_spu_rs_wr_stat___r5___lsb 5 -#define reg_iop_spu_rs_wr_stat___r5___width 1 -#define reg_iop_spu_rs_wr_stat___r5___bit 5 -#define reg_iop_spu_rs_wr_stat___r6___lsb 6 -#define reg_iop_spu_rs_wr_stat___r6___width 1 -#define reg_iop_spu_rs_wr_stat___r6___bit 6 -#define reg_iop_spu_rs_wr_stat___r7___lsb 7 -#define reg_iop_spu_rs_wr_stat___r7___width 1 -#define reg_iop_spu_rs_wr_stat___r7___bit 7 -#define reg_iop_spu_rs_wr_stat___r8___lsb 8 -#define reg_iop_spu_rs_wr_stat___r8___width 1 -#define reg_iop_spu_rs_wr_stat___r8___bit 8 -#define reg_iop_spu_rs_wr_stat___r9___lsb 9 -#define reg_iop_spu_rs_wr_stat___r9___width 1 -#define reg_iop_spu_rs_wr_stat___r9___bit 9 -#define reg_iop_spu_rs_wr_stat___r10___lsb 10 -#define reg_iop_spu_rs_wr_stat___r10___width 1 -#define reg_iop_spu_rs_wr_stat___r10___bit 10 -#define reg_iop_spu_rs_wr_stat___r11___lsb 11 -#define reg_iop_spu_rs_wr_stat___r11___width 1 -#define reg_iop_spu_rs_wr_stat___r11___bit 11 -#define reg_iop_spu_rs_wr_stat___r12___lsb 12 -#define reg_iop_spu_rs_wr_stat___r12___width 1 -#define reg_iop_spu_rs_wr_stat___r12___bit 12 -#define reg_iop_spu_rs_wr_stat___r13___lsb 13 -#define reg_iop_spu_rs_wr_stat___r13___width 1 -#define reg_iop_spu_rs_wr_stat___r13___bit 13 -#define reg_iop_spu_rs_wr_stat___r14___lsb 14 -#define reg_iop_spu_rs_wr_stat___r14___width 1 -#define reg_iop_spu_rs_wr_stat___r14___bit 14 -#define reg_iop_spu_rs_wr_stat___r15___lsb 15 -#define reg_iop_spu_rs_wr_stat___r15___width 1 -#define reg_iop_spu_rs_wr_stat___r15___bit 15 -#define reg_iop_spu_rs_wr_stat_offset 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_wr_stat___r0___lsb 0 -#define reg_iop_spu_r_wr_stat___r0___width 1 -#define reg_iop_spu_r_wr_stat___r0___bit 0 -#define reg_iop_spu_r_wr_stat___r1___lsb 1 -#define reg_iop_spu_r_wr_stat___r1___width 1 -#define reg_iop_spu_r_wr_stat___r1___bit 1 -#define reg_iop_spu_r_wr_stat___r2___lsb 2 -#define reg_iop_spu_r_wr_stat___r2___width 1 -#define reg_iop_spu_r_wr_stat___r2___bit 2 -#define reg_iop_spu_r_wr_stat___r3___lsb 3 -#define reg_iop_spu_r_wr_stat___r3___width 1 -#define reg_iop_spu_r_wr_stat___r3___bit 3 -#define reg_iop_spu_r_wr_stat___r4___lsb 4 -#define reg_iop_spu_r_wr_stat___r4___width 1 -#define reg_iop_spu_r_wr_stat___r4___bit 4 -#define reg_iop_spu_r_wr_stat___r5___lsb 5 -#define reg_iop_spu_r_wr_stat___r5___width 1 -#define reg_iop_spu_r_wr_stat___r5___bit 5 -#define reg_iop_spu_r_wr_stat___r6___lsb 6 -#define reg_iop_spu_r_wr_stat___r6___width 1 -#define reg_iop_spu_r_wr_stat___r6___bit 6 -#define reg_iop_spu_r_wr_stat___r7___lsb 7 -#define reg_iop_spu_r_wr_stat___r7___width 1 -#define reg_iop_spu_r_wr_stat___r7___bit 7 -#define reg_iop_spu_r_wr_stat___r8___lsb 8 -#define reg_iop_spu_r_wr_stat___r8___width 1 -#define reg_iop_spu_r_wr_stat___r8___bit 8 -#define reg_iop_spu_r_wr_stat___r9___lsb 9 -#define reg_iop_spu_r_wr_stat___r9___width 1 -#define reg_iop_spu_r_wr_stat___r9___bit 9 -#define reg_iop_spu_r_wr_stat___r10___lsb 10 -#define reg_iop_spu_r_wr_stat___r10___width 1 -#define reg_iop_spu_r_wr_stat___r10___bit 10 -#define reg_iop_spu_r_wr_stat___r11___lsb 11 -#define reg_iop_spu_r_wr_stat___r11___width 1 -#define reg_iop_spu_r_wr_stat___r11___bit 11 -#define reg_iop_spu_r_wr_stat___r12___lsb 12 -#define reg_iop_spu_r_wr_stat___r12___width 1 -#define reg_iop_spu_r_wr_stat___r12___bit 12 -#define reg_iop_spu_r_wr_stat___r13___lsb 13 -#define reg_iop_spu_r_wr_stat___r13___width 1 -#define reg_iop_spu_r_wr_stat___r13___bit 13 -#define reg_iop_spu_r_wr_stat___r14___lsb 14 -#define reg_iop_spu_r_wr_stat___r14___width 1 -#define reg_iop_spu_r_wr_stat___r14___bit 14 -#define reg_iop_spu_r_wr_stat___r15___lsb 15 -#define reg_iop_spu_r_wr_stat___r15___width 1 -#define reg_iop_spu_r_wr_stat___r15___bit 15 -#define reg_iop_spu_r_wr_stat_offset 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 - -/* Register r_stat_in, scope iop_spu, type r */ -#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 -#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 -#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 -#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 -#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 -#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 -#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 -#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 -#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 -#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 -#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 -#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 -#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 -#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 -#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 -#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 -#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 -#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 -#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 -#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 -#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 -#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 -#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 -#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 -#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 -#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 -#define reg_iop_spu_r_stat_in___sync_clk12___width 1 -#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 -#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 -#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 -#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 -#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 -#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 -#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 -#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 -#define reg_iop_spu_r_stat_in___mc_busy___width 1 -#define reg_iop_spu_r_stat_in___mc_busy___bit 30 -#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 -#define reg_iop_spu_r_stat_in___mc_owned___width 1 -#define reg_iop_spu_r_stat_in___mc_owned___bit 31 -#define reg_iop_spu_r_stat_in_offset 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -#define reg_iop_spu_r_trigger_in_offset 132 - -/* Register r_special_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_special_stat___c_flag___lsb 0 -#define reg_iop_spu_r_special_stat___c_flag___width 1 -#define reg_iop_spu_r_special_stat___c_flag___bit 0 -#define reg_iop_spu_r_special_stat___v_flag___lsb 1 -#define reg_iop_spu_r_special_stat___v_flag___width 1 -#define reg_iop_spu_r_special_stat___v_flag___bit 1 -#define reg_iop_spu_r_special_stat___z_flag___lsb 2 -#define reg_iop_spu_r_special_stat___z_flag___width 1 -#define reg_iop_spu_r_special_stat___z_flag___bit 2 -#define reg_iop_spu_r_special_stat___n_flag___lsb 3 -#define reg_iop_spu_r_special_stat___n_flag___width 1 -#define reg_iop_spu_r_special_stat___n_flag___bit 3 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 -#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 -#define reg_iop_spu_r_special_stat___fsm_in0___width 1 -#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 -#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 -#define reg_iop_spu_r_special_stat___fsm_in1___width 1 -#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 -#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 -#define reg_iop_spu_r_special_stat___fsm_in2___width 1 -#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 -#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 -#define reg_iop_spu_r_special_stat___fsm_in3___width 1 -#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 -#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 -#define reg_iop_spu_r_special_stat___fsm_in4___width 1 -#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 -#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 -#define reg_iop_spu_r_special_stat___fsm_in5___width 1 -#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 -#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 -#define reg_iop_spu_r_special_stat___fsm_in6___width 1 -#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 -#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 -#define reg_iop_spu_r_special_stat___fsm_in7___width 1 -#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 -#define reg_iop_spu_r_special_stat___event0___lsb 16 -#define reg_iop_spu_r_special_stat___event0___width 1 -#define reg_iop_spu_r_special_stat___event0___bit 16 -#define reg_iop_spu_r_special_stat___event1___lsb 17 -#define reg_iop_spu_r_special_stat___event1___width 1 -#define reg_iop_spu_r_special_stat___event1___bit 17 -#define reg_iop_spu_r_special_stat___event2___lsb 18 -#define reg_iop_spu_r_special_stat___event2___width 1 -#define reg_iop_spu_r_special_stat___event2___bit 18 -#define reg_iop_spu_r_special_stat___event3___lsb 19 -#define reg_iop_spu_r_special_stat___event3___width 1 -#define reg_iop_spu_r_special_stat___event3___bit 19 -#define reg_iop_spu_r_special_stat_offset 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -#define reg_iop_spu_rw_reg_access___addr___lsb 0 -#define reg_iop_spu_rw_reg_access___addr___width 13 -#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 -#define reg_iop_spu_rw_reg_access___imm_hi___width 16 -#define reg_iop_spu_rw_reg_access_offset 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_cfg___addr___lsb 0 -#define reg_iop_spu_rw_event_cfg___addr___width 12 -#define reg_iop_spu_rw_event_cfg___src___lsb 12 -#define reg_iop_spu_rw_event_cfg___src___width 2 -#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 -#define reg_iop_spu_rw_event_cfg___eq_en___width 1 -#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 -#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 -#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 -#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 -#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 -#define reg_iop_spu_rw_event_cfg___gt_en___width 1 -#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 -#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 -#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 -#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 -#define reg_iop_spu_rw_event_cfg_offset 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_mask_offset 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_val_offset 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_ret___addr___lsb 0 -#define reg_iop_spu_rw_event_ret___addr___width 12 -#define reg_iop_spu_rw_event_ret_offset 192 - -/* Register r_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_trace___fsm___lsb 0 -#define reg_iop_spu_r_trace___fsm___width 1 -#define reg_iop_spu_r_trace___fsm___bit 0 -#define reg_iop_spu_r_trace___en___lsb 1 -#define reg_iop_spu_r_trace___en___width 1 -#define reg_iop_spu_r_trace___en___bit 1 -#define reg_iop_spu_r_trace___c_flag___lsb 2 -#define reg_iop_spu_r_trace___c_flag___width 1 -#define reg_iop_spu_r_trace___c_flag___bit 2 -#define reg_iop_spu_r_trace___v_flag___lsb 3 -#define reg_iop_spu_r_trace___v_flag___width 1 -#define reg_iop_spu_r_trace___v_flag___bit 3 -#define reg_iop_spu_r_trace___z_flag___lsb 4 -#define reg_iop_spu_r_trace___z_flag___width 1 -#define reg_iop_spu_r_trace___z_flag___bit 4 -#define reg_iop_spu_r_trace___n_flag___lsb 5 -#define reg_iop_spu_r_trace___n_flag___width 1 -#define reg_iop_spu_r_trace___n_flag___bit 5 -#define reg_iop_spu_r_trace___seq_addr___lsb 6 -#define reg_iop_spu_r_trace___seq_addr___width 12 -#define reg_iop_spu_r_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_trace___fsm_addr___width 12 -#define reg_iop_spu_r_trace_offset 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 -#define reg_iop_spu_r_fsm_trace___fsm___width 1 -#define reg_iop_spu_r_fsm_trace___fsm___bit 0 -#define reg_iop_spu_r_fsm_trace___en___lsb 1 -#define reg_iop_spu_r_fsm_trace___en___width 1 -#define reg_iop_spu_r_fsm_trace___en___bit 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 -#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 -#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 -#define reg_iop_spu_r_fsm_trace___inp0___width 1 -#define reg_iop_spu_r_fsm_trace___inp0___bit 3 -#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 -#define reg_iop_spu_r_fsm_trace___inp1___width 1 -#define reg_iop_spu_r_fsm_trace___inp1___bit 4 -#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 -#define reg_iop_spu_r_fsm_trace___inp2___width 1 -#define reg_iop_spu_r_fsm_trace___inp2___bit 5 -#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 -#define reg_iop_spu_r_fsm_trace___inp3___width 1 -#define reg_iop_spu_r_fsm_trace___inp3___bit 6 -#define reg_iop_spu_r_fsm_trace___event0___lsb 7 -#define reg_iop_spu_r_fsm_trace___event0___width 1 -#define reg_iop_spu_r_fsm_trace___event0___bit 7 -#define reg_iop_spu_r_fsm_trace___event1___lsb 8 -#define reg_iop_spu_r_fsm_trace___event1___width 1 -#define reg_iop_spu_r_fsm_trace___event1___bit 8 -#define reg_iop_spu_r_fsm_trace___event2___lsb 9 -#define reg_iop_spu_r_fsm_trace___event2___width 1 -#define reg_iop_spu_r_fsm_trace___event2___bit 9 -#define reg_iop_spu_r_fsm_trace___event3___lsb 10 -#define reg_iop_spu_r_fsm_trace___event3___width 1 -#define reg_iop_spu_r_fsm_trace___event3___bit 10 -#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 -#define reg_iop_spu_r_fsm_trace___gio_out___width 8 -#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 -#define reg_iop_spu_r_fsm_trace_offset 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -#define reg_iop_spu_rw_brp___addr___lsb 0 -#define reg_iop_spu_rw_brp___addr___width 12 -#define reg_iop_spu_rw_brp___fsm___lsb 12 -#define reg_iop_spu_rw_brp___fsm___width 1 -#define reg_iop_spu_rw_brp___fsm___bit 12 -#define reg_iop_spu_rw_brp___en___lsb 13 -#define reg_iop_spu_rw_brp___en___width 1 -#define reg_iop_spu_rw_brp___en___bit 13 -#define reg_iop_spu_rw_brp_offset 204 - - -/* Constants */ -#define regk_iop_spu_attn_hi 0x00000005 -#define regk_iop_spu_attn_lo 0x00000005 -#define regk_iop_spu_attn_r0 0x00000000 -#define regk_iop_spu_attn_r1 0x00000001 -#define regk_iop_spu_attn_r10 0x00000002 -#define regk_iop_spu_attn_r11 0x00000003 -#define regk_iop_spu_attn_r12 0x00000004 -#define regk_iop_spu_attn_r13 0x00000005 -#define regk_iop_spu_attn_r14 0x00000006 -#define regk_iop_spu_attn_r15 0x00000007 -#define regk_iop_spu_attn_r2 0x00000002 -#define regk_iop_spu_attn_r3 0x00000003 -#define regk_iop_spu_attn_r4 0x00000004 -#define regk_iop_spu_attn_r5 0x00000005 -#define regk_iop_spu_attn_r6 0x00000006 -#define regk_iop_spu_attn_r7 0x00000007 -#define regk_iop_spu_attn_r8 0x00000000 -#define regk_iop_spu_attn_r9 0x00000001 -#define regk_iop_spu_c 0x00000000 -#define regk_iop_spu_flag 0x00000002 -#define regk_iop_spu_gio_in 0x00000000 -#define regk_iop_spu_gio_out 0x00000005 -#define regk_iop_spu_gio_out0 0x00000008 -#define regk_iop_spu_gio_out1 0x00000009 -#define regk_iop_spu_gio_out2 0x0000000a -#define regk_iop_spu_gio_out3 0x0000000b -#define regk_iop_spu_gio_out4 0x0000000c -#define regk_iop_spu_gio_out5 0x0000000d -#define regk_iop_spu_gio_out6 0x0000000e -#define regk_iop_spu_gio_out7 0x0000000f -#define regk_iop_spu_n 0x00000003 -#define regk_iop_spu_no 0x00000000 -#define regk_iop_spu_r0 0x00000008 -#define regk_iop_spu_r1 0x00000009 -#define regk_iop_spu_r10 0x0000000a -#define regk_iop_spu_r11 0x0000000b -#define regk_iop_spu_r12 0x0000000c -#define regk_iop_spu_r13 0x0000000d -#define regk_iop_spu_r14 0x0000000e -#define regk_iop_spu_r15 0x0000000f -#define regk_iop_spu_r2 0x0000000a -#define regk_iop_spu_r3 0x0000000b -#define regk_iop_spu_r4 0x0000000c -#define regk_iop_spu_r5 0x0000000d -#define regk_iop_spu_r6 0x0000000e -#define regk_iop_spu_r7 0x0000000f -#define regk_iop_spu_r8 0x00000008 -#define regk_iop_spu_r9 0x00000009 -#define regk_iop_spu_reg_hi 0x00000002 -#define regk_iop_spu_reg_lo 0x00000002 -#define regk_iop_spu_rw_brp_default 0x00000000 -#define regk_iop_spu_rw_brp_size 0x00000004 -#define regk_iop_spu_rw_ctrl_default 0x00000000 -#define regk_iop_spu_rw_event_cfg_size 0x00000004 -#define regk_iop_spu_rw_event_mask_size 0x00000004 -#define regk_iop_spu_rw_event_val_size 0x00000004 -#define regk_iop_spu_rw_gio_out_default 0x00000000 -#define regk_iop_spu_rw_r_size 0x00000010 -#define regk_iop_spu_rw_reg_access_default 0x00000000 -#define regk_iop_spu_stat_in 0x00000002 -#define regk_iop_spu_statin_hi 0x00000004 -#define regk_iop_spu_statin_lo 0x00000004 -#define regk_iop_spu_trig 0x00000003 -#define regk_iop_spu_trigger 0x00000006 -#define regk_iop_spu_v 0x00000001 -#define regk_iop_spu_wsts_gioout_spec 0x00000001 -#define regk_iop_spu_xor 0x00000003 -#define regk_iop_spu_xor_bus0_r2_0 0x00000000 -#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 -#define regk_iop_spu_xor_bus1_r3_0 0x00000001 -#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 -#define regk_iop_spu_yes 0x00000001 -#define regk_iop_spu_z 0x00000002 -#endif /* __iop_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3be60f9b024c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,1052 +0,0 @@ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus0 0x00000000 -#define regk_iop_sw_cfg_bus0_rot16 0x00000004 -#define regk_iop_sw_cfg_bus0_rot24 0x00000006 -#define regk_iop_sw_cfg_bus0_rot8 0x00000002 -#define regk_iop_sw_cfg_bus1 0x00000001 -#define regk_iop_sw_cfg_bus1_rot16 0x00000005 -#define regk_iop_sw_cfg_bus1_rot24 0x00000007 -#define regk_iop_sw_cfg_bus1_rot8 0x00000003 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_dmc0 0x00000000 -#define regk_iop_sw_cfg_dmc1 0x00000001 -#define regk_iop_sw_cfg_gated_clk0 0x00000010 -#define regk_iop_sw_cfg_gated_clk1 0x00000011 -#define regk_iop_sw_cfg_gated_clk2 0x00000012 -#define regk_iop_sw_cfg_gated_clk3 0x00000013 -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in0 0x00000000 -#define regk_iop_sw_cfg_gio_in1 0x00000001 -#define regk_iop_sw_cfg_gio_in10 0x00000002 -#define regk_iop_sw_cfg_gio_in11 0x00000003 -#define regk_iop_sw_cfg_gio_in14 0x00000004 -#define regk_iop_sw_cfg_gio_in15 0x00000005 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in28 0x00000006 -#define regk_iop_sw_cfg_gio_in29 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 -#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_par0 0x00000000 -#define regk_iop_sw_cfg_par1 0x00000001 -#define regk_iop_sw_cfg_pdp_out0 0x00000002 -#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 -#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_pdp_out1 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 -#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out0 0x00000008 -#define regk_iop_sw_cfg_sdp_out1 0x00000009 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu0 0x00000002 -#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu0_g0 0x0000000e -#define regk_iop_sw_cfg_spu0_g1 0x0000000e -#define regk_iop_sw_cfg_spu0_g2 0x0000000e -#define regk_iop_sw_cfg_spu0_g3 0x0000000e -#define regk_iop_sw_cfg_spu0_g4 0x0000000e -#define regk_iop_sw_cfg_spu0_g5 0x0000000e -#define regk_iop_sw_cfg_spu0_g6 0x0000000e -#define regk_iop_sw_cfg_spu0_g7 0x0000000e -#define regk_iop_sw_cfg_spu0_gio0 0x00000000 -#define regk_iop_sw_cfg_spu0_gio1 0x00000001 -#define regk_iop_sw_cfg_spu0_gio2 0x00000000 -#define regk_iop_sw_cfg_spu0_gio5 0x00000005 -#define regk_iop_sw_cfg_spu0_gio6 0x00000006 -#define regk_iop_sw_cfg_spu0_gio7 0x00000007 -#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e -#define regk_iop_sw_cfg_spu1 0x00000003 -#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu1_g0 0x0000000f -#define regk_iop_sw_cfg_spu1_g1 0x0000000f -#define regk_iop_sw_cfg_spu1_g2 0x0000000f -#define regk_iop_sw_cfg_spu1_g3 0x0000000f -#define regk_iop_sw_cfg_spu1_g4 0x0000000f -#define regk_iop_sw_cfg_spu1_g5 0x0000000f -#define regk_iop_sw_cfg_spu1_g6 0x0000000f -#define regk_iop_sw_cfg_spu1_g7 0x0000000f -#define regk_iop_sw_cfg_spu1_gio0 0x00000002 -#define regk_iop_sw_cfg_spu1_gio1 0x00000003 -#define regk_iop_sw_cfg_spu1_gio2 0x00000002 -#define regk_iop_sw_cfg_spu1_gio5 0x00000005 -#define regk_iop_sw_cfg_spu1_gio6 0x00000006 -#define regk_iop_sw_cfg_spu1_gio7 0x00000007 -#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 -#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 -#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 -#define regk_iop_sw_cfg_timer_grp2 0x00000000 -#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 -#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 -#define regk_iop_sw_cfg_timer_grp3 0x00000000 -#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 -#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000000 -#define regk_iop_sw_cfg_trig2_1 0x00000000 -#define regk_iop_sw_cfg_trig2_2 0x00000000 -#define regk_iop_sw_cfg_trig2_3 0x00000000 -#define regk_iop_sw_cfg_trig3_0 0x00000000 -#define regk_iop_sw_cfg_trig3_1 0x00000000 -#define regk_iop_sw_cfg_trig3_2 0x00000000 -#define regk_iop_sw_cfg_trig3_3 0x00000000 -#define regk_iop_sw_cfg_trig4_0 0x00000001 -#define regk_iop_sw_cfg_trig4_1 0x00000001 -#define regk_iop_sw_cfg_trig4_2 0x00000001 -#define regk_iop_sw_cfg_trig4_3 0x00000001 -#define regk_iop_sw_cfg_trig5_0 0x00000001 -#define regk_iop_sw_cfg_trig5_1 0x00000001 -#define regk_iop_sw_cfg_trig5_2 0x00000001 -#define regk_iop_sw_cfg_trig5_3 0x00000001 -#define regk_iop_sw_cfg_trig6_0 0x00000001 -#define regk_iop_sw_cfg_trig6_1 0x00000001 -#define regk_iop_sw_cfg_trig6_2 0x00000001 -#define regk_iop_sw_cfg_trig6_3 0x00000001 -#define regk_iop_sw_cfg_trig7_0 0x00000001 -#define regk_iop_sw_cfg_trig7_1 0x00000001 -#define regk_iop_sw_cfg_trig7_2 0x00000001 -#define regk_iop_sw_cfg_trig7_3 0x00000001 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index db347bcba025..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,1758 +0,0 @@ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_cpu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr2_offset 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr2_offset 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 -#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_intr3_offset 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_masked_intr3_offset 144 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ee7dc0435b59..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1776 +0,0 @@ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_mpu_r_mc_stat_offset 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus0_in_offset 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus1_in_offset 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp0_offset 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp1_offset 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp2_offset 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp3_offset 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu0 0x00000002 -#define regk_iop_sw_mpu_spu1 0x00000003 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 0929f144cfa1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,691 +0,0 @@ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_spu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 -#define reg_iop_sw_spu_r_hw_intr_offset 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 -#define reg_iop_sw_spu_r_mpu_intr_offset 164 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h deleted file mode 100644 index 7129a9a4bedc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h +++ /dev/null @@ -1,237 +0,0 @@ -#ifndef __iop_timer_grp_defs_asm_h -#define __iop_timer_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 -#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 -#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 -#define reg_iop_timer_grp_rw_cfg___trig___width 2 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 -#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 -#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 -#define reg_iop_timer_grp_rw_cfg_offset 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 -#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 -#define reg_iop_timer_grp_rw_half_period_offset 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period_len_offset 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 -#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 -#define reg_iop_timer_grp_rw_tmr_len___val___width 16 -#define reg_iop_timer_grp_rw_tmr_len_offset 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 -#define reg_iop_timer_grp_rw_cmd___rst___width 4 -#define reg_iop_timer_grp_rw_cmd___en___lsb 4 -#define reg_iop_timer_grp_rw_cmd___en___width 4 -#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 -#define reg_iop_timer_grp_rw_cmd___dis___width 4 -#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 -#define reg_iop_timer_grp_rw_cmd___strb___width 4 -#define reg_iop_timer_grp_rw_cmd_offset 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_r_tmr_cnt_offset 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 -#define reg_iop_timer_grp_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 -#define reg_iop_timer_grp_rw_ack_intr_offset 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_intr_offset 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_iop_timer_grp_clk200 0x00000000 -#define regk_iop_timer_grp_clk_gen 0x00000002 -#define regk_iop_timer_grp_complete 0x00000002 -#define regk_iop_timer_grp_div_clk200 0x00000001 -#define regk_iop_timer_grp_div_clk_gen 0x00000003 -#define regk_iop_timer_grp_ext 0x00000001 -#define regk_iop_timer_grp_hi 0x00000000 -#define regk_iop_timer_grp_long_period 0x00000001 -#define regk_iop_timer_grp_neg 0x00000002 -#define regk_iop_timer_grp_no 0x00000000 -#define regk_iop_timer_grp_once 0x00000003 -#define regk_iop_timer_grp_pause 0x00000001 -#define regk_iop_timer_grp_pos 0x00000001 -#define regk_iop_timer_grp_pos_neg 0x00000003 -#define regk_iop_timer_grp_pulse 0x00000000 -#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rw_cfg_default 0x00000002 -#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 -#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 -#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 -#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 -#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 -#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 -#define regk_iop_timer_grp_short_period 0x00000000 -#define regk_iop_timer_grp_stop 0x00000000 -#define regk_iop_timer_grp_tmr 0x00000004 -#define regk_iop_timer_grp_toggle 0x00000001 -#define regk_iop_timer_grp_yes 0x00000001 -#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h deleted file mode 100644 index 1005d9db80dc..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h +++ /dev/null @@ -1,157 +0,0 @@ -#ifndef __iop_trigger_grp_defs_asm_h -#define __iop_trigger_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 -#define reg_iop_trigger_grp_rw_cfg___action___width 2 -#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 -#define reg_iop_trigger_grp_rw_cfg___once___width 1 -#define reg_iop_trigger_grp_rw_cfg___once___bit 2 -#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 -#define reg_iop_trigger_grp_rw_cfg___trig___width 3 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 -#define reg_iop_trigger_grp_rw_cfg_offset 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 -#define reg_iop_trigger_grp_rw_cmd___dis___width 4 -#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 -#define reg_iop_trigger_grp_rw_cmd___en___width 4 -#define reg_iop_trigger_grp_rw_cmd_offset 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 -#define reg_iop_trigger_grp_rw_intr_mask_offset 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 -#define reg_iop_trigger_grp_rw_ack_intr_offset 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_intr_offset 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_masked_intr_offset 32 - - -/* Constants */ -#define regk_iop_trigger_grp_fall 0x00000002 -#define regk_iop_trigger_grp_fall_lo 0x00000006 -#define regk_iop_trigger_grp_no 0x00000000 -#define regk_iop_trigger_grp_off 0x00000000 -#define regk_iop_trigger_grp_pulse 0x00000000 -#define regk_iop_trigger_grp_rise 0x00000001 -#define regk_iop_trigger_grp_rise_fall 0x00000003 -#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 -#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 -#define regk_iop_trigger_grp_rise_hi 0x00000005 -#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 -#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 -#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_trigger_grp_toggle 0x00000003 -#define regk_iop_trigger_grp_yes 0x00000001 -#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index e13feb20a7e3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v1_0 0x00000001 -#endif /* __iop_version_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h deleted file mode 100644 index 90e4785b6474..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h +++ /dev/null @@ -1,232 +0,0 @@ -#ifndef __iop_crc_par_defs_h -#define __iop_crc_par_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_crc_par */ - -/* Register rw_cfg, scope iop_crc_par, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int crc_out : 1; - unsigned int rev_out : 1; - unsigned int inv_out : 1; - unsigned int trig : 2; - unsigned int poly : 3; - unsigned int dummy1 : 23; -} reg_iop_crc_par_rw_cfg; -#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 -#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_init_crc; -#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 -#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_correct_crc; -#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 -#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_ctrl; -#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 -#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int tr_dif : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_set_last; -#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 -#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 - -/* Register r_stat, scope iop_crc_par, type r */ -typedef struct { - unsigned int err : 1; - unsigned int busy : 1; - unsigned int dummy1 : 30; -} reg_iop_crc_par_r_stat; -#define REG_RD_ADDR_iop_crc_par_r_stat 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_sh_reg; -#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 - -/* Register r_crc, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_crc; -#define REG_RD_ADDR_iop_crc_par_r_crc 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_crc_par_rw_strb_rec_dif_in; -#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 -#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 - - -/* Constants */ -enum { - regk_iop_crc_par_calc = 0x00000001, - regk_iop_crc_par_ccitt = 0x00000002, - regk_iop_crc_par_check = 0x00000000, - regk_iop_crc_par_crc16 = 0x00000001, - regk_iop_crc_par_crc32 = 0x00000000, - regk_iop_crc_par_crc5 = 0x00000003, - regk_iop_crc_par_crc5_11 = 0x00000004, - regk_iop_crc_par_dif_in = 0x00000002, - regk_iop_crc_par_hi = 0x00000000, - regk_iop_crc_par_neg = 0x00000002, - regk_iop_crc_par_no = 0x00000000, - regk_iop_crc_par_pos = 0x00000001, - regk_iop_crc_par_pos_neg = 0x00000003, - regk_iop_crc_par_rw_cfg_default = 0x00000000, - regk_iop_crc_par_rw_ctrl_default = 0x00000000, - regk_iop_crc_par_yes = 0x00000001 -}; -#endif /* __iop_crc_par_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h deleted file mode 100644 index 76aec6e37f3e..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h +++ /dev/null @@ -1,325 +0,0 @@ -#ifndef __iop_dmc_in_defs_h -#define __iop_dmc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_in */ - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int sth_intr : 3; - unsigned int last_dis_dif : 1; - unsigned int dummy1 : 28; -} reg_iop_dmc_in_rw_cfg; -#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int stream_clr : 1; - unsigned int dummy1 : 29; -} reg_iop_dmc_in_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_in_r_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_in_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int eop : 1; - unsigned int wait : 1; - unsigned int keep_md : 1; - unsigned int size : 3; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_stream_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int sth : 7; - unsigned int dummy1 : 9; - unsigned int full : 1; - unsigned int last_pkt : 1; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int dummy2 : 9; -} reg_iop_dmc_in_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_data_descr; -#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_in_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_group_descr; -#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 -#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_in_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 -#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 -#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 -#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_intr; -#define REG_RD_ADDR_iop_dmc_in_r_intr 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 - - -/* Constants */ -enum { - regk_iop_dmc_in_ack_pkt = 0x00000100, - regk_iop_dmc_in_array = 0x00000008, - regk_iop_dmc_in_burst = 0x00000020, - regk_iop_dmc_in_copy_next = 0x00000010, - regk_iop_dmc_in_copy_up = 0x00000020, - regk_iop_dmc_in_dis_c = 0x00000010, - regk_iop_dmc_in_dis_g = 0x00000020, - regk_iop_dmc_in_lim1 = 0x00000000, - regk_iop_dmc_in_lim16 = 0x00000004, - regk_iop_dmc_in_lim2 = 0x00000001, - regk_iop_dmc_in_lim32 = 0x00000005, - regk_iop_dmc_in_lim4 = 0x00000002, - regk_iop_dmc_in_lim64 = 0x00000006, - regk_iop_dmc_in_lim8 = 0x00000003, - regk_iop_dmc_in_load_c = 0x00000200, - regk_iop_dmc_in_load_c_n = 0x00000280, - regk_iop_dmc_in_load_c_next = 0x00000240, - regk_iop_dmc_in_load_d = 0x00000140, - regk_iop_dmc_in_load_g = 0x00000300, - regk_iop_dmc_in_load_g_down = 0x000003c0, - regk_iop_dmc_in_load_g_next = 0x00000340, - regk_iop_dmc_in_load_g_up = 0x00000380, - regk_iop_dmc_in_next_en = 0x00000010, - regk_iop_dmc_in_next_pkt = 0x00000010, - regk_iop_dmc_in_no = 0x00000000, - regk_iop_dmc_in_restore = 0x00000020, - regk_iop_dmc_in_rw_cfg_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_in_rw_data_descr_default = 0x00000000, - regk_iop_dmc_in_rw_group_descr_default = 0x00000000, - regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, - regk_iop_dmc_in_save_down = 0x00000020, - regk_iop_dmc_in_save_up = 0x00000020, - regk_iop_dmc_in_set_reg = 0x00000050, - regk_iop_dmc_in_set_w_size1 = 0x00000190, - regk_iop_dmc_in_set_w_size2 = 0x000001a0, - regk_iop_dmc_in_set_w_size4 = 0x000001c0, - regk_iop_dmc_in_store_c = 0x00000002, - regk_iop_dmc_in_store_descr = 0x00000000, - regk_iop_dmc_in_store_g = 0x00000004, - regk_iop_dmc_in_store_md = 0x00000001, - regk_iop_dmc_in_update_down = 0x00000020, - regk_iop_dmc_in_yes = 0x00000001 -}; -#endif /* __iop_dmc_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h deleted file mode 100644 index 938a0d4c4604..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef __iop_dmc_out_defs_h -#define __iop_dmc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_out */ - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int trf_lim : 16; - unsigned int last_at_trf_lim : 1; - unsigned int dth_intr : 3; - unsigned int dummy1 : 12; -} reg_iop_dmc_out_rw_cfg; -#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int dummy1 : 30; -} reg_iop_dmc_out_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_out_r_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_out_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -typedef unsigned int reg_iop_dmc_out_rs_stream_data; -#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_stream_data; -#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dth : 7; - unsigned int dummy1 : 9; - unsigned int dv : 1; - unsigned int all_avail : 1; - unsigned int last : 1; - unsigned int size : 3; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int cmd_rq : 1; - unsigned int dummy2 : 4; -} reg_iop_dmc_out_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_data_descr; -#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_out_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_group_descr; -#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 -#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_out_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 -#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 -#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 -#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_intr; -#define REG_RD_ADDR_iop_dmc_out_r_intr 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 - - -/* Constants */ -enum { - regk_iop_dmc_out_ack_pkt = 0x00000100, - regk_iop_dmc_out_array = 0x00000008, - regk_iop_dmc_out_burst = 0x00000020, - regk_iop_dmc_out_copy_next = 0x00000010, - regk_iop_dmc_out_copy_up = 0x00000020, - regk_iop_dmc_out_dis_c = 0x00000010, - regk_iop_dmc_out_dis_g = 0x00000020, - regk_iop_dmc_out_lim1 = 0x00000000, - regk_iop_dmc_out_lim16 = 0x00000004, - regk_iop_dmc_out_lim2 = 0x00000001, - regk_iop_dmc_out_lim32 = 0x00000005, - regk_iop_dmc_out_lim4 = 0x00000002, - regk_iop_dmc_out_lim64 = 0x00000006, - regk_iop_dmc_out_lim8 = 0x00000003, - regk_iop_dmc_out_load_c = 0x00000200, - regk_iop_dmc_out_load_c_n = 0x00000280, - regk_iop_dmc_out_load_c_next = 0x00000240, - regk_iop_dmc_out_load_d = 0x00000140, - regk_iop_dmc_out_load_g = 0x00000300, - regk_iop_dmc_out_load_g_down = 0x000003c0, - regk_iop_dmc_out_load_g_next = 0x00000340, - regk_iop_dmc_out_load_g_up = 0x00000380, - regk_iop_dmc_out_next_en = 0x00000010, - regk_iop_dmc_out_next_pkt = 0x00000010, - regk_iop_dmc_out_no = 0x00000000, - regk_iop_dmc_out_restore = 0x00000020, - regk_iop_dmc_out_rw_cfg_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_out_rw_data_descr_default = 0x00000000, - regk_iop_dmc_out_rw_group_descr_default = 0x00000000, - regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_out_save_down = 0x00000020, - regk_iop_dmc_out_save_up = 0x00000020, - regk_iop_dmc_out_set_reg = 0x00000050, - regk_iop_dmc_out_set_w_size1 = 0x00000190, - regk_iop_dmc_out_set_w_size2 = 0x000001a0, - regk_iop_dmc_out_set_w_size4 = 0x000001c0, - regk_iop_dmc_out_store_c = 0x00000002, - regk_iop_dmc_out_store_descr = 0x00000000, - regk_iop_dmc_out_store_g = 0x00000004, - regk_iop_dmc_out_store_md = 0x00000001, - regk_iop_dmc_out_update_down = 0x00000020, - regk_iop_dmc_out_yes = 0x00000001 -}; -#endif /* __iop_dmc_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h deleted file mode 100644 index e0c982b263fa..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h +++ /dev/null @@ -1,255 +0,0 @@ -#ifndef __iop_fifo_in_defs_h -#define __iop_fifo_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in */ - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int avail_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int dummy1 : 22; -} reg_iop_fifo_in_rw_cfg; -#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_r_stat; -#define REG_RD_ADDR_iop_fifo_in_r_stat 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_rs_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_r_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_rs_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_r_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_rs_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_r_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_rs_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_r_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -typedef unsigned int reg_iop_fifo_in_rw_set_last; -#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 -#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 -#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 -#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_intr; -#define REG_RD_ADDR_iop_fifo_in_r_intr 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 - - -/* Constants */ -enum { - regk_iop_fifo_in_dif_in = 0x00000002, - regk_iop_fifo_in_hi = 0x00000000, - regk_iop_fifo_in_neg = 0x00000002, - regk_iop_fifo_in_no = 0x00000000, - regk_iop_fifo_in_order16 = 0x00000001, - regk_iop_fifo_in_order24 = 0x00000002, - regk_iop_fifo_in_order32 = 0x00000003, - regk_iop_fifo_in_order8 = 0x00000000, - regk_iop_fifo_in_pos = 0x00000001, - regk_iop_fifo_in_pos_neg = 0x00000003, - regk_iop_fifo_in_rw_cfg_default = 0x00000024, - regk_iop_fifo_in_rw_ctrl_default = 0x00000000, - regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_rw_set_last_default = 0x00000000, - regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, - regk_iop_fifo_in_size16 = 0x00000002, - regk_iop_fifo_in_size24 = 0x00000001, - regk_iop_fifo_in_size32 = 0x00000000, - regk_iop_fifo_in_size8 = 0x00000003, - regk_iop_fifo_in_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h deleted file mode 100644 index 798ac95870e9..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __iop_fifo_in_extra_defs_h -#define __iop_fifo_in_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in_extra */ - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_extra_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 - - -/* Constants */ -enum { - regk_iop_fifo_in_extra_fifo_in = 0x00000002, - regk_iop_fifo_in_extra_no = 0x00000000, - regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h deleted file mode 100644 index 833e10f02526..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h +++ /dev/null @@ -1,278 +0,0 @@ -#ifndef __iop_fifo_out_defs_h -#define __iop_fifo_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out */ - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int free_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int delay_out_last : 1; - unsigned int last_dis_dif_out : 1; - unsigned int dummy1 : 20; -} reg_iop_fifo_out_rw_cfg; -#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_out_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_r_stat; -#define REG_RD_ADDR_iop_fifo_out_r_stat 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_set_last; -#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -typedef unsigned int reg_iop_fifo_out_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -typedef unsigned int reg_iop_fifo_out_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 -#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 -#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 -#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_intr; -#define REG_RD_ADDR_iop_fifo_out_r_intr 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 - - -/* Constants */ -enum { - regk_iop_fifo_out_hi = 0x00000000, - regk_iop_fifo_out_neg = 0x00000002, - regk_iop_fifo_out_no = 0x00000000, - regk_iop_fifo_out_order16 = 0x00000001, - regk_iop_fifo_out_order24 = 0x00000002, - regk_iop_fifo_out_order32 = 0x00000003, - regk_iop_fifo_out_order8 = 0x00000000, - regk_iop_fifo_out_pos = 0x00000001, - regk_iop_fifo_out_pos_neg = 0x00000003, - regk_iop_fifo_out_rw_cfg_default = 0x00000024, - regk_iop_fifo_out_rw_ctrl_default = 0x00000000, - regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_rw_set_last_default = 0x00000000, - regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, - regk_iop_fifo_out_size16 = 0x00000002, - regk_iop_fifo_out_size24 = 0x00000001, - regk_iop_fifo_out_size32 = 0x00000000, - regk_iop_fifo_out_size8 = 0x00000003, - regk_iop_fifo_out_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h deleted file mode 100644 index 4a840aae84ee..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __iop_fifo_out_extra_defs_h -#define __iop_fifo_out_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out_extra */ - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 - - -/* Constants */ -enum { - regk_iop_fifo_out_extra_no = 0x00000000, - regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h deleted file mode 100644 index c2b0ba1be60f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h +++ /dev/null @@ -1,190 +0,0 @@ -#ifndef __iop_mpu_defs_h -#define __iop_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_mpu */ - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_r; -#define REG_RD_ADDR_iop_mpu_rw_r 0 -#define REG_WR_ADDR_iop_mpu_rw_r 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_mpu_rw_ctrl; -#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 -#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 - -/* Register r_pc, scope iop_mpu, type r */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_r_pc; -#define REG_RD_ADDR_iop_mpu_r_pc 132 - -/* Register r_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int intr_vect : 16; - unsigned int dummy1 : 14; -} reg_iop_mpu_r_stat; -#define REG_RD_ADDR_iop_mpu_r_stat 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_instr; -#define REG_RD_ADDR_iop_mpu_rw_instr 140 -#define REG_WR_ADDR_iop_mpu_rw_instr 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_immediate; -#define REG_RD_ADDR_iop_mpu_rw_immediate 144 -#define REG_WR_ADDR_iop_mpu_rw_immediate 144 - -/* Register r_trace, scope iop_mpu, type r */ -typedef struct { - unsigned int intr_vect : 16; - unsigned int pc : 12; - unsigned int en : 1; - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int dummy1 : 1; -} reg_iop_mpu_r_trace; -#define REG_RD_ADDR_iop_mpu_r_trace 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_mpu_r_wr_stat; -#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_thread; -#define REG_RD_ADDR_iop_mpu_rw_thread 156 -#define REG_WR_ADDR_iop_mpu_rw_thread 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_intr; -#define REG_RD_ADDR_iop_mpu_rw_intr 196 -#define REG_WR_ADDR_iop_mpu_rw_intr 196 - - -/* Constants */ -enum { - regk_iop_mpu_no = 0x00000000, - regk_iop_mpu_r_pc_default = 0x00000000, - regk_iop_mpu_rw_ctrl_default = 0x00000000, - regk_iop_mpu_rw_intr_size = 0x00000010, - regk_iop_mpu_rw_r_size = 0x00000010, - regk_iop_mpu_rw_thread_default = 0x00000000, - regk_iop_mpu_rw_thread_size = 0x00000004, - regk_iop_mpu_yes = 0x00000001 -}; -#endif /* __iop_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h deleted file mode 100644 index 2ec897ced166..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h +++ /dev/null @@ -1,764 +0,0 @@ -/* ************************************************************************* */ -/* This file is autogenerated by IOPASM Version 1.2 */ -/* DO NOT EDIT THIS FILE - All changes will be lost! */ -/* ************************************************************************* */ - - - -#ifndef __IOP_MPU_MACROS_H__ -#define __IOP_MPU_MACROS_H__ - - -/* ************************************************************************* */ -/* REGISTER DEFINITIONS */ -/* ************************************************************************* */ -#define MPU_R0 (0x0) -#define MPU_R1 (0x1) -#define MPU_R2 (0x2) -#define MPU_R3 (0x3) -#define MPU_R4 (0x4) -#define MPU_R5 (0x5) -#define MPU_R6 (0x6) -#define MPU_R7 (0x7) -#define MPU_R8 (0x8) -#define MPU_R9 (0x9) -#define MPU_R10 (0xa) -#define MPU_R11 (0xb) -#define MPU_R12 (0xc) -#define MPU_R13 (0xd) -#define MPU_R14 (0xe) -#define MPU_R15 (0xf) -#define MPU_PC (0x2) -#define MPU_WSTS (0x3) -#define MPU_JADDR (0x4) -#define MPU_IRP (0x5) -#define MPU_SRP (0x6) -#define MPU_T0 (0x8) -#define MPU_T1 (0x9) -#define MPU_T2 (0xa) -#define MPU_T3 (0xb) -#define MPU_I0 (0x10) -#define MPU_I1 (0x11) -#define MPU_I2 (0x12) -#define MPU_I3 (0x13) -#define MPU_I4 (0x14) -#define MPU_I5 (0x15) -#define MPU_I6 (0x16) -#define MPU_I7 (0x17) -#define MPU_I8 (0x18) -#define MPU_I9 (0x19) -#define MPU_I10 (0x1a) -#define MPU_I11 (0x1b) -#define MPU_I12 (0x1c) -#define MPU_I13 (0x1d) -#define MPU_I14 (0x1e) -#define MPU_I15 (0x1f) -#define MPU_P2 (0x2) -#define MPU_P3 (0x3) -#define MPU_P5 (0x5) -#define MPU_P6 (0x6) -#define MPU_P8 (0x8) -#define MPU_P9 (0x9) -#define MPU_P10 (0xa) -#define MPU_P11 (0xb) -#define MPU_P16 (0x10) -#define MPU_P17 (0x12) -#define MPU_P18 (0x12) -#define MPU_P19 (0x13) -#define MPU_P20 (0x14) -#define MPU_P21 (0x15) -#define MPU_P22 (0x16) -#define MPU_P23 (0x17) -#define MPU_P24 (0x18) -#define MPU_P25 (0x19) -#define MPU_P26 (0x1a) -#define MPU_P27 (0x1b) -#define MPU_P28 (0x1c) -#define MPU_P29 (0x1d) -#define MPU_P30 (0x1e) -#define MPU_P31 (0x1f) -#define MPU_P1 (0x1) -#define MPU_REGA (0x1) - - - -/* ************************************************************************* */ -/* ADDRESS MACROS */ -/* ************************************************************************* */ -#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) -#define MK_BYTE_ADDR(ADDR) (ADDR) - - - -/* ************************************************************************* */ -/* INSTRUCTION MACROS */ -/* ************************************************************************* */ -#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_DI() (0x40000001) - -#define MPU_EI() (0x40000003) - -#define MPU_HALT() (0x40000002) - -#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JNT() (0x61000000) - -#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_NOP() (0x40000000) - -#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_RET() (0x63003000) - -#define MPU_RETI() (0x63602800) - -#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - - -#endif /* end of __IOP_MPU_MACROS_H__ */ -/* End of iop_mpu_macros.h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 756550f5d6cb..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in0_extra (regi_iop + 64) -#define regi_iop_fifo_in1_extra (regi_iop + 128) -#define regi_iop_fifo_out0_extra (regi_iop + 192) -#define regi_iop_fifo_out1_extra (regi_iop + 256) -#define regi_iop_trigger_grp0 (regi_iop + 320) -#define regi_iop_trigger_grp1 (regi_iop + 384) -#define regi_iop_trigger_grp2 (regi_iop + 448) -#define regi_iop_trigger_grp3 (regi_iop + 512) -#define regi_iop_trigger_grp4 (regi_iop + 576) -#define regi_iop_trigger_grp5 (regi_iop + 640) -#define regi_iop_trigger_grp6 (regi_iop + 704) -#define regi_iop_trigger_grp7 (regi_iop + 768) -#define regi_iop_crc_par0 (regi_iop + 896) -#define regi_iop_crc_par1 (regi_iop + 1024) -#define regi_iop_dmc_in0 (regi_iop + 1152) -#define regi_iop_dmc_in1 (regi_iop + 1280) -#define regi_iop_dmc_out0 (regi_iop + 1408) -#define regi_iop_dmc_out1 (regi_iop + 1536) -#define regi_iop_fifo_in0 (regi_iop + 1664) -#define regi_iop_fifo_in1 (regi_iop + 1792) -#define regi_iop_fifo_out0 (regi_iop + 1920) -#define regi_iop_fifo_out1 (regi_iop + 2048) -#define regi_iop_scrc_in0 (regi_iop + 2176) -#define regi_iop_scrc_in1 (regi_iop + 2304) -#define regi_iop_scrc_out0 (regi_iop + 2432) -#define regi_iop_scrc_out1 (regi_iop + 2560) -#define regi_iop_timer_grp0 (regi_iop + 2688) -#define regi_iop_timer_grp1 (regi_iop + 2816) -#define regi_iop_timer_grp2 (regi_iop + 2944) -#define regi_iop_timer_grp3 (regi_iop + 3072) -#define regi_iop_sap_in (regi_iop + 3328) -#define regi_iop_sap_out (regi_iop + 3584) -#define regi_iop_spu0 (regi_iop + 3840) -#define regi_iop_spu1 (regi_iop + 4096) -#define regi_iop_sw_cfg (regi_iop + 4352) -#define regi_iop_sw_cpu (regi_iop + 4608) -#define regi_iop_sw_mpu (regi_iop + 4864) -#define regi_iop_sw_spu0 (regi_iop + 5120) -#define regi_iop_sw_spu1 (regi_iop + 5376) -#define regi_iop_mpu (regi_iop + 5632) diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 5548ac10074f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,179 +0,0 @@ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus0_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus1_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 -#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 1; - unsigned int logic : 2; - unsigned int dummy1 : 22; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 8 -#define REG_WR_ADDR_iop_sap_in_rw_gio 8 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio1 = 0x00000000, - regk_iop_sap_in_gio13 = 0x00000005, - regk_iop_sap_in_gio18 = 0x00000003, - regk_iop_sap_in_gio19 = 0x00000004, - regk_iop_sap_in_gio21 = 0x00000006, - regk_iop_sap_in_gio23 = 0x00000005, - regk_iop_sap_in_gio29 = 0x00000007, - regk_iop_sap_in_gio5 = 0x00000004, - regk_iop_sap_in_gio6 = 0x00000001, - regk_iop_sap_in_gio7 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, - regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, - regk_iop_sap_in_rw_gio_default = 0x00000002, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, - regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, - regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, - regk_iop_sap_in_tmr_clk200 = 0x00000000, - regk_iop_sap_in_two_clk200 = 0x00000002, - regk_iop_sap_in_yes = 0x00000001 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 273936996183..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,306 +0,0 @@ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int clk2_src : 2; - unsigned int clk2_gate_src : 2; - unsigned int clk2_force_src : 3; - unsigned int clk3_src : 2; - unsigned int clk3_gate_src : 2; - unsigned int clk3_force_src : 3; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus0; -#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus1; -#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 4; - unsigned int out_gated_clk : 2; - unsigned int out_clk_inv : 1; - unsigned int out_logic : 1; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 3; - unsigned int oe_gated_clk : 2; - unsigned int oe_clk_inv : 1; - unsigned int oe_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 28 -#define REG_WR_ADDR_iop_sap_out_rw_gio 28 - - -/* Constants */ -enum { - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000002, - regk_iop_sap_out_clk2 = 0x00000002, - regk_iop_sap_out_clk200 = 0x00000001, - regk_iop_sap_out_clk3 = 0x00000003, - regk_iop_sap_out_ext = 0x00000003, - regk_iop_sap_out_gated = 0x00000004, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio13 = 0x00000002, - regk_iop_sap_out_gio13_clk = 0x0000000c, - regk_iop_sap_out_gio15 = 0x00000001, - regk_iop_sap_out_gio18 = 0x00000003, - regk_iop_sap_out_gio18_clk = 0x0000000d, - regk_iop_sap_out_gio1_clk = 0x00000008, - regk_iop_sap_out_gio21_clk = 0x0000000e, - regk_iop_sap_out_gio23 = 0x00000002, - regk_iop_sap_out_gio29_clk = 0x0000000f, - regk_iop_sap_out_gio31 = 0x00000003, - regk_iop_sap_out_gio5 = 0x00000001, - regk_iop_sap_out_gio5_clk = 0x00000009, - regk_iop_sap_out_gio6_clk = 0x0000000a, - regk_iop_sap_out_gio7 = 0x00000000, - regk_iop_sap_out_gio7_clk = 0x0000000b, - regk_iop_sap_out_gio_in13 = 0x00000001, - regk_iop_sap_out_gio_in21 = 0x00000002, - regk_iop_sap_out_gio_in29 = 0x00000003, - regk_iop_sap_out_gio_in5 = 0x00000000, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_rw_bus0_default = 0x00000000, - regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_default = 0x00000000, - regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu0_gio0 = 0x00000002, - regk_iop_sap_out_spu0_gio1 = 0x00000003, - regk_iop_sap_out_spu0_gio12 = 0x00000004, - regk_iop_sap_out_spu0_gio13 = 0x00000004, - regk_iop_sap_out_spu0_gio14 = 0x00000004, - regk_iop_sap_out_spu0_gio15 = 0x00000004, - regk_iop_sap_out_spu0_gio2 = 0x00000002, - regk_iop_sap_out_spu0_gio3 = 0x00000003, - regk_iop_sap_out_spu0_gio4 = 0x00000002, - regk_iop_sap_out_spu0_gio5 = 0x00000003, - regk_iop_sap_out_spu0_gio6 = 0x00000002, - regk_iop_sap_out_spu0_gio7 = 0x00000003, - regk_iop_sap_out_spu1_gio0 = 0x00000005, - regk_iop_sap_out_spu1_gio1 = 0x00000006, - regk_iop_sap_out_spu1_gio12 = 0x00000007, - regk_iop_sap_out_spu1_gio13 = 0x00000007, - regk_iop_sap_out_spu1_gio14 = 0x00000007, - regk_iop_sap_out_spu1_gio15 = 0x00000007, - regk_iop_sap_out_spu1_gio2 = 0x00000005, - regk_iop_sap_out_spu1_gio3 = 0x00000006, - regk_iop_sap_out_spu1_gio4 = 0x00000005, - regk_iop_sap_out_spu1_gio5 = 0x00000006, - regk_iop_sap_out_spu1_gio6 = 0x00000005, - regk_iop_sap_out_spu1_gio7 = 0x00000006, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, - regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, - regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, - regk_iop_sap_out_tmr = 0x00000005, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h deleted file mode 100644 index 4f0a9a81e737..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h +++ /dev/null @@ -1,160 +0,0 @@ -#ifndef __iop_scrc_in_defs_h -#define __iop_scrc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_in */ - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int dummy1 : 30; -} reg_iop_scrc_in_rw_cfg; -#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -typedef struct { - unsigned int err : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_r_stat; -#define REG_RD_ADDR_iop_scrc_in_r_stat 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 -#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -typedef unsigned int reg_iop_scrc_in_rs_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -typedef unsigned int reg_iop_scrc_in_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 -#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_correct_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 -#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int data : 2; - unsigned int last : 2; - unsigned int dummy1 : 28; -} reg_iop_scrc_in_rw_wr1bit; -#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 -#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 - - -/* Constants */ -enum { - regk_iop_scrc_in_dif_in = 0x00000002, - regk_iop_scrc_in_hi = 0x00000000, - regk_iop_scrc_in_neg = 0x00000002, - regk_iop_scrc_in_no = 0x00000000, - regk_iop_scrc_in_pos = 0x00000001, - regk_iop_scrc_in_pos_neg = 0x00000003, - regk_iop_scrc_in_r_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rw_cfg_default = 0x00000000, - regk_iop_scrc_in_rw_ctrl_default = 0x00000000, - regk_iop_scrc_in_rw_init_crc_default = 0x00000000, - regk_iop_scrc_in_set0 = 0x00000000, - regk_iop_scrc_in_set1 = 0x00000001, - regk_iop_scrc_in_yes = 0x00000001 -}; -#endif /* __iop_scrc_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h deleted file mode 100644 index fd1d6ea1d484..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef __iop_scrc_out_defs_h -#define __iop_scrc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_out */ - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int inv_crc : 1; - unsigned int dummy1 : 29; -} reg_iop_scrc_out_rw_cfg; -#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int strb_src : 1; - unsigned int out_src : 1; - unsigned int dummy1 : 30; -} reg_iop_scrc_out_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 -#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 -#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int val : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_out_rw_data; -#define REG_RD_ADDR_iop_scrc_out_rw_data 16 -#define REG_WR_ADDR_iop_scrc_out_rw_data 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -typedef unsigned int reg_iop_scrc_out_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 - - -/* Constants */ -enum { - regk_iop_scrc_out_crc = 0x00000001, - regk_iop_scrc_out_data = 0x00000000, - regk_iop_scrc_out_dif = 0x00000001, - regk_iop_scrc_out_hi = 0x00000000, - regk_iop_scrc_out_neg = 0x00000002, - regk_iop_scrc_out_no = 0x00000000, - regk_iop_scrc_out_pos = 0x00000001, - regk_iop_scrc_out_pos_neg = 0x00000003, - regk_iop_scrc_out_reg = 0x00000000, - regk_iop_scrc_out_rw_cfg_default = 0x00000000, - regk_iop_scrc_out_rw_crc_default = 0x00000000, - regk_iop_scrc_out_rw_ctrl_default = 0x00000000, - regk_iop_scrc_out_rw_data_default = 0x00000000, - regk_iop_scrc_out_rw_init_crc_default = 0x00000000, - regk_iop_scrc_out_yes = 0x00000001 -}; -#endif /* __iop_scrc_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h deleted file mode 100644 index 0fda26e2f06f..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h +++ /dev/null @@ -1,453 +0,0 @@ -#ifndef __iop_spu_defs_h -#define __iop_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: <not found> - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_spu */ - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_r; -#define REG_RD_ADDR_iop_spu_rw_r 0 -#define REG_WR_ADDR_iop_spu_rw_r 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_seq_pc; -#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 -#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_fsm_pc; -#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 -#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_iop_spu_rw_ctrl; -#define REG_RD_ADDR_iop_spu_rw_ctrl 72 -#define REG_WR_ADDR_iop_spu_rw_ctrl 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -typedef struct { - unsigned int val0 : 5; - unsigned int src0 : 3; - unsigned int val1 : 5; - unsigned int src1 : 3; - unsigned int val2 : 5; - unsigned int src2 : 3; - unsigned int val3 : 5; - unsigned int src3 : 3; -} reg_iop_spu_rw_fsm_inputs3_0; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -typedef struct { - unsigned int val4 : 5; - unsigned int src4 : 3; - unsigned int val5 : 5; - unsigned int src5 : 3; - unsigned int val6 : 5; - unsigned int src6 : 3; - unsigned int val7 : 5; - unsigned int src7 : 3; -} reg_iop_spu_rw_fsm_inputs7_4; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out; -#define REG_RD_ADDR_iop_spu_rw_gio_out 84 -#define REG_WR_ADDR_iop_spu_rw_gio_out 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus0_out; -#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 -#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus1_out; -#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 -#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 - -/* Register r_gio_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_gio_in; -#define REG_RD_ADDR_iop_spu_r_gio_in 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus0_in; -#define REG_RD_ADDR_iop_spu_r_bus0_in 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus1_in; -#define REG_RD_ADDR_iop_spu_r_bus1_in 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_set; -#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 -#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_clr; -#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 -#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_rs_wr_stat; -#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_r_wr_stat; -#define REG_RD_ADDR_iop_spu_r_wr_stat 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; -#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 - -/* Register r_stat_in, scope iop_spu, type r */ -typedef struct { - unsigned int timer_grp_lo : 4; - unsigned int fifo_out_last : 1; - unsigned int fifo_out_rdy : 1; - unsigned int fifo_out_all : 1; - unsigned int fifo_in_rdy : 1; - unsigned int dmc_out_all : 1; - unsigned int dmc_out_dth : 1; - unsigned int dmc_out_eop : 1; - unsigned int dmc_out_dv : 1; - unsigned int dmc_out_last : 1; - unsigned int dmc_out_cmd_rq : 1; - unsigned int dmc_out_cmd_rdy : 1; - unsigned int pcrc_correct : 1; - unsigned int timer_grp_hi : 4; - unsigned int dmc_in_sth : 1; - unsigned int dmc_in_full : 1; - unsigned int dmc_in_cmd_rdy : 1; - unsigned int spu_gio_out : 4; - unsigned int sync_clk12 : 1; - unsigned int scrc_out_data : 1; - unsigned int scrc_in_err : 1; - unsigned int mc_busy : 1; - unsigned int mc_owned : 1; -} reg_iop_spu_r_stat_in; -#define REG_RD_ADDR_iop_spu_r_stat_in 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_trigger_in; -#define REG_RD_ADDR_iop_spu_r_trigger_in 132 - -/* Register r_special_stat, scope iop_spu, type r */ -typedef struct { - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int xor_bus0_r2_0 : 1; - unsigned int xor_bus1_r3_0 : 1; - unsigned int xor_bus0m_r2_0 : 1; - unsigned int xor_bus1m_r3_0 : 1; - unsigned int fsm_in0 : 1; - unsigned int fsm_in1 : 1; - unsigned int fsm_in2 : 1; - unsigned int fsm_in3 : 1; - unsigned int fsm_in4 : 1; - unsigned int fsm_in5 : 1; - unsigned int fsm_in6 : 1; - unsigned int fsm_in7 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int dummy1 : 12; -} reg_iop_spu_r_special_stat; -#define REG_RD_ADDR_iop_spu_r_special_stat 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 13; - unsigned int dummy1 : 3; - unsigned int imm_hi : 16; -} reg_iop_spu_rw_reg_access; -#define REG_RD_ADDR_iop_spu_rw_reg_access 140 -#define REG_WR_ADDR_iop_spu_rw_reg_access 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int src : 2; - unsigned int eq_en : 1; - unsigned int eq_inv : 1; - unsigned int gt_en : 1; - unsigned int gt_inv : 1; - unsigned int dummy1 : 14; -} reg_iop_spu_rw_event_cfg; -#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 -#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_mask; -#define REG_RD_ADDR_iop_spu_rw_event_mask 160 -#define REG_WR_ADDR_iop_spu_rw_event_mask 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_val; -#define REG_RD_ADDR_iop_spu_rw_event_val 176 -#define REG_WR_ADDR_iop_spu_rw_event_val 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_event_ret; -#define REG_RD_ADDR_iop_spu_rw_event_ret 192 -#define REG_WR_ADDR_iop_spu_rw_event_ret 192 - -/* Register r_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int seq_addr : 12; - unsigned int dummy1 : 2; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_trace; -#define REG_RD_ADDR_iop_spu_r_trace 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int tmr_done : 1; - unsigned int inp0 : 1; - unsigned int inp1 : 1; - unsigned int inp2 : 1; - unsigned int inp3 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int gio_out : 8; - unsigned int dummy1 : 1; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_fsm_trace; -#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 18; -} reg_iop_spu_rw_brp; -#define REG_RD_ADDR_iop_spu_rw_brp 204 -#define REG_WR_ADDR_iop_spu_rw_brp 204 - - -/* Constants */ -enum { - regk_iop_spu_attn_hi = 0x00000005, - regk_iop_spu_attn_lo = 0x00000005, - regk_iop_spu_attn_r0 = 0x00000000, - regk_iop_spu_attn_r1 = 0x00000001, - regk_iop_spu_attn_r10 = 0x00000002, - regk_iop_spu_attn_r11 = 0x00000003, - regk_iop_spu_attn_r12 = 0x00000004, - regk_iop_spu_attn_r13 = 0x00000005, - regk_iop_spu_attn_r14 = 0x00000006, - regk_iop_spu_attn_r15 = 0x00000007, - regk_iop_spu_attn_r2 = 0x00000002, - regk_iop_spu_attn_r3 = 0x00000003, - regk_iop_spu_attn_r4 = 0x00000004, - regk_iop_spu_attn_r5 = 0x00000005, - regk_iop_spu_attn_r6 = 0x00000006, - regk_iop_spu_attn_r7 = 0x00000007, - regk_iop_spu_attn_r8 = 0x00000000, - regk_iop_spu_attn_r9 = 0x00000001, - regk_iop_spu_c = 0x00000000, - regk_iop_spu_flag = 0x00000002, - regk_iop_spu_gio_in = 0x00000000, - regk_iop_spu_gio_out = 0x00000005, - regk_iop_spu_gio_out0 = 0x00000008, - regk_iop_spu_gio_out1 = 0x00000009, - regk_iop_spu_gio_out2 = 0x0000000a, - regk_iop_spu_gio_out3 = 0x0000000b, - regk_iop_spu_gio_out4 = 0x0000000c, - regk_iop_spu_gio_out5 = 0x0000000d, - regk_iop_spu_gio_out6 = 0x0000000e, - regk_iop_spu_gio_out7 = 0x0000000f, - regk_iop_spu_n = 0x00000003, - regk_iop_spu_no = 0x00000000, - regk_iop_spu_r0 = 0x00000008, - regk_iop_spu_r1 = 0x00000009, - regk_iop_spu_r10 = 0x0000000a, - regk_iop_spu_r11 = 0x0000000b, - regk_iop_spu_r12 = 0x0000000c, - regk_iop_spu_r13 = 0x0000000d, - regk_iop_spu_r14 = 0x0000000e, - regk_iop_spu_r15 = 0x0000000f, - regk_iop_spu_r2 = 0x0000000a, - regk_iop_spu_r3 = 0x0000000b, - regk_iop_spu_r4 = 0x0000000c, - regk_iop_spu_r5 = 0x0000000d, - regk_iop_spu_r6 = 0x0000000e, - regk_iop_spu_r7 = 0x0000000f, - regk_iop_spu_r8 = 0x00000008, - regk_iop_spu_r9 = 0x00000009, - regk_iop_spu_reg_hi = 0x00000002, - regk_iop_spu_reg_lo = 0x00000002, - regk_iop_spu_rw_brp_default = 0x00000000, - regk_iop_spu_rw_brp_size = 0x00000004, - regk_iop_spu_rw_ctrl_default = 0x00000000, - regk_iop_spu_rw_event_cfg_size = 0x00000004, - regk_iop_spu_rw_event_mask_size = 0x00000004, - regk_iop_spu_rw_event_val_size = 0x00000004, - regk_iop_spu_rw_gio_out_default = 0x00000000, - regk_iop_spu_rw_r_size = 0x00000010, - regk_iop_spu_rw_reg_access_default = 0x00000000, - regk_iop_spu_stat_in = 0x00000002, - regk_iop_spu_statin_hi = 0x00000004, - regk_iop_spu_statin_lo = 0x00000004, - regk_iop_spu_trig = 0x00000003, - regk_iop_spu_trigger = 0x00000006, - regk_iop_spu_v = 0x00000001, - regk_iop_spu_wsts_gioout_spec = 0x00000001, - regk_iop_spu_xor = 0x00000003, - regk_iop_spu_xor_bus0_r2_0 = 0x00000000, - regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, - regk_iop_spu_xor_bus1_r3_0 = 0x00000001, - regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, - regk_iop_spu_yes = 0x00000001, - regk_iop_spu_z = 0x00000002 -}; -#endif /* __iop_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index d7b6d75884d2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,1042 +0,0 @@ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus0_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus0_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus1_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus1_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_byte0 : 2; - unsigned int bus0_byte1 : 2; - unsigned int bus0_byte2 : 2; - unsigned int bus0_byte3 : 2; - unsigned int bus1_byte0 : 2; - unsigned int bus1_byte1 : 2; - unsigned int bus1_byte2 : 2; - unsigned int bus1_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_lo : 3; - unsigned int bus0_hi : 3; - unsigned int bus0_lo_oe : 3; - unsigned int bus0_hi_oe : 3; - unsigned int bus1_lo : 3; - unsigned int bus1_hi : 3; - unsigned int bus1_lo_oe : 3; - unsigned int bus1_hi_oe : 3; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 4; - unsigned int gio0_oe : 2; - unsigned int gio1 : 4; - unsigned int gio1_oe : 2; - unsigned int gio2 : 4; - unsigned int gio2_oe : 2; - unsigned int gio3 : 4; - unsigned int gio3_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 4; - unsigned int gio4_oe : 2; - unsigned int gio5 : 4; - unsigned int gio5_oe : 2; - unsigned int gio6 : 4; - unsigned int gio6_oe : 2; - unsigned int gio7 : 4; - unsigned int gio7_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 4; - unsigned int gio8_oe : 2; - unsigned int gio9 : 4; - unsigned int gio9_oe : 2; - unsigned int gio10 : 4; - unsigned int gio10_oe : 2; - unsigned int gio11 : 4; - unsigned int gio11_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 4; - unsigned int gio12_oe : 2; - unsigned int gio13 : 4; - unsigned int gio13_oe : 2; - unsigned int gio14 : 4; - unsigned int gio14_oe : 2; - unsigned int gio15 : 4; - unsigned int gio15_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 4; - unsigned int gio16_oe : 2; - unsigned int gio17 : 4; - unsigned int gio17_oe : 2; - unsigned int gio18 : 4; - unsigned int gio18_oe : 2; - unsigned int gio19 : 4; - unsigned int gio19_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 4; - unsigned int gio20_oe : 2; - unsigned int gio21 : 4; - unsigned int gio21_oe : 2; - unsigned int gio22 : 4; - unsigned int gio22_oe : 2; - unsigned int gio23 : 4; - unsigned int gio23_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 4; - unsigned int gio24_oe : 2; - unsigned int gio25 : 4; - unsigned int gio25_oe : 2; - unsigned int gio26 : 4; - unsigned int gio26_oe : 2; - unsigned int gio27 : 4; - unsigned int gio27_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 4; - unsigned int gio28_oe : 2; - unsigned int gio29 : 4; - unsigned int gio29_oe : 2; - unsigned int gio30 : 4; - unsigned int gio30_oe : 2; - unsigned int gio31 : 4; - unsigned int gio31_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc0_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc1_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out0_strb : 3; - unsigned int sdp_out1_strb : 3; - unsigned int sdp_in0_data : 3; - unsigned int sdp_in0_last : 2; - unsigned int sdp_in0_strb : 3; - unsigned int sdp_in1_data : 3; - unsigned int sdp_in1_last : 2; - unsigned int sdp_in1_strb : 3; - unsigned int dummy1 : 10; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus0 = 0x00000000, - regk_iop_sw_cfg_bus0_rot16 = 0x00000004, - regk_iop_sw_cfg_bus0_rot24 = 0x00000006, - regk_iop_sw_cfg_bus0_rot8 = 0x00000002, - regk_iop_sw_cfg_bus1 = 0x00000001, - regk_iop_sw_cfg_bus1_rot16 = 0x00000005, - regk_iop_sw_cfg_bus1_rot24 = 0x00000007, - regk_iop_sw_cfg_bus1_rot8 = 0x00000003, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_dmc0 = 0x00000000, - regk_iop_sw_cfg_dmc1 = 0x00000001, - regk_iop_sw_cfg_gated_clk0 = 0x00000010, - regk_iop_sw_cfg_gated_clk1 = 0x00000011, - regk_iop_sw_cfg_gated_clk2 = 0x00000012, - regk_iop_sw_cfg_gated_clk3 = 0x00000013, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in0 = 0x00000000, - regk_iop_sw_cfg_gio_in1 = 0x00000001, - regk_iop_sw_cfg_gio_in10 = 0x00000002, - regk_iop_sw_cfg_gio_in11 = 0x00000003, - regk_iop_sw_cfg_gio_in14 = 0x00000004, - regk_iop_sw_cfg_gio_in15 = 0x00000005, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in28 = 0x00000006, - regk_iop_sw_cfg_gio_in29 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, - regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_par0 = 0x00000000, - regk_iop_sw_cfg_par1 = 0x00000001, - regk_iop_sw_cfg_pdp_out0 = 0x00000002, - regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, - regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_pdp_out1 = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, - regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out0 = 0x00000008, - regk_iop_sw_cfg_sdp_out1 = 0x00000009, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu0 = 0x00000002, - regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu0_g0 = 0x0000000e, - regk_iop_sw_cfg_spu0_g1 = 0x0000000e, - regk_iop_sw_cfg_spu0_g2 = 0x0000000e, - regk_iop_sw_cfg_spu0_g3 = 0x0000000e, - regk_iop_sw_cfg_spu0_g4 = 0x0000000e, - regk_iop_sw_cfg_spu0_g5 = 0x0000000e, - regk_iop_sw_cfg_spu0_g6 = 0x0000000e, - regk_iop_sw_cfg_spu0_g7 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio0 = 0x00000000, - regk_iop_sw_cfg_spu0_gio1 = 0x00000001, - regk_iop_sw_cfg_spu0_gio2 = 0x00000000, - regk_iop_sw_cfg_spu0_gio5 = 0x00000005, - regk_iop_sw_cfg_spu0_gio6 = 0x00000006, - regk_iop_sw_cfg_spu0_gio7 = 0x00000007, - regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, - regk_iop_sw_cfg_spu1 = 0x00000003, - regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu1_g0 = 0x0000000f, - regk_iop_sw_cfg_spu1_g1 = 0x0000000f, - regk_iop_sw_cfg_spu1_g2 = 0x0000000f, - regk_iop_sw_cfg_spu1_g3 = 0x0000000f, - regk_iop_sw_cfg_spu1_g4 = 0x0000000f, - regk_iop_sw_cfg_spu1_g5 = 0x0000000f, - regk_iop_sw_cfg_spu1_g6 = 0x0000000f, - regk_iop_sw_cfg_spu1_g7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gio0 = 0x00000002, - regk_iop_sw_cfg_spu1_gio1 = 0x00000003, - regk_iop_sw_cfg_spu1_gio2 = 0x00000002, - regk_iop_sw_cfg_spu1_gio5 = 0x00000005, - regk_iop_sw_cfg_spu1_gio6 = 0x00000006, - regk_iop_sw_cfg_spu1_gio7 = 0x00000007, - regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, - regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, - regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, - regk_iop_sw_cfg_timer_grp2 = 0x00000000, - regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, - regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, - regk_iop_sw_cfg_timer_grp3 = 0x00000000, - regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, - regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000000, - regk_iop_sw_cfg_trig2_1 = 0x00000000, - regk_iop_sw_cfg_trig2_2 = 0x00000000, - regk_iop_sw_cfg_trig2_3 = 0x00000000, - regk_iop_sw_cfg_trig3_0 = 0x00000000, - regk_iop_sw_cfg_trig3_1 = 0x00000000, - regk_iop_sw_cfg_trig3_2 = 0x00000000, - regk_iop_sw_cfg_trig3_3 = 0x00000000, - regk_iop_sw_cfg_trig4_0 = 0x00000001, - regk_iop_sw_cfg_trig4_1 = 0x00000001, - regk_iop_sw_cfg_trig4_2 = 0x00000001, - regk_iop_sw_cfg_trig4_3 = 0x00000001, - regk_iop_sw_cfg_trig5_0 = 0x00000001, - regk_iop_sw_cfg_trig5_1 = 0x00000001, - regk_iop_sw_cfg_trig5_2 = 0x00000001, - regk_iop_sw_cfg_trig5_3 = 0x00000001, - regk_iop_sw_cfg_trig6_0 = 0x00000001, - regk_iop_sw_cfg_trig6_1 = 0x00000001, - regk_iop_sw_cfg_trig6_2 = 0x00000001, - regk_iop_sw_cfg_trig6_3 = 0x00000001, - regk_iop_sw_cfg_trig7_0 = 0x00000001, - regk_iop_sw_cfg_trig7_1 = 0x00000001, - regk_iop_sw_cfg_trig7_2 = 0x00000001, - regk_iop_sw_cfg_trig7_3 = 0x00000001 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index 5fed844b19e2..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,853 +0,0 @@ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr2_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr2; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_rw_intr3_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr3; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_masked_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index da718f2a8cad..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,893 +0,0 @@ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu0 = 0x00000002, - regk_iop_sw_mpu_spu1 = 0x00000003, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index b59dde4bd0d1..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,552 +0,0 @@ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: <not found> - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out1 : 1; - unsigned int dmc_in1 : 1; - unsigned int dummy1 : 8; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int other_spu_intr0 : 1; - unsigned int other_spu_intr1 : 1; - unsigned int other_spu_intr2 : 1; - unsigned int other_spu_intr3 : 1; - unsigned int other_spu_intr4 : 1; - unsigned int other_spu_intr5 : 1; - unsigned int other_spu_intr6 : 1; - unsigned int other_spu_intr7 : 1; - unsigned int other_spu_intr8 : 1; - unsigned int other_spu_intr9 : 1; - unsigned int other_spu_intr10 : 1; - unsigned int other_spu_intr11 : 1; - unsigned int other_spu_intr12 : 1; - unsigned int other_spu_intr13 : 1; - unsigned int other_spu_intr14 : 1; - unsigned int other_spu_intr15 : 1; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h deleted file mode 100644 index c994114f3b51..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __iop_timer_grp_defs_h -#define __iop_timer_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_timer_grp */ - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 1; - unsigned int trig : 2; - unsigned int clk_gen_div : 8; - unsigned int clk_div : 8; - unsigned int dummy1 : 13; -} reg_iop_timer_grp_rw_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int quota_lo : 15; - unsigned int quota_hi : 15; - unsigned int quota_hi_sel : 1; - unsigned int dummy1 : 1; -} reg_iop_timer_grp_rw_half_period; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -typedef unsigned int reg_iop_timer_grp_rw_half_period_len; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 3; - unsigned int strb : 2; - unsigned int run_mode : 2; - unsigned int out_mode : 1; - unsigned int active_on_tmr : 2; - unsigned int inv : 1; - unsigned int en_by_tmr : 2; - unsigned int dis_by_tmr : 2; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int rst_at_en_strb : 1; - unsigned int dummy1 : 14; -} reg_iop_timer_grp_rw_tmr_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_tmr_len; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int rst : 4; - unsigned int en : 4; - unsigned int dis : 4; - unsigned int strb : 4; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_cmd; -#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 -#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rs_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_r_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 -#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 -#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_intr; -#define REG_RD_ADDR_iop_timer_grp_r_intr 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_masked_intr; -#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 - - -/* Constants */ -enum { - regk_iop_timer_grp_clk200 = 0x00000000, - regk_iop_timer_grp_clk_gen = 0x00000002, - regk_iop_timer_grp_complete = 0x00000002, - regk_iop_timer_grp_div_clk200 = 0x00000001, - regk_iop_timer_grp_div_clk_gen = 0x00000003, - regk_iop_timer_grp_ext = 0x00000001, - regk_iop_timer_grp_hi = 0x00000000, - regk_iop_timer_grp_long_period = 0x00000001, - regk_iop_timer_grp_neg = 0x00000002, - regk_iop_timer_grp_no = 0x00000000, - regk_iop_timer_grp_once = 0x00000003, - regk_iop_timer_grp_pause = 0x00000001, - regk_iop_timer_grp_pos = 0x00000001, - regk_iop_timer_grp_pos_neg = 0x00000003, - regk_iop_timer_grp_pulse = 0x00000000, - regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rw_cfg_default = 0x00000002, - regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, - regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, - regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, - regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, - regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, - regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, - regk_iop_timer_grp_short_period = 0x00000000, - regk_iop_timer_grp_stop = 0x00000000, - regk_iop_timer_grp_tmr = 0x00000004, - regk_iop_timer_grp_toggle = 0x00000001, - regk_iop_timer_grp_yes = 0x00000001 -}; -#endif /* __iop_timer_grp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h deleted file mode 100644 index 36e44282399d..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h +++ /dev/null @@ -1,170 +0,0 @@ -#ifndef __iop_trigger_grp_defs_h -#define __iop_trigger_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_trigger_grp */ - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int action : 2; - unsigned int once : 1; - unsigned int trig : 3; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cfg; -#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int dis : 4; - unsigned int en : 4; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cmd; -#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 -#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 -#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 -#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_masked_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 - - -/* Constants */ -enum { - regk_iop_trigger_grp_fall = 0x00000002, - regk_iop_trigger_grp_fall_lo = 0x00000006, - regk_iop_trigger_grp_no = 0x00000000, - regk_iop_trigger_grp_off = 0x00000000, - regk_iop_trigger_grp_pulse = 0x00000000, - regk_iop_trigger_grp_rise = 0x00000001, - regk_iop_trigger_grp_rise_fall = 0x00000003, - regk_iop_trigger_grp_rise_fall_hi = 0x00000007, - regk_iop_trigger_grp_rise_fall_lo = 0x00000004, - regk_iop_trigger_grp_rise_hi = 0x00000005, - regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, - regk_iop_trigger_grp_rw_cfg_size = 0x00000004, - regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, - regk_iop_trigger_grp_toggle = 0x00000003, - regk_iop_trigger_grp_yes = 0x00000001 -}; -#endif /* __iop_trigger_grp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h deleted file mode 100644 index b8d6a910c71c..000000000000 --- a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v1_0 = 0x00000001 -}; -#endif /* __iop_version_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h deleted file mode 100644 index 7b167e3c0572..000000000000 --- a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __irq_nmi_defs_h -#define __irq_nmi_defs_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: <not found> - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope irq_nmi */ - -/* Register rw_cmd, scope irq_nmi, type rw */ -typedef struct { - unsigned int delay : 16; - unsigned int op : 2; - unsigned int dummy1 : 14; -} reg_irq_nmi_rw_cmd; -#define REG_RD_ADDR_irq_nmi_rw_cmd 0 -#define REG_WR_ADDR_irq_nmi_rw_cmd 0 - - -/* Constants */ -enum { - regk_irq_nmi_ack_irq = 0x00000002, - regk_irq_nmi_ack_nmi = 0x00000003, - regk_irq_nmi_irq = 0x00000000, - regk_irq_nmi_nmi = 0x00000001 -}; -#endif /* __irq_nmi_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h deleted file mode 100644 index a11fdd3cd907..000000000000 --- a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,205 +0,0 @@ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h deleted file mode 100644 index 71e8af0bb3a4..000000000000 --- a/include/asm-cris/arch-v32/hwregs/marb_defs.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h deleted file mode 100644 index 9d91c2de1b07..000000000000 --- a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h +++ /dev/null @@ -1,357 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h deleted file mode 100644 index 236f91efe7e8..000000000000 --- a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Read/write register macros used by *_defs.h - */ - -#ifndef reg_rdwr_h -#define reg_rdwr_h - -#ifndef REG_READ -#define REG_READ(type, addr) (*((volatile type *) (addr))) -#endif - -#ifndef REG_WRITE -#define REG_WRITE(type, addr, val) \ - do { *((volatile type *) (addr)) = (val); } while(0) -#endif - -#endif diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h deleted file mode 100644 index d9f0e924fb23..000000000000 --- a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h +++ /dev/null @@ -1,173 +0,0 @@ -#ifndef __rt_trace_defs_h -#define __rt_trace_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope rt_trace */ - -/* Register rw_cfg, scope rt_trace, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int mode : 1; - unsigned int owner : 1; - unsigned int wp : 1; - unsigned int stall : 1; - unsigned int dummy1 : 3; - unsigned int wp_start : 7; - unsigned int dummy2 : 1; - unsigned int wp_stop : 7; - unsigned int dummy3 : 9; -} reg_rt_trace_rw_cfg; -#define REG_RD_ADDR_rt_trace_rw_cfg 0 -#define REG_WR_ADDR_rt_trace_rw_cfg 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -typedef struct { - unsigned int ack_data : 1; - unsigned int ack_guru : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_rw_tap_ctrl; -#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 -#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -typedef struct { - unsigned int dav : 1; - unsigned int empty : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_r_tap_stat; -#define REG_RD_ADDR_rt_trace_r_tap_stat 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -typedef unsigned int reg_rt_trace_rw_tap_data; -#define REG_RD_ADDR_rt_trace_rw_tap_data 12 -#define REG_WR_ADDR_rt_trace_rw_tap_data 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -typedef struct { - unsigned int op : 4; - unsigned int sub_op : 4; - unsigned int dummy1 : 24; -} reg_rt_trace_rw_tap_hdata; -#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 -#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 - -/* Register r_redir, scope rt_trace, type r */ -typedef unsigned int reg_rt_trace_r_redir; -#define REG_RD_ADDR_rt_trace_r_redir 20 - - -/* Constants */ -enum { - regk_rt_trace_brk = 0x0000000c, - regk_rt_trace_dbg = 0x00000003, - regk_rt_trace_dbgdi = 0x00000004, - regk_rt_trace_dbgdo = 0x00000005, - regk_rt_trace_gmode = 0x00000000, - regk_rt_trace_no = 0x00000000, - regk_rt_trace_nop = 0x00000000, - regk_rt_trace_normal = 0x00000000, - regk_rt_trace_rdmem = 0x00000007, - regk_rt_trace_rdmemb = 0x00000009, - regk_rt_trace_rdpreg = 0x00000002, - regk_rt_trace_rdreg = 0x00000001, - regk_rt_trace_rdsreg = 0x00000003, - regk_rt_trace_redir = 0x00000006, - regk_rt_trace_ret = 0x0000000b, - regk_rt_trace_rw_cfg_default = 0x00000000, - regk_rt_trace_trcfg = 0x00000001, - regk_rt_trace_wp = 0x00000001, - regk_rt_trace_wp0 = 0x00000001, - regk_rt_trace_wp1 = 0x00000002, - regk_rt_trace_wp2 = 0x00000004, - regk_rt_trace_wp3 = 0x00000008, - regk_rt_trace_wp4 = 0x00000010, - regk_rt_trace_wp5 = 0x00000020, - regk_rt_trace_wp6 = 0x00000040, - regk_rt_trace_wrmem = 0x00000008, - regk_rt_trace_wrmemb = 0x0000000a, - regk_rt_trace_wrpreg = 0x00000005, - regk_rt_trace_wrreg = 0x00000004, - regk_rt_trace_wrsreg = 0x00000006, - regk_rt_trace_yes = 0x00000001 -}; -#endif /* __rt_trace_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h deleted file mode 100644 index 01c2fab97d43..000000000000 --- a/include/asm-cris/arch-v32/hwregs/ser_defs.h +++ /dev/null @@ -1,308 +0,0 @@ -#ifndef __ser_defs_h -#define __ser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ser */ - -/* Register rw_tr_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int stop_bits : 1; - unsigned int stop : 1; - unsigned int rts_delay : 3; - unsigned int rts_setup : 1; - unsigned int auto_rts : 1; - unsigned int txd : 1; - unsigned int auto_cts : 1; - unsigned int dummy1 : 15; -} reg_ser_rw_tr_ctrl; -#define REG_RD_ADDR_ser_rw_tr_ctrl 0 -#define REG_WR_ADDR_ser_rw_tr_ctrl 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_tr_dma_en; -#define REG_RD_ADDR_ser_rw_tr_dma_en 4 -#define REG_WR_ADDR_ser_rw_tr_dma_en 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int dma_mode : 1; - unsigned int dma_err : 1; - unsigned int sampling : 1; - unsigned int timeout : 3; - unsigned int auto_eop : 1; - unsigned int half_duplex : 1; - unsigned int rts_n : 1; - unsigned int loopback : 1; - unsigned int dummy1 : 14; -} reg_ser_rw_rec_ctrl; -#define REG_RD_ADDR_ser_rw_rec_ctrl 8 -#define REG_WR_ADDR_ser_rw_rec_ctrl 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_tr_baud_div; -#define REG_RD_ADDR_ser_rw_tr_baud_div 12 -#define REG_WR_ADDR_ser_rw_tr_baud_div 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_rec_baud_div; -#define REG_RD_ADDR_ser_rw_rec_baud_div 16 -#define REG_WR_ADDR_ser_rw_rec_baud_div 16 - -/* Register rw_xoff, scope ser, type rw */ -typedef struct { - unsigned int chr : 8; - unsigned int automatic : 1; - unsigned int dummy1 : 23; -} reg_ser_rw_xoff; -#define REG_RD_ADDR_ser_rw_xoff 20 -#define REG_WR_ADDR_ser_rw_xoff 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_xoff_clr; -#define REG_RD_ADDR_ser_rw_xoff_clr 24 -#define REG_WR_ADDR_ser_rw_xoff_clr 24 - -/* Register rw_dout, scope ser, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_ser_rw_dout; -#define REG_RD_ADDR_ser_rw_dout 28 -#define REG_WR_ADDR_ser_rw_dout 28 - -/* Register rs_stat_din, scope ser, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_rs_stat_din; -#define REG_RD_ADDR_ser_rs_stat_din 32 - -/* Register r_stat_din, scope ser, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_r_stat_din; -#define REG_RD_ADDR_ser_r_stat_din 36 - -/* Register rw_rec_eop, scope ser, type rw */ -typedef struct { - unsigned int set : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_rec_eop; -#define REG_RD_ADDR_ser_rw_rec_eop 40 -#define REG_WR_ADDR_ser_rw_rec_eop 40 - -/* Register rw_intr_mask, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_intr_mask; -#define REG_RD_ADDR_ser_rw_intr_mask 44 -#define REG_WR_ADDR_ser_rw_intr_mask 44 - -/* Register rw_ack_intr, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_ack_intr; -#define REG_RD_ADDR_ser_rw_ack_intr 48 -#define REG_WR_ADDR_ser_rw_ack_intr 48 - -/* Register r_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_intr; -#define REG_RD_ADDR_ser_r_intr 52 - -/* Register r_masked_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_masked_intr; -#define REG_RD_ADDR_ser_r_masked_intr 56 - - -/* Constants */ -enum { - regk_ser_active = 0x00000000, - regk_ser_bits1 = 0x00000000, - regk_ser_bits2 = 0x00000001, - regk_ser_bits7 = 0x00000001, - regk_ser_bits8 = 0x00000000, - regk_ser_del0_5 = 0x00000000, - regk_ser_del1 = 0x00000001, - regk_ser_del1_5 = 0x00000002, - regk_ser_del2 = 0x00000003, - regk_ser_del2_5 = 0x00000004, - regk_ser_del3 = 0x00000005, - regk_ser_del3_5 = 0x00000006, - regk_ser_del4 = 0x00000007, - regk_ser_even = 0x00000000, - regk_ser_ext = 0x00000001, - regk_ser_f100 = 0x00000007, - regk_ser_f29_493 = 0x00000004, - regk_ser_f32 = 0x00000005, - regk_ser_f32_768 = 0x00000006, - regk_ser_ignore = 0x00000001, - regk_ser_inactive = 0x00000001, - regk_ser_majority = 0x00000001, - regk_ser_mark = 0x00000002, - regk_ser_middle = 0x00000000, - regk_ser_no = 0x00000000, - regk_ser_odd = 0x00000001, - regk_ser_off = 0x00000000, - regk_ser_rw_intr_mask_default = 0x00000000, - regk_ser_rw_rec_baud_div_default = 0x00000000, - regk_ser_rw_rec_ctrl_default = 0x00010000, - regk_ser_rw_tr_baud_div_default = 0x00000000, - regk_ser_rw_tr_ctrl_default = 0x00008000, - regk_ser_rw_tr_dma_en_default = 0x00000000, - regk_ser_rw_xoff_default = 0x00000000, - regk_ser_space = 0x00000003, - regk_ser_stop = 0x00000000, - regk_ser_yes = 0x00000001 -}; -#endif /* __ser_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h deleted file mode 100644 index 8d1dab218b91..000000000000 --- a/include/asm-cris/arch-v32/hwregs/sser_defs.h +++ /dev/null @@ -1,331 +0,0 @@ -#ifndef __sser_defs_h -#define __sser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope sser */ - -/* Register rw_cfg, scope sser, type rw */ -typedef struct { - unsigned int clk_div : 16; - unsigned int base_freq : 3; - unsigned int gate_clk : 1; - unsigned int clkgate_ctrl : 1; - unsigned int clkgate_in : 1; - unsigned int clk_dir : 1; - unsigned int clk_od_mode : 1; - unsigned int out_clk_pol : 1; - unsigned int out_clk_src : 2; - unsigned int clk_in_sel : 1; - unsigned int hold_pol : 1; - unsigned int prepare : 1; - unsigned int en : 1; - unsigned int dummy1 : 1; -} reg_sser_rw_cfg; -#define REG_RD_ADDR_sser_rw_cfg 0 -#define REG_WR_ADDR_sser_rw_cfg 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -typedef struct { - unsigned int wordrate : 10; - unsigned int rec_delay : 3; - unsigned int tr_delay : 3; - unsigned int early_wend : 1; - unsigned int level : 2; - unsigned int type : 1; - unsigned int clk_pol : 1; - unsigned int fr_in_rxclk : 1; - unsigned int clk_src : 1; - unsigned int out_off : 1; - unsigned int out_on : 1; - unsigned int frame_pin_dir : 1; - unsigned int frame_pin_use : 2; - unsigned int status_pin_dir : 1; - unsigned int status_pin_use : 2; - unsigned int dummy1 : 1; -} reg_sser_rw_frm_cfg; -#define REG_RD_ADDR_sser_rw_frm_cfg 4 -#define REG_WR_ADDR_sser_rw_frm_cfg 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -typedef struct { - unsigned int tr_en : 1; - unsigned int stop : 1; - unsigned int urun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 1; - unsigned int use60958 : 1; - unsigned int iec60958_ckdiv : 2; - unsigned int rate_ctrl : 1; - unsigned int use_md : 1; - unsigned int dual_i2s : 1; - unsigned int data_pin_use : 2; - unsigned int od_mode : 1; - unsigned int bulk_wspace : 2; - unsigned int dummy1 : 4; -} reg_sser_rw_tr_cfg; -#define REG_RD_ADDR_sser_rw_tr_cfg 8 -#define REG_WR_ADDR_sser_rw_tr_cfg 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -typedef struct { - unsigned int rec_en : 1; - unsigned int force_eop : 1; - unsigned int stop : 1; - unsigned int orun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 2; - unsigned int use60958 : 1; - unsigned int iec60958_ui_len : 5; - unsigned int slave2_en : 1; - unsigned int slave3_en : 1; - unsigned int fifo_thr : 2; - unsigned int dummy1 : 3; -} reg_sser_rw_rec_cfg; -#define REG_RD_ADDR_sser_rw_rec_cfg 12 -#define REG_WR_ADDR_sser_rw_rec_cfg 12 - -/* Register rw_tr_data, scope sser, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int dummy1 : 15; -} reg_sser_rw_tr_data; -#define REG_RD_ADDR_sser_rw_tr_data 16 -#define REG_WR_ADDR_sser_rw_tr_data 16 - -/* Register r_rec_data, scope sser, type r */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int ext_clk : 1; - unsigned int status_in : 1; - unsigned int frame_in : 1; - unsigned int din : 1; - unsigned int data_in : 1; - unsigned int clk_in : 1; - unsigned int dummy1 : 9; -} reg_sser_r_rec_data; -#define REG_RD_ADDR_sser_r_rec_data 20 - -/* Register rw_extra, scope sser, type rw */ -typedef struct { - unsigned int clkoff_cycles : 20; - unsigned int clkoff_en : 1; - unsigned int clkon_en : 1; - unsigned int dout_delay : 5; - unsigned int dummy1 : 5; -} reg_sser_rw_extra; -#define REG_RD_ADDR_sser_rw_extra 24 -#define REG_WR_ADDR_sser_rw_extra 24 - -/* Register rw_intr_mask, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_intr_mask; -#define REG_RD_ADDR_sser_rw_intr_mask 28 -#define REG_WR_ADDR_sser_rw_intr_mask 28 - -/* Register rw_ack_intr, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_ack_intr; -#define REG_RD_ADDR_sser_rw_ack_intr 32 -#define REG_WR_ADDR_sser_rw_ack_intr 32 - -/* Register r_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_intr; -#define REG_RD_ADDR_sser_r_intr 36 - -/* Register r_masked_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_masked_intr; -#define REG_RD_ADDR_sser_r_masked_intr 40 - - -/* Constants */ -enum { - regk_sser_both = 0x00000002, - regk_sser_bulk = 0x00000001, - regk_sser_clk100 = 0x00000000, - regk_sser_clk_in = 0x00000000, - regk_sser_const0 = 0x00000003, - regk_sser_dout = 0x00000002, - regk_sser_edge = 0x00000000, - regk_sser_ext = 0x00000001, - regk_sser_ext_clk = 0x00000001, - regk_sser_f100 = 0x00000000, - regk_sser_f29_493 = 0x00000004, - regk_sser_f32 = 0x00000005, - regk_sser_f32_768 = 0x00000006, - regk_sser_frm = 0x00000003, - regk_sser_gio0 = 0x00000000, - regk_sser_gio1 = 0x00000001, - regk_sser_hispeed = 0x00000001, - regk_sser_hold = 0x00000002, - regk_sser_in = 0x00000000, - regk_sser_inf = 0x00000003, - regk_sser_intern = 0x00000000, - regk_sser_intern_clk = 0x00000001, - regk_sser_intern_tb = 0x00000000, - regk_sser_iso = 0x00000000, - regk_sser_level = 0x00000001, - regk_sser_lospeed = 0x00000000, - regk_sser_lsbfirst = 0x00000000, - regk_sser_msbfirst = 0x00000001, - regk_sser_neg = 0x00000001, - regk_sser_neg_lo = 0x00000000, - regk_sser_no = 0x00000000, - regk_sser_no_clk = 0x00000007, - regk_sser_nojitter = 0x00000002, - regk_sser_out = 0x00000001, - regk_sser_pos = 0x00000000, - regk_sser_pos_hi = 0x00000001, - regk_sser_rec = 0x00000000, - regk_sser_rw_cfg_default = 0x00000000, - regk_sser_rw_extra_default = 0x00000000, - regk_sser_rw_frm_cfg_default = 0x00000000, - regk_sser_rw_intr_mask_default = 0x00000000, - regk_sser_rw_rec_cfg_default = 0x00000000, - regk_sser_rw_tr_cfg_default = 0x01800000, - regk_sser_rw_tr_data_default = 0x00000000, - regk_sser_thr16 = 0x00000001, - regk_sser_thr32 = 0x00000002, - regk_sser_thr8 = 0x00000000, - regk_sser_tr = 0x00000001, - regk_sser_ts_out = 0x00000003, - regk_sser_tx_bulk = 0x00000002, - regk_sser_wiresave = 0x00000002, - regk_sser_yes = 0x00000001 -}; -#endif /* __sser_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h deleted file mode 100644 index 35131ba466f3..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strcop.h +++ /dev/null @@ -1,57 +0,0 @@ -// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ - -// Streamcop meta-data configuration structs - -struct strcop_meta_out { - unsigned char csumsel : 3; - unsigned char ciphsel : 3; - unsigned char ciphconf : 2; - unsigned char hashsel : 3; - unsigned char hashconf : 1; - unsigned char hashmode : 1; - unsigned char decrypt : 1; - unsigned char dlkey : 1; - unsigned char cbcmode : 1; -}; - -struct strcop_meta_in { - unsigned char dmasel : 3; - unsigned char sync : 1; - unsigned char res1 : 5; - unsigned char res2; -}; - -// Source definitions - -enum { - src_none = 0, - src_dma = 1, - src_des = 2, - src_sha1 = 3, - src_csum = 4, - src_aes = 5, - src_md5 = 6, - src_res = 7 -}; - -// Cipher definitions - -enum { - ciph_des = 0, - ciph_3des = 1, - ciph_aes = 2 -}; - -// Hash definitions - -enum { - hash_sha1 = 0, - hash_md5 = 1 -}; - -enum { - hash_noiv = 0, - hash_iv = 1 -}; - - diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h deleted file mode 100644 index bd145a49b2c4..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strcop_defs.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __strcop_defs_h -#define __strcop_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strcop */ - -/* Register rw_cfg, scope strcop, type rw */ -typedef struct { - unsigned int td3 : 1; - unsigned int td2 : 1; - unsigned int td1 : 1; - unsigned int ipend : 1; - unsigned int ignore_sync : 1; - unsigned int en : 1; - unsigned int dummy1 : 26; -} reg_strcop_rw_cfg; -#define REG_RD_ADDR_strcop_rw_cfg 0 -#define REG_WR_ADDR_strcop_rw_cfg 0 - - -/* Constants */ -enum { - regk_strcop_big = 0x00000001, - regk_strcop_d = 0x00000001, - regk_strcop_e = 0x00000000, - regk_strcop_little = 0x00000000, - regk_strcop_rw_cfg_default = 0x00000002 -}; -#endif /* __strcop_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h deleted file mode 100644 index 67474855c499..000000000000 --- a/include/asm-cris/arch-v32/hwregs/strmux_defs.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h deleted file mode 100644 index ffe49625ae36..000000000000 --- a/include/asm-cris/arch-v32/hwregs/supp_reg.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef __SUPP_REG_H__ -#define __SUPP_REG_H__ - -/* Macros for reading and writing support/special registers. */ - -#ifndef STRINGIFYFY -#define STRINGIFYFY(i) #i -#endif - -#ifndef STRINGIFY -#define STRINGIFY(i) STRINGIFYFY(i) -#endif - -#define SPEC_REG_BZ "BZ" -#define SPEC_REG_VR "VR" -#define SPEC_REG_PID "PID" -#define SPEC_REG_SRS "SRS" -#define SPEC_REG_WZ "WZ" -#define SPEC_REG_EXS "EXS" -#define SPEC_REG_EDA "EDA" -#define SPEC_REG_MOF "MOF" -#define SPEC_REG_DZ "DZ" -#define SPEC_REG_EBP "EBP" -#define SPEC_REG_ERP "ERP" -#define SPEC_REG_SRP "SRP" -#define SPEC_REG_NRP "NRP" -#define SPEC_REG_CCS "CCS" -#define SPEC_REG_USP "USP" -#define SPEC_REG_SPC "SPC" - -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define RW_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 -#define RW_MM_TLB_PGD 7 - -#define BANK_GC 0 -#define BANK_IM 1 -#define BANK_DM 2 -#define BANK_BP 3 - -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_R0 8 -#define RW_GC_R1 9 - -#define SPEC_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $" r : : "r" (v)); - -#define SPEC_REG_RD(r,v) \ -__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); - -#define NOP() \ - __asm__ __volatile__ ("nop"); - -#define SUPP_BANK_SEL(b) \ - SPEC_REG_WR(SPEC_REG_SRS,b); \ - NOP(); \ - NOP(); \ - NOP(); - -#define SUPP_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - : : "r" (v)); - -#define SUPP_REG_RD(r,v) \ -__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); - -#endif /* __SUPP_REG_H__ */ diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h deleted file mode 100644 index c0ada33bf90f..000000000000 --- a/include/asm-cris/arch-v32/intmem.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_INTMEM_H -#define _ASM_CRIS_INTMEM_H - -void* crisv32_intmem_alloc(unsigned size, unsigned align); -void crisv32_intmem_free(void* addr); -void* crisv32_intmem_phys_to_virt(unsigned long addr); -unsigned long crisv32_intmem_virt_to_phys(void *addr); - -#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h deleted file mode 100644 index 72024452cea9..000000000000 --- a/include/asm-cris/arch-v32/io.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_IO_H -#define _ASM_ARCH_CRIS_IO_H - -#include <linux/spinlock.h> -#include <hwregs/reg_map.h> -#include <hwregs/reg_rdwr.h> -#include <hwregs/gio_defs.h> - -enum crisv32_io_dir -{ - crisv32_io_dir_in = 0, - crisv32_io_dir_out = 1 -}; - -struct crisv32_ioport -{ - volatile unsigned long *oe; - volatile unsigned long *data; - volatile unsigned long *data_in; - unsigned int pin_count; - spinlock_t lock; -}; - -struct crisv32_iopin -{ - struct crisv32_ioport* port; - int bit; -}; - -extern struct crisv32_ioport crisv32_ioports[]; - -extern struct crisv32_iopin crisv32_led1_green; -extern struct crisv32_iopin crisv32_led1_red; -extern struct crisv32_iopin crisv32_led2_green; -extern struct crisv32_iopin crisv32_led2_red; -extern struct crisv32_iopin crisv32_led3_green; -extern struct crisv32_iopin crisv32_led3_red; - -extern struct crisv32_iopin crisv32_led_net0_green; -extern struct crisv32_iopin crisv32_led_net0_red; -extern struct crisv32_iopin crisv32_led_net1_green; -extern struct crisv32_iopin crisv32_led_net1_red; - -static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) -{ - unsigned long flags; - spin_lock_irqsave(&iopin->port->lock, flags); - - if (val) - *iopin->port->data |= iopin->bit; - else - *iopin->port->data &= ~iopin->bit; - - spin_unlock_irqrestore(&iopin->port->lock, flags); -} - -static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, - enum crisv32_io_dir dir) -{ - unsigned long flags; - spin_lock_irqsave(&iopin->port->lock, flags); - - if (dir == crisv32_io_dir_in) - *iopin->port->oe &= ~iopin->bit; - else - *iopin->port->oe |= iopin->bit; - - spin_unlock_irqrestore(&iopin->port->lock, flags); -} - -static inline int crisv32_io_rd(struct crisv32_iopin* iopin) -{ - return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); -} - -int crisv32_io_get(struct crisv32_iopin* iopin, - unsigned int port, unsigned int pin); -int crisv32_io_get_name(struct crisv32_iopin* iopin, - const char *name); - -#define CRIS_LED_OFF 0x00 -#define CRIS_LED_GREEN 0x01 -#define CRIS_LED_RED 0x02 -#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) - -#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) -#define CRIS_LED_NETWORK_GRP0_SET(x) \ - do { \ - CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#else -#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} -#endif - -#define CRIS_LED_NETWORK_GRP0_SET_G(x) \ - crisv32_io_set(&crisv32_led_net0_green, !(x)); - -#define CRIS_LED_NETWORK_GRP0_SET_R(x) \ - crisv32_io_set(&crisv32_led_net0_red, !(x)); - -#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) -#define CRIS_LED_NETWORK_GRP1_SET(x) \ - do { \ - CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#else -#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} -#endif - -#define CRIS_LED_NETWORK_GRP1_SET_G(x) \ - crisv32_io_set(&crisv32_led_net1_green, !(x)); - -#define CRIS_LED_NETWORK_GRP1_SET_R(x) \ - crisv32_io_set(&crisv32_led_net1_red, !(x)); - -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ - } while (0) - -#define CRIS_LED_ACTIVE_SET_G(x) \ - crisv32_io_set(&crisv32_led2_green, !(x)); -#define CRIS_LED_ACTIVE_SET_R(x) \ - crisv32_io_set(&crisv32_led2_red, !(x)); -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - crisv32_io_set(&crisv32_led3_green, !(x)); \ - crisv32_io_set(&crisv32_led3_red, !(x)); \ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - crisv32_io_set(&crisv32_led3_green, !(x)); - -#endif diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h deleted file mode 100644 index 9e4c9fbdfddf..000000000000 --- a/include/asm-cris/arch-v32/irq.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include <hwregs/intr_vect.h> - -/* Number of non-cpu interrupts. */ -#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ -#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ -#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ -#if NR_REAL_IRQS > 32 -#define MACH_IRQS 64 -#else -#define MACH_IRQS 32 -#endif - -#ifndef __ASSEMBLY__ -/* Global IRQ vector. */ -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ - -void mask_irq(int irq); -void unmask_irq(int irq); - -void set_exception_vector(int n, irqvectptr addr); - -/* Save registers so that they match pt_regs. */ -#define SAVE_ALL \ - "subq 12,$sp\n\t" \ - "move $erp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $ccs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $spc,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $mof,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $acr,[$sp]\n\t" \ - "subq 14*4,$sp\n\t" \ - "movem $r13,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $r10,[$sp]\n" - -#define STR2(x) #x -#define STR(x) STR2(x) - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) - -/* - * The reason for setting the S-bit when debugging the kernel is that we want - * hardware breakpoints to remain active while we are in an exception handler. - * Note that we cannot simply copy S1, since we may come here from user-space, - * or any context where the S-bit wasn't set. - */ -#ifdef CONFIG_ETRAX_KGDB -#define KGDB_FIXUP \ - "move $ccs, $r10\n\t" \ - "or.d (1<<9), $r10\n\t" \ - "move $r10, $ccs\n\t" -#else -#define KGDB_FIXUP "" -#endif - -/* - * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock - * and jump to ret_from_intr which is found in entry.S. - * - * The reason for blocking the IRQ is to allow an sti() before the handler, - * which will acknowledge the interrupt, is run. The actual blocking is made - * by crisv32_do_IRQ. - */ -#define BUILD_IRQ(nr) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp, $r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 1, $r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); -/* - * This is subtle. The timer interrupt is crucial and it should not be disabled - * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it - * would have been BLOCK'ed, and then softirq's are run before we return here to - * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run - * and the watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the - * multiple_irq handler is run and it prioritizes the timer interrupt. However - * if we had BLOCK'edit here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt is - * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not - * be an sti() before the timer irq handler is run to acknowledge the interrupt. - */ -#define BUILD_TIMER_IRQ(nr, mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp,$r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 0,$r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_ARCH_IRQ_H */ diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h deleted file mode 100644 index 65e9d6ff0520..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/arbiter.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x7fe, - arbiter_cpu = 0x1800, - arbiter_all_clients = 0x7fff -}; - -enum { - arbiter_bar_all_clients = 0x1ff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h deleted file mode 100644 index 9e8eb13b601d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/dma.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ - -enum dma_owner { - dma_eth, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_ser4, - dma_iop, - dma_sser, - dma_strp, - dma_h264, - dma_jpeg -}; - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned bandwidth, enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h deleted file mode 100644 index 02855adf63e8..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef __clkgen_defs_asm_h -#define __clkgen_defs_asm_h - -/* - * This file is autogenerated from - * file: clkgen.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope clkgen, type r */ -#define reg_clkgen_r_bootsel___boot_mode___lsb 0 -#define reg_clkgen_r_bootsel___boot_mode___width 5 -#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 -#define reg_clkgen_r_bootsel___intern_main_clk___width 1 -#define reg_clkgen_r_bootsel___intern_main_clk___bit 5 -#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 -#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 -#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 -#define reg_clkgen_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope clkgen, type rw */ -#define reg_clkgen_rw_clk_ctrl___pll___lsb 0 -#define reg_clkgen_rw_clk_ctrl___pll___width 1 -#define reg_clkgen_rw_clk_ctrl___pll___bit 0 -#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 -#define reg_clkgen_rw_clk_ctrl___cpu___width 1 -#define reg_clkgen_rw_clk_ctrl___cpu___bit 1 -#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 -#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 -#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 -#define reg_clkgen_rw_clk_ctrl___vin___lsb 3 -#define reg_clkgen_rw_clk_ctrl___vin___width 1 -#define reg_clkgen_rw_clk_ctrl___vin___bit 3 -#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 -#define reg_clkgen_rw_clk_ctrl___sclr___width 1 -#define reg_clkgen_rw_clk_ctrl___sclr___bit 4 -#define reg_clkgen_rw_clk_ctrl___h264___lsb 5 -#define reg_clkgen_rw_clk_ctrl___h264___width 1 -#define reg_clkgen_rw_clk_ctrl___h264___bit 5 -#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 -#define reg_clkgen_rw_clk_ctrl___ddr2___width 1 -#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 -#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 -#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 -#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 -#define reg_clkgen_rw_clk_ctrl___eth___lsb 8 -#define reg_clkgen_rw_clk_ctrl___eth___width 1 -#define reg_clkgen_rw_clk_ctrl___eth___bit 8 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 -#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 -#define reg_clkgen_rw_clk_ctrl___jpeg___width 1 -#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 -#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 -#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 -#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 -#define reg_clkgen_rw_clk_ctrl_offset 4 - - -/* Constants */ -#define regk_clkgen_eth1000_rx 0x0000000c -#define regk_clkgen_eth1000_tx 0x0000000e -#define regk_clkgen_eth100_rx 0x0000001d -#define regk_clkgen_eth100_rx_half 0x0000001c -#define regk_clkgen_eth100_tx 0x0000001f -#define regk_clkgen_eth100_tx_half 0x0000001e -#define regk_clkgen_nand_3_2 0x00000000 -#define regk_clkgen_nand_3_2_0x30 0x00000002 -#define regk_clkgen_nand_3_2_0x30_pll 0x00000012 -#define regk_clkgen_nand_3_2_pll 0x00000010 -#define regk_clkgen_nand_3_3 0x00000001 -#define regk_clkgen_nand_3_3_0x30 0x00000003 -#define regk_clkgen_nand_3_3_0x30_pll 0x00000013 -#define regk_clkgen_nand_3_3_pll 0x00000011 -#define regk_clkgen_nand_4_2 0x00000004 -#define regk_clkgen_nand_4_2_0x30 0x00000006 -#define regk_clkgen_nand_4_2_0x30_pll 0x00000016 -#define regk_clkgen_nand_4_2_pll 0x00000014 -#define regk_clkgen_nand_4_3 0x00000005 -#define regk_clkgen_nand_4_3_0x30 0x00000007 -#define regk_clkgen_nand_4_3_0x30_pll 0x00000017 -#define regk_clkgen_nand_4_3_pll 0x00000015 -#define regk_clkgen_nand_5_2 0x00000008 -#define regk_clkgen_nand_5_2_0x30 0x0000000a -#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a -#define regk_clkgen_nand_5_2_pll 0x00000018 -#define regk_clkgen_nand_5_3 0x00000009 -#define regk_clkgen_nand_5_3_0x30 0x0000000b -#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b -#define regk_clkgen_nand_5_3_pll 0x00000019 -#define regk_clkgen_no 0x00000000 -#define regk_clkgen_rw_clk_ctrl_default 0x00000002 -#define regk_clkgen_ser 0x0000000d -#define regk_clkgen_ser_pll 0x0000000f -#define regk_clkgen_yes 0x00000001 -#endif /* __clkgen_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h deleted file mode 100644 index b12be03edacb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h +++ /dev/null @@ -1,266 +0,0 @@ -#ifndef __ddr2_defs_asm_h -#define __ddr2_defs_asm_h - -/* - * This file is autogenerated from - * file: ddr2.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope ddr2, type rw */ -#define reg_ddr2_rw_cfg___col_width___lsb 0 -#define reg_ddr2_rw_cfg___col_width___width 4 -#define reg_ddr2_rw_cfg___nr_banks___lsb 4 -#define reg_ddr2_rw_cfg___nr_banks___width 1 -#define reg_ddr2_rw_cfg___nr_banks___bit 4 -#define reg_ddr2_rw_cfg___bw___lsb 5 -#define reg_ddr2_rw_cfg___bw___width 1 -#define reg_ddr2_rw_cfg___bw___bit 5 -#define reg_ddr2_rw_cfg___nr_ref___lsb 6 -#define reg_ddr2_rw_cfg___nr_ref___width 4 -#define reg_ddr2_rw_cfg___ref_interval___lsb 10 -#define reg_ddr2_rw_cfg___ref_interval___width 11 -#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 -#define reg_ddr2_rw_cfg___odt_ctrl___width 2 -#define reg_ddr2_rw_cfg___odt_mem___lsb 23 -#define reg_ddr2_rw_cfg___odt_mem___width 1 -#define reg_ddr2_rw_cfg___odt_mem___bit 23 -#define reg_ddr2_rw_cfg___imp_strength___lsb 24 -#define reg_ddr2_rw_cfg___imp_strength___width 1 -#define reg_ddr2_rw_cfg___imp_strength___bit 24 -#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 -#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 -#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 -#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 -#define reg_ddr2_rw_cfg___imp_cal_override___width 1 -#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 -#define reg_ddr2_rw_cfg___dll_override___lsb 27 -#define reg_ddr2_rw_cfg___dll_override___width 1 -#define reg_ddr2_rw_cfg___dll_override___bit 27 -#define reg_ddr2_rw_cfg_offset 0 - -/* Register rw_timing, scope ddr2, type rw */ -#define reg_ddr2_rw_timing___wr___lsb 0 -#define reg_ddr2_rw_timing___wr___width 3 -#define reg_ddr2_rw_timing___rcd___lsb 3 -#define reg_ddr2_rw_timing___rcd___width 3 -#define reg_ddr2_rw_timing___rp___lsb 6 -#define reg_ddr2_rw_timing___rp___width 3 -#define reg_ddr2_rw_timing___ras___lsb 9 -#define reg_ddr2_rw_timing___ras___width 4 -#define reg_ddr2_rw_timing___rfc___lsb 13 -#define reg_ddr2_rw_timing___rfc___width 7 -#define reg_ddr2_rw_timing___rc___lsb 20 -#define reg_ddr2_rw_timing___rc___width 5 -#define reg_ddr2_rw_timing___rtp___lsb 25 -#define reg_ddr2_rw_timing___rtp___width 2 -#define reg_ddr2_rw_timing___rtw___lsb 27 -#define reg_ddr2_rw_timing___rtw___width 3 -#define reg_ddr2_rw_timing___wtr___lsb 30 -#define reg_ddr2_rw_timing___wtr___width 2 -#define reg_ddr2_rw_timing_offset 4 - -/* Register rw_latency, scope ddr2, type rw */ -#define reg_ddr2_rw_latency___cas___lsb 0 -#define reg_ddr2_rw_latency___cas___width 3 -#define reg_ddr2_rw_latency___additive___lsb 3 -#define reg_ddr2_rw_latency___additive___width 3 -#define reg_ddr2_rw_latency_offset 8 - -/* Register rw_phy_cfg, scope ddr2, type rw */ -#define reg_ddr2_rw_phy_cfg___en___lsb 0 -#define reg_ddr2_rw_phy_cfg___en___width 1 -#define reg_ddr2_rw_phy_cfg___en___bit 0 -#define reg_ddr2_rw_phy_cfg_offset 12 - -/* Register rw_phy_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 -#define reg_ddr2_rw_phy_ctrl___rst___width 1 -#define reg_ddr2_rw_phy_ctrl___rst___bit 0 -#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 -#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 -#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 -#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 -#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 -#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 -#define reg_ddr2_rw_phy_ctrl_offset 16 - -/* Register rw_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 -#define reg_ddr2_rw_ctrl___mrs_data___width 16 -#define reg_ddr2_rw_ctrl___cmd___lsb 16 -#define reg_ddr2_rw_ctrl___cmd___width 8 -#define reg_ddr2_rw_ctrl_offset 20 - -/* Register rw_pwr_down, scope ddr2, type rw */ -#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 -#define reg_ddr2_rw_pwr_down___self_ref___width 2 -#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 -#define reg_ddr2_rw_pwr_down___phy_en___width 1 -#define reg_ddr2_rw_pwr_down___phy_en___bit 2 -#define reg_ddr2_rw_pwr_down_offset 24 - -/* Register r_stat, scope ddr2, type r */ -#define reg_ddr2_r_stat___dll_lock___lsb 0 -#define reg_ddr2_r_stat___dll_lock___width 1 -#define reg_ddr2_r_stat___dll_lock___bit 0 -#define reg_ddr2_r_stat___dll_delay_code___lsb 1 -#define reg_ddr2_r_stat___dll_delay_code___width 7 -#define reg_ddr2_r_stat___imp_cal_done___lsb 8 -#define reg_ddr2_r_stat___imp_cal_done___width 1 -#define reg_ddr2_r_stat___imp_cal_done___bit 8 -#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 -#define reg_ddr2_r_stat___imp_cal_fault___width 1 -#define reg_ddr2_r_stat___imp_cal_fault___bit 9 -#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 -#define reg_ddr2_r_stat___cal_imp_pu___width 4 -#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 -#define reg_ddr2_r_stat___cal_imp_pd___width 4 -#define reg_ddr2_r_stat_offset 28 - -/* Register rw_imp_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 -#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 -#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 -#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 -#define reg_ddr2_rw_imp_ctrl_offset 32 - -#define STRIDE_ddr2_rw_dll_ctrl 4 -/* Register rw_dll_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 -#define reg_ddr2_rw_dll_ctrl___mode___width 1 -#define reg_ddr2_rw_dll_ctrl___mode___bit 0 -#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 -#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 -#define reg_ddr2_rw_dll_ctrl_offset 36 - -#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 -/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 - - -/* Constants */ -#define regk_ddr2_al0 0x00000000 -#define regk_ddr2_al1 0x00000008 -#define regk_ddr2_al2 0x00000010 -#define regk_ddr2_al3 0x00000018 -#define regk_ddr2_al4 0x00000020 -#define regk_ddr2_auto 0x00000003 -#define regk_ddr2_bank4 0x00000000 -#define regk_ddr2_bank8 0x00000001 -#define regk_ddr2_bl4 0x00000002 -#define regk_ddr2_bl8 0x00000003 -#define regk_ddr2_bt_il 0x00000008 -#define regk_ddr2_bt_seq 0x00000000 -#define regk_ddr2_bw16 0x00000001 -#define regk_ddr2_bw32 0x00000000 -#define regk_ddr2_cas2 0x00000020 -#define regk_ddr2_cas3 0x00000030 -#define regk_ddr2_cas4 0x00000040 -#define regk_ddr2_cas5 0x00000050 -#define regk_ddr2_deselect 0x000000c0 -#define regk_ddr2_dic_weak 0x00000002 -#define regk_ddr2_direct 0x00000001 -#define regk_ddr2_dis 0x00000000 -#define regk_ddr2_dll_dis 0x00000001 -#define regk_ddr2_dll_en 0x00000000 -#define regk_ddr2_dll_rst 0x00000100 -#define regk_ddr2_emrs 0x00000081 -#define regk_ddr2_emrs2 0x00000082 -#define regk_ddr2_emrs3 0x00000083 -#define regk_ddr2_full 0x00000001 -#define regk_ddr2_hi_ref_rate 0x00000080 -#define regk_ddr2_mrs 0x00000080 -#define regk_ddr2_no 0x00000000 -#define regk_ddr2_nop 0x000000b8 -#define regk_ddr2_ocd_adj 0x00000200 -#define regk_ddr2_ocd_default 0x00000380 -#define regk_ddr2_ocd_drive0 0x00000100 -#define regk_ddr2_ocd_drive1 0x00000080 -#define regk_ddr2_ocd_exit 0x00000000 -#define regk_ddr2_odt_dis 0x00000000 -#define regk_ddr2_offs 0x00000000 -#define regk_ddr2_pre 0x00000090 -#define regk_ddr2_pre_all 0x00000400 -#define regk_ddr2_pwr_down_fast 0x00000000 -#define regk_ddr2_pwr_down_slow 0x00001000 -#define regk_ddr2_ref 0x00000088 -#define regk_ddr2_rtt150 0x00000040 -#define regk_ddr2_rtt50 0x00000044 -#define regk_ddr2_rtt75 0x00000004 -#define regk_ddr2_rw_cfg_default 0x00186000 -#define regk_ddr2_rw_dll_ctrl_default 0x00000000 -#define regk_ddr2_rw_dll_ctrl_size 0x00000004 -#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 -#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 -#define regk_ddr2_rw_latency_default 0x00000000 -#define regk_ddr2_rw_phy_cfg_default 0x00000000 -#define regk_ddr2_rw_pwr_down_default 0x00000000 -#define regk_ddr2_rw_timing_default 0x00000000 -#define regk_ddr2_s1Gb 0x0000001a -#define regk_ddr2_s256Mb 0x0000000f -#define regk_ddr2_s2Gb 0x00000027 -#define regk_ddr2_s4Gb 0x00000042 -#define regk_ddr2_s512Mb 0x00000015 -#define regk_ddr2_temp0_85 0x00000618 -#define regk_ddr2_temp85_95 0x0000030c -#define regk_ddr2_term150 0x00000002 -#define regk_ddr2_term50 0x00000003 -#define regk_ddr2_term75 0x00000001 -#define regk_ddr2_test 0x00000080 -#define regk_ddr2_weak 0x00000000 -#define regk_ddr2_wr2 0x00000200 -#define regk_ddr2_wr3 0x00000400 -#define regk_ddr2_yes 0x00000001 -#endif /* __ddr2_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index df6714fda179..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,849 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: gio.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 32 -#define reg_gio_r_pa_din_offset 0 - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 32 -#define reg_gio_rw_pa_dout_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 32 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_pa_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte0_dout___data___lsb 0 -#define reg_gio_rw_pa_byte0_dout___data___width 8 -#define reg_gio_rw_pa_byte0_dout_offset 12 - -/* Register rw_pa_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte0_oe___oe___width 8 -#define reg_gio_rw_pa_byte0_oe_offset 16 - -/* Register rw_pa_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte1_dout___data___lsb 0 -#define reg_gio_rw_pa_byte1_dout___data___width 8 -#define reg_gio_rw_pa_byte1_dout_offset 20 - -/* Register rw_pa_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte1_oe___oe___width 8 -#define reg_gio_rw_pa_byte1_oe_offset 24 - -/* Register rw_pa_byte2_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte2_dout___data___lsb 0 -#define reg_gio_rw_pa_byte2_dout___data___width 8 -#define reg_gio_rw_pa_byte2_dout_offset 28 - -/* Register rw_pa_byte2_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte2_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte2_oe___oe___width 8 -#define reg_gio_rw_pa_byte2_oe_offset 32 - -/* Register rw_pa_byte3_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte3_dout___data___lsb 0 -#define reg_gio_rw_pa_byte3_dout___data___width 8 -#define reg_gio_rw_pa_byte3_dout_offset 36 - -/* Register rw_pa_byte3_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte3_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte3_oe___oe___width 8 -#define reg_gio_rw_pa_byte3_oe_offset 40 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 32 -#define reg_gio_r_pb_din_offset 44 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 32 -#define reg_gio_rw_pb_dout_offset 48 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 32 -#define reg_gio_rw_pb_oe_offset 52 - -/* Register rw_pb_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte0_dout___data___lsb 0 -#define reg_gio_rw_pb_byte0_dout___data___width 8 -#define reg_gio_rw_pb_byte0_dout_offset 56 - -/* Register rw_pb_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte0_oe___oe___width 8 -#define reg_gio_rw_pb_byte0_oe_offset 60 - -/* Register rw_pb_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte1_dout___data___lsb 0 -#define reg_gio_rw_pb_byte1_dout___data___width 8 -#define reg_gio_rw_pb_byte1_dout_offset 64 - -/* Register rw_pb_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte1_oe___oe___width 8 -#define reg_gio_rw_pb_byte1_oe_offset 68 - -/* Register rw_pb_byte2_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte2_dout___data___lsb 0 -#define reg_gio_rw_pb_byte2_dout___data___width 8 -#define reg_gio_rw_pb_byte2_dout_offset 72 - -/* Register rw_pb_byte2_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte2_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte2_oe___oe___width 8 -#define reg_gio_rw_pb_byte2_oe_offset 76 - -/* Register rw_pb_byte3_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte3_dout___data___lsb 0 -#define reg_gio_rw_pb_byte3_dout___data___width 8 -#define reg_gio_rw_pb_byte3_dout_offset 80 - -/* Register rw_pb_byte3_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte3_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte3_oe___oe___width 8 -#define reg_gio_rw_pb_byte3_oe_offset 84 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 16 -#define reg_gio_r_pc_din_offset 88 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 16 -#define reg_gio_rw_pc_dout_offset 92 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 16 -#define reg_gio_rw_pc_oe_offset 96 - -/* Register rw_pc_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pc_byte0_dout___data___lsb 0 -#define reg_gio_rw_pc_byte0_dout___data___width 8 -#define reg_gio_rw_pc_byte0_dout_offset 100 - -/* Register rw_pc_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pc_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pc_byte0_oe___oe___width 8 -#define reg_gio_rw_pc_byte0_oe_offset 104 - -/* Register rw_pc_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pc_byte1_dout___data___lsb 0 -#define reg_gio_rw_pc_byte1_dout___data___width 8 -#define reg_gio_rw_pc_byte1_dout_offset 108 - -/* Register rw_pc_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pc_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pc_byte1_oe___oe___width 8 -#define reg_gio_rw_pc_byte1_oe_offset 112 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 32 -#define reg_gio_r_pd_din_offset 116 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___intr0___lsb 0 -#define reg_gio_rw_intr_cfg___intr0___width 3 -#define reg_gio_rw_intr_cfg___intr1___lsb 3 -#define reg_gio_rw_intr_cfg___intr1___width 3 -#define reg_gio_rw_intr_cfg___intr2___lsb 6 -#define reg_gio_rw_intr_cfg___intr2___width 3 -#define reg_gio_rw_intr_cfg___intr3___lsb 9 -#define reg_gio_rw_intr_cfg___intr3___width 3 -#define reg_gio_rw_intr_cfg___intr4___lsb 12 -#define reg_gio_rw_intr_cfg___intr4___width 3 -#define reg_gio_rw_intr_cfg___intr5___lsb 15 -#define reg_gio_rw_intr_cfg___intr5___width 3 -#define reg_gio_rw_intr_cfg___intr6___lsb 18 -#define reg_gio_rw_intr_cfg___intr6___width 3 -#define reg_gio_rw_intr_cfg___intr7___lsb 21 -#define reg_gio_rw_intr_cfg___intr7___width 3 -#define reg_gio_rw_intr_cfg_offset 120 - -/* Register rw_intr_pins, scope gio, type rw */ -#define reg_gio_rw_intr_pins___intr0___lsb 0 -#define reg_gio_rw_intr_pins___intr0___width 4 -#define reg_gio_rw_intr_pins___intr1___lsb 4 -#define reg_gio_rw_intr_pins___intr1___width 4 -#define reg_gio_rw_intr_pins___intr2___lsb 8 -#define reg_gio_rw_intr_pins___intr2___width 4 -#define reg_gio_rw_intr_pins___intr3___lsb 12 -#define reg_gio_rw_intr_pins___intr3___width 4 -#define reg_gio_rw_intr_pins___intr4___lsb 16 -#define reg_gio_rw_intr_pins___intr4___width 4 -#define reg_gio_rw_intr_pins___intr5___lsb 20 -#define reg_gio_rw_intr_pins___intr5___width 4 -#define reg_gio_rw_intr_pins___intr6___lsb 24 -#define reg_gio_rw_intr_pins___intr6___width 4 -#define reg_gio_rw_intr_pins___intr7___lsb 28 -#define reg_gio_rw_intr_pins___intr7___width 4 -#define reg_gio_rw_intr_pins_offset 124 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___intr0___lsb 0 -#define reg_gio_rw_intr_mask___intr0___width 1 -#define reg_gio_rw_intr_mask___intr0___bit 0 -#define reg_gio_rw_intr_mask___intr1___lsb 1 -#define reg_gio_rw_intr_mask___intr1___width 1 -#define reg_gio_rw_intr_mask___intr1___bit 1 -#define reg_gio_rw_intr_mask___intr2___lsb 2 -#define reg_gio_rw_intr_mask___intr2___width 1 -#define reg_gio_rw_intr_mask___intr2___bit 2 -#define reg_gio_rw_intr_mask___intr3___lsb 3 -#define reg_gio_rw_intr_mask___intr3___width 1 -#define reg_gio_rw_intr_mask___intr3___bit 3 -#define reg_gio_rw_intr_mask___intr4___lsb 4 -#define reg_gio_rw_intr_mask___intr4___width 1 -#define reg_gio_rw_intr_mask___intr4___bit 4 -#define reg_gio_rw_intr_mask___intr5___lsb 5 -#define reg_gio_rw_intr_mask___intr5___width 1 -#define reg_gio_rw_intr_mask___intr5___bit 5 -#define reg_gio_rw_intr_mask___intr6___lsb 6 -#define reg_gio_rw_intr_mask___intr6___width 1 -#define reg_gio_rw_intr_mask___intr6___bit 6 -#define reg_gio_rw_intr_mask___intr7___lsb 7 -#define reg_gio_rw_intr_mask___intr7___width 1 -#define reg_gio_rw_intr_mask___intr7___bit 7 -#define reg_gio_rw_intr_mask___i2c0_done___lsb 8 -#define reg_gio_rw_intr_mask___i2c0_done___width 1 -#define reg_gio_rw_intr_mask___i2c0_done___bit 8 -#define reg_gio_rw_intr_mask___i2c1_done___lsb 9 -#define reg_gio_rw_intr_mask___i2c1_done___width 1 -#define reg_gio_rw_intr_mask___i2c1_done___bit 9 -#define reg_gio_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___intr0___lsb 0 -#define reg_gio_rw_ack_intr___intr0___width 1 -#define reg_gio_rw_ack_intr___intr0___bit 0 -#define reg_gio_rw_ack_intr___intr1___lsb 1 -#define reg_gio_rw_ack_intr___intr1___width 1 -#define reg_gio_rw_ack_intr___intr1___bit 1 -#define reg_gio_rw_ack_intr___intr2___lsb 2 -#define reg_gio_rw_ack_intr___intr2___width 1 -#define reg_gio_rw_ack_intr___intr2___bit 2 -#define reg_gio_rw_ack_intr___intr3___lsb 3 -#define reg_gio_rw_ack_intr___intr3___width 1 -#define reg_gio_rw_ack_intr___intr3___bit 3 -#define reg_gio_rw_ack_intr___intr4___lsb 4 -#define reg_gio_rw_ack_intr___intr4___width 1 -#define reg_gio_rw_ack_intr___intr4___bit 4 -#define reg_gio_rw_ack_intr___intr5___lsb 5 -#define reg_gio_rw_ack_intr___intr5___width 1 -#define reg_gio_rw_ack_intr___intr5___bit 5 -#define reg_gio_rw_ack_intr___intr6___lsb 6 -#define reg_gio_rw_ack_intr___intr6___width 1 -#define reg_gio_rw_ack_intr___intr6___bit 6 -#define reg_gio_rw_ack_intr___intr7___lsb 7 -#define reg_gio_rw_ack_intr___intr7___width 1 -#define reg_gio_rw_ack_intr___intr7___bit 7 -#define reg_gio_rw_ack_intr___i2c0_done___lsb 8 -#define reg_gio_rw_ack_intr___i2c0_done___width 1 -#define reg_gio_rw_ack_intr___i2c0_done___bit 8 -#define reg_gio_rw_ack_intr___i2c1_done___lsb 9 -#define reg_gio_rw_ack_intr___i2c1_done___width 1 -#define reg_gio_rw_ack_intr___i2c1_done___bit 9 -#define reg_gio_rw_ack_intr_offset 132 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___intr0___lsb 0 -#define reg_gio_r_intr___intr0___width 1 -#define reg_gio_r_intr___intr0___bit 0 -#define reg_gio_r_intr___intr1___lsb 1 -#define reg_gio_r_intr___intr1___width 1 -#define reg_gio_r_intr___intr1___bit 1 -#define reg_gio_r_intr___intr2___lsb 2 -#define reg_gio_r_intr___intr2___width 1 -#define reg_gio_r_intr___intr2___bit 2 -#define reg_gio_r_intr___intr3___lsb 3 -#define reg_gio_r_intr___intr3___width 1 -#define reg_gio_r_intr___intr3___bit 3 -#define reg_gio_r_intr___intr4___lsb 4 -#define reg_gio_r_intr___intr4___width 1 -#define reg_gio_r_intr___intr4___bit 4 -#define reg_gio_r_intr___intr5___lsb 5 -#define reg_gio_r_intr___intr5___width 1 -#define reg_gio_r_intr___intr5___bit 5 -#define reg_gio_r_intr___intr6___lsb 6 -#define reg_gio_r_intr___intr6___width 1 -#define reg_gio_r_intr___intr6___bit 6 -#define reg_gio_r_intr___intr7___lsb 7 -#define reg_gio_r_intr___intr7___width 1 -#define reg_gio_r_intr___intr7___bit 7 -#define reg_gio_r_intr___i2c0_done___lsb 8 -#define reg_gio_r_intr___i2c0_done___width 1 -#define reg_gio_r_intr___i2c0_done___bit 8 -#define reg_gio_r_intr___i2c1_done___lsb 9 -#define reg_gio_r_intr___i2c1_done___width 1 -#define reg_gio_r_intr___i2c1_done___bit 9 -#define reg_gio_r_intr_offset 136 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___intr0___lsb 0 -#define reg_gio_r_masked_intr___intr0___width 1 -#define reg_gio_r_masked_intr___intr0___bit 0 -#define reg_gio_r_masked_intr___intr1___lsb 1 -#define reg_gio_r_masked_intr___intr1___width 1 -#define reg_gio_r_masked_intr___intr1___bit 1 -#define reg_gio_r_masked_intr___intr2___lsb 2 -#define reg_gio_r_masked_intr___intr2___width 1 -#define reg_gio_r_masked_intr___intr2___bit 2 -#define reg_gio_r_masked_intr___intr3___lsb 3 -#define reg_gio_r_masked_intr___intr3___width 1 -#define reg_gio_r_masked_intr___intr3___bit 3 -#define reg_gio_r_masked_intr___intr4___lsb 4 -#define reg_gio_r_masked_intr___intr4___width 1 -#define reg_gio_r_masked_intr___intr4___bit 4 -#define reg_gio_r_masked_intr___intr5___lsb 5 -#define reg_gio_r_masked_intr___intr5___width 1 -#define reg_gio_r_masked_intr___intr5___bit 5 -#define reg_gio_r_masked_intr___intr6___lsb 6 -#define reg_gio_r_masked_intr___intr6___width 1 -#define reg_gio_r_masked_intr___intr6___bit 6 -#define reg_gio_r_masked_intr___intr7___lsb 7 -#define reg_gio_r_masked_intr___intr7___width 1 -#define reg_gio_r_masked_intr___intr7___bit 7 -#define reg_gio_r_masked_intr___i2c0_done___lsb 8 -#define reg_gio_r_masked_intr___i2c0_done___width 1 -#define reg_gio_r_masked_intr___i2c0_done___bit 8 -#define reg_gio_r_masked_intr___i2c1_done___lsb 9 -#define reg_gio_r_masked_intr___i2c1_done___width 1 -#define reg_gio_r_masked_intr___i2c1_done___bit 9 -#define reg_gio_r_masked_intr_offset 140 - -/* Register rw_i2c0_start, scope gio, type rw */ -#define reg_gio_rw_i2c0_start___run___lsb 0 -#define reg_gio_rw_i2c0_start___run___width 1 -#define reg_gio_rw_i2c0_start___run___bit 0 -#define reg_gio_rw_i2c0_start_offset 144 - -/* Register rw_i2c0_cfg, scope gio, type rw */ -#define reg_gio_rw_i2c0_cfg___en___lsb 0 -#define reg_gio_rw_i2c0_cfg___en___width 1 -#define reg_gio_rw_i2c0_cfg___en___bit 0 -#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 -#define reg_gio_rw_i2c0_cfg___bit_order___width 1 -#define reg_gio_rw_i2c0_cfg___bit_order___bit 1 -#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 -#define reg_gio_rw_i2c0_cfg___scl_io___width 1 -#define reg_gio_rw_i2c0_cfg___scl_io___bit 2 -#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 -#define reg_gio_rw_i2c0_cfg___scl_inv___width 1 -#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 -#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 -#define reg_gio_rw_i2c0_cfg___sda_io___width 1 -#define reg_gio_rw_i2c0_cfg___sda_io___bit 4 -#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 -#define reg_gio_rw_i2c0_cfg___sda_idle___width 1 -#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 -#define reg_gio_rw_i2c0_cfg_offset 148 - -/* Register rw_i2c0_ctrl, scope gio, type rw */ -#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 -#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 -#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 -#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 -#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 -#define reg_gio_rw_i2c0_ctrl___extra_start___width 3 -#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 -#define reg_gio_rw_i2c0_ctrl___early_end___width 1 -#define reg_gio_rw_i2c0_ctrl___early_end___bit 15 -#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 -#define reg_gio_rw_i2c0_ctrl___start_stop___width 1 -#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 -#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 -#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 -#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 -#define reg_gio_rw_i2c0_ctrl___start_bit___width 1 -#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 -#define reg_gio_rw_i2c0_ctrl___freq___lsb 25 -#define reg_gio_rw_i2c0_ctrl___freq___width 2 -#define reg_gio_rw_i2c0_ctrl_offset 152 - -/* Register rw_i2c0_data, scope gio, type rw */ -#define reg_gio_rw_i2c0_data___data0___lsb 0 -#define reg_gio_rw_i2c0_data___data0___width 8 -#define reg_gio_rw_i2c0_data___data1___lsb 8 -#define reg_gio_rw_i2c0_data___data1___width 8 -#define reg_gio_rw_i2c0_data___data2___lsb 16 -#define reg_gio_rw_i2c0_data___data2___width 8 -#define reg_gio_rw_i2c0_data___data3___lsb 24 -#define reg_gio_rw_i2c0_data___data3___width 8 -#define reg_gio_rw_i2c0_data_offset 156 - -/* Register rw_i2c0_data2, scope gio, type rw */ -#define reg_gio_rw_i2c0_data2___data4___lsb 0 -#define reg_gio_rw_i2c0_data2___data4___width 8 -#define reg_gio_rw_i2c0_data2___data5___lsb 8 -#define reg_gio_rw_i2c0_data2___data5___width 8 -#define reg_gio_rw_i2c0_data2___start_val___lsb 16 -#define reg_gio_rw_i2c0_data2___start_val___width 6 -#define reg_gio_rw_i2c0_data2___ack_val___lsb 22 -#define reg_gio_rw_i2c0_data2___ack_val___width 6 -#define reg_gio_rw_i2c0_data2_offset 160 - -/* Register rw_i2c1_start, scope gio, type rw */ -#define reg_gio_rw_i2c1_start___run___lsb 0 -#define reg_gio_rw_i2c1_start___run___width 1 -#define reg_gio_rw_i2c1_start___run___bit 0 -#define reg_gio_rw_i2c1_start_offset 164 - -/* Register rw_i2c1_cfg, scope gio, type rw */ -#define reg_gio_rw_i2c1_cfg___en___lsb 0 -#define reg_gio_rw_i2c1_cfg___en___width 1 -#define reg_gio_rw_i2c1_cfg___en___bit 0 -#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 -#define reg_gio_rw_i2c1_cfg___bit_order___width 1 -#define reg_gio_rw_i2c1_cfg___bit_order___bit 1 -#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 -#define reg_gio_rw_i2c1_cfg___scl_io___width 1 -#define reg_gio_rw_i2c1_cfg___scl_io___bit 2 -#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 -#define reg_gio_rw_i2c1_cfg___scl_inv___width 1 -#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 -#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 -#define reg_gio_rw_i2c1_cfg___sda0_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 -#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 -#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 -#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 -#define reg_gio_rw_i2c1_cfg___sda1_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 -#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 -#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 -#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 -#define reg_gio_rw_i2c1_cfg___sda2_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 -#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 -#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 -#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 -#define reg_gio_rw_i2c1_cfg___sda3_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 -#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 -#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 -#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 -#define reg_gio_rw_i2c1_cfg___sda_sel___width 2 -#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 -#define reg_gio_rw_i2c1_cfg___sen_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 -#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 -#define reg_gio_rw_i2c1_cfg___sen_inv___width 1 -#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 -#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 -#define reg_gio_rw_i2c1_cfg___sen_sel___width 2 -#define reg_gio_rw_i2c1_cfg_offset 168 - -/* Register rw_i2c1_ctrl, scope gio, type rw */ -#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 -#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 -#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 -#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 -#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 -#define reg_gio_rw_i2c1_ctrl___extra_start___width 3 -#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 -#define reg_gio_rw_i2c1_ctrl___early_end___width 1 -#define reg_gio_rw_i2c1_ctrl___early_end___bit 15 -#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 -#define reg_gio_rw_i2c1_ctrl___start_stop___width 1 -#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 -#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 -#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 -#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 -#define reg_gio_rw_i2c1_ctrl___start_bit___width 1 -#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 -#define reg_gio_rw_i2c1_ctrl___freq___lsb 25 -#define reg_gio_rw_i2c1_ctrl___freq___width 2 -#define reg_gio_rw_i2c1_ctrl_offset 172 - -/* Register rw_i2c1_data, scope gio, type rw */ -#define reg_gio_rw_i2c1_data___data0___lsb 0 -#define reg_gio_rw_i2c1_data___data0___width 8 -#define reg_gio_rw_i2c1_data___data1___lsb 8 -#define reg_gio_rw_i2c1_data___data1___width 8 -#define reg_gio_rw_i2c1_data___data2___lsb 16 -#define reg_gio_rw_i2c1_data___data2___width 8 -#define reg_gio_rw_i2c1_data___data3___lsb 24 -#define reg_gio_rw_i2c1_data___data3___width 8 -#define reg_gio_rw_i2c1_data_offset 176 - -/* Register rw_i2c1_data2, scope gio, type rw */ -#define reg_gio_rw_i2c1_data2___data4___lsb 0 -#define reg_gio_rw_i2c1_data2___data4___width 8 -#define reg_gio_rw_i2c1_data2___data5___lsb 8 -#define reg_gio_rw_i2c1_data2___data5___width 8 -#define reg_gio_rw_i2c1_data2___start_val___lsb 16 -#define reg_gio_rw_i2c1_data2___start_val___width 6 -#define reg_gio_rw_i2c1_data2___ack_val___lsb 22 -#define reg_gio_rw_i2c1_data2___ack_val___width 6 -#define reg_gio_rw_i2c1_data2_offset 180 - -/* Register r_ppwm_stat, scope gio, type r */ -#define reg_gio_r_ppwm_stat___freq___lsb 0 -#define reg_gio_r_ppwm_stat___freq___width 2 -#define reg_gio_r_ppwm_stat_offset 184 - -/* Register rw_ppwm_data, scope gio, type rw */ -#define reg_gio_rw_ppwm_data___data___lsb 0 -#define reg_gio_rw_ppwm_data___data___width 8 -#define reg_gio_rw_ppwm_data_offset 188 - -/* Register rw_pwm0_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm0_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm0_ctrl___mode___width 2 -#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm0_ctrl_offset 192 - -/* Register rw_pwm0_var, scope gio, type rw */ -#define reg_gio_rw_pwm0_var___lo___lsb 0 -#define reg_gio_rw_pwm0_var___lo___width 13 -#define reg_gio_rw_pwm0_var___hi___lsb 13 -#define reg_gio_rw_pwm0_var___hi___width 13 -#define reg_gio_rw_pwm0_var_offset 196 - -/* Register rw_pwm0_data, scope gio, type rw */ -#define reg_gio_rw_pwm0_data___data___lsb 0 -#define reg_gio_rw_pwm0_data___data___width 8 -#define reg_gio_rw_pwm0_data_offset 200 - -/* Register rw_pwm1_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm1_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm1_ctrl___mode___width 2 -#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm1_ctrl_offset 204 - -/* Register rw_pwm1_var, scope gio, type rw */ -#define reg_gio_rw_pwm1_var___lo___lsb 0 -#define reg_gio_rw_pwm1_var___lo___width 13 -#define reg_gio_rw_pwm1_var___hi___lsb 13 -#define reg_gio_rw_pwm1_var___hi___width 13 -#define reg_gio_rw_pwm1_var_offset 208 - -/* Register rw_pwm1_data, scope gio, type rw */ -#define reg_gio_rw_pwm1_data___data___lsb 0 -#define reg_gio_rw_pwm1_data___data___width 8 -#define reg_gio_rw_pwm1_data_offset 212 - -/* Register rw_pwm2_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm2_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm2_ctrl___mode___width 2 -#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm2_ctrl_offset 216 - -/* Register rw_pwm2_var, scope gio, type rw */ -#define reg_gio_rw_pwm2_var___lo___lsb 0 -#define reg_gio_rw_pwm2_var___lo___width 13 -#define reg_gio_rw_pwm2_var___hi___lsb 13 -#define reg_gio_rw_pwm2_var___hi___width 13 -#define reg_gio_rw_pwm2_var_offset 220 - -/* Register rw_pwm2_data, scope gio, type rw */ -#define reg_gio_rw_pwm2_data___data___lsb 0 -#define reg_gio_rw_pwm2_data___data___width 8 -#define reg_gio_rw_pwm2_data_offset 224 - -/* Register rw_pwm_in_cfg, scope gio, type rw */ -#define reg_gio_rw_pwm_in_cfg___pin___lsb 0 -#define reg_gio_rw_pwm_in_cfg___pin___width 3 -#define reg_gio_rw_pwm_in_cfg_offset 228 - -/* Register r_pwm_in_lo, scope gio, type r */ -#define reg_gio_r_pwm_in_lo___data___lsb 0 -#define reg_gio_r_pwm_in_lo___data___width 32 -#define reg_gio_r_pwm_in_lo_offset 232 - -/* Register r_pwm_in_hi, scope gio, type r */ -#define reg_gio_r_pwm_in_hi___data___lsb 0 -#define reg_gio_r_pwm_in_hi___data___width 32 -#define reg_gio_r_pwm_in_hi_offset 236 - -/* Register r_pwm_in_cnt, scope gio, type r */ -#define reg_gio_r_pwm_in_cnt___data___lsb 0 -#define reg_gio_r_pwm_in_cnt___data___width 32 -#define reg_gio_r_pwm_in_cnt_offset 240 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_f100k 0x00000000 -#define regk_gio_f1562 0x00000000 -#define regk_gio_f195 0x00000003 -#define regk_gio_f1m 0x00000002 -#define regk_gio_f390 0x00000002 -#define regk_gio_f400k 0x00000001 -#define regk_gio_f5m 0x00000003 -#define regk_gio_f781 0x00000001 -#define regk_gio_hi 0x00000001 -#define regk_gio_in 0x00000000 -#define regk_gio_intr_pa0 0x00000000 -#define regk_gio_intr_pa1 0x00000000 -#define regk_gio_intr_pa10 0x00000001 -#define regk_gio_intr_pa11 0x00000001 -#define regk_gio_intr_pa12 0x00000001 -#define regk_gio_intr_pa13 0x00000001 -#define regk_gio_intr_pa14 0x00000001 -#define regk_gio_intr_pa15 0x00000001 -#define regk_gio_intr_pa16 0x00000002 -#define regk_gio_intr_pa17 0x00000002 -#define regk_gio_intr_pa18 0x00000002 -#define regk_gio_intr_pa19 0x00000002 -#define regk_gio_intr_pa2 0x00000000 -#define regk_gio_intr_pa20 0x00000002 -#define regk_gio_intr_pa21 0x00000002 -#define regk_gio_intr_pa22 0x00000002 -#define regk_gio_intr_pa23 0x00000002 -#define regk_gio_intr_pa24 0x00000003 -#define regk_gio_intr_pa25 0x00000003 -#define regk_gio_intr_pa26 0x00000003 -#define regk_gio_intr_pa27 0x00000003 -#define regk_gio_intr_pa28 0x00000003 -#define regk_gio_intr_pa29 0x00000003 -#define regk_gio_intr_pa3 0x00000000 -#define regk_gio_intr_pa30 0x00000003 -#define regk_gio_intr_pa31 0x00000003 -#define regk_gio_intr_pa4 0x00000000 -#define regk_gio_intr_pa5 0x00000000 -#define regk_gio_intr_pa6 0x00000000 -#define regk_gio_intr_pa7 0x00000000 -#define regk_gio_intr_pa8 0x00000001 -#define regk_gio_intr_pa9 0x00000001 -#define regk_gio_intr_pb0 0x00000004 -#define regk_gio_intr_pb1 0x00000004 -#define regk_gio_intr_pb10 0x00000005 -#define regk_gio_intr_pb11 0x00000005 -#define regk_gio_intr_pb12 0x00000005 -#define regk_gio_intr_pb13 0x00000005 -#define regk_gio_intr_pb14 0x00000005 -#define regk_gio_intr_pb15 0x00000005 -#define regk_gio_intr_pb16 0x00000006 -#define regk_gio_intr_pb17 0x00000006 -#define regk_gio_intr_pb18 0x00000006 -#define regk_gio_intr_pb19 0x00000006 -#define regk_gio_intr_pb2 0x00000004 -#define regk_gio_intr_pb20 0x00000006 -#define regk_gio_intr_pb21 0x00000006 -#define regk_gio_intr_pb22 0x00000006 -#define regk_gio_intr_pb23 0x00000006 -#define regk_gio_intr_pb24 0x00000007 -#define regk_gio_intr_pb25 0x00000007 -#define regk_gio_intr_pb26 0x00000007 -#define regk_gio_intr_pb27 0x00000007 -#define regk_gio_intr_pb28 0x00000007 -#define regk_gio_intr_pb29 0x00000007 -#define regk_gio_intr_pb3 0x00000004 -#define regk_gio_intr_pb30 0x00000007 -#define regk_gio_intr_pb31 0x00000007 -#define regk_gio_intr_pb4 0x00000004 -#define regk_gio_intr_pb5 0x00000004 -#define regk_gio_intr_pb6 0x00000004 -#define regk_gio_intr_pb7 0x00000004 -#define regk_gio_intr_pb8 0x00000005 -#define regk_gio_intr_pb9 0x00000005 -#define regk_gio_intr_pc0 0x00000008 -#define regk_gio_intr_pc1 0x00000008 -#define regk_gio_intr_pc10 0x00000009 -#define regk_gio_intr_pc11 0x00000009 -#define regk_gio_intr_pc12 0x00000009 -#define regk_gio_intr_pc13 0x00000009 -#define regk_gio_intr_pc14 0x00000009 -#define regk_gio_intr_pc15 0x00000009 -#define regk_gio_intr_pc2 0x00000008 -#define regk_gio_intr_pc3 0x00000008 -#define regk_gio_intr_pc4 0x00000008 -#define regk_gio_intr_pc5 0x00000008 -#define regk_gio_intr_pc6 0x00000008 -#define regk_gio_intr_pc7 0x00000008 -#define regk_gio_intr_pc8 0x00000009 -#define regk_gio_intr_pc9 0x00000009 -#define regk_gio_intr_pd0 0x0000000c -#define regk_gio_intr_pd1 0x0000000c -#define regk_gio_intr_pd10 0x0000000d -#define regk_gio_intr_pd11 0x0000000d -#define regk_gio_intr_pd12 0x0000000d -#define regk_gio_intr_pd13 0x0000000d -#define regk_gio_intr_pd14 0x0000000d -#define regk_gio_intr_pd15 0x0000000d -#define regk_gio_intr_pd16 0x0000000e -#define regk_gio_intr_pd17 0x0000000e -#define regk_gio_intr_pd18 0x0000000e -#define regk_gio_intr_pd19 0x0000000e -#define regk_gio_intr_pd2 0x0000000c -#define regk_gio_intr_pd20 0x0000000e -#define regk_gio_intr_pd21 0x0000000e -#define regk_gio_intr_pd22 0x0000000e -#define regk_gio_intr_pd23 0x0000000e -#define regk_gio_intr_pd24 0x0000000f -#define regk_gio_intr_pd25 0x0000000f -#define regk_gio_intr_pd26 0x0000000f -#define regk_gio_intr_pd27 0x0000000f -#define regk_gio_intr_pd28 0x0000000f -#define regk_gio_intr_pd29 0x0000000f -#define regk_gio_intr_pd3 0x0000000c -#define regk_gio_intr_pd30 0x0000000f -#define regk_gio_intr_pd31 0x0000000f -#define regk_gio_intr_pd4 0x0000000c -#define regk_gio_intr_pd5 0x0000000c -#define regk_gio_intr_pd6 0x0000000c -#define regk_gio_intr_pd7 0x0000000c -#define regk_gio_intr_pd8 0x0000000d -#define regk_gio_intr_pd9 0x0000000d -#define regk_gio_lo 0x00000002 -#define regk_gio_lsb 0x00000000 -#define regk_gio_msb 0x00000001 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_no_switch 0x0000003f -#define regk_gio_none 0x00000007 -#define regk_gio_off 0x00000000 -#define regk_gio_opendrain 0x00000000 -#define regk_gio_out 0x00000001 -#define regk_gio_posedge 0x00000005 -#define regk_gio_pwm_hfp 0x00000002 -#define regk_gio_pwm_pa0 0x00000001 -#define regk_gio_pwm_pa19 0x00000004 -#define regk_gio_pwm_pa6 0x00000002 -#define regk_gio_pwm_pa7 0x00000003 -#define regk_gio_pwm_pb26 0x00000005 -#define regk_gio_pwm_pd23 0x00000006 -#define regk_gio_pwm_pd31 0x00000007 -#define regk_gio_pwm_std 0x00000001 -#define regk_gio_pwm_var 0x00000003 -#define regk_gio_rw_i2c0_cfg_default 0x00000020 -#define regk_gio_rw_i2c0_ctrl_default 0x00010000 -#define regk_gio_rw_i2c0_start_default 0x00000000 -#define regk_gio_rw_i2c1_cfg_default 0x00000aa0 -#define regk_gio_rw_i2c1_ctrl_default 0x00010000 -#define regk_gio_rw_i2c1_start_default 0x00000000 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_ppwm_data_default 0x00000000 -#define regk_gio_rw_pwm0_ctrl_default 0x00000000 -#define regk_gio_rw_pwm1_ctrl_default 0x00000000 -#define regk_gio_rw_pwm2_ctrl_default 0x00000000 -#define regk_gio_rw_pwm_in_cfg_default 0x00000000 -#define regk_gio_sda0 0x00000000 -#define regk_gio_sda1 0x00000001 -#define regk_gio_sda2 0x00000002 -#define regk_gio_sda3 0x00000003 -#define regk_gio_sen 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index c3dc9c666c46..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,572 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: pinmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___eth___lsb 0 -#define reg_pinmux_rw_hwprot___eth___width 1 -#define reg_pinmux_rw_hwprot___eth___bit 0 -#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 -#define reg_pinmux_rw_hwprot___eth_mdio___width 1 -#define reg_pinmux_rw_hwprot___eth_mdio___bit 1 -#define reg_pinmux_rw_hwprot___geth___lsb 2 -#define reg_pinmux_rw_hwprot___geth___width 1 -#define reg_pinmux_rw_hwprot___geth___bit 2 -#define reg_pinmux_rw_hwprot___tg___lsb 3 -#define reg_pinmux_rw_hwprot___tg___width 1 -#define reg_pinmux_rw_hwprot___tg___bit 3 -#define reg_pinmux_rw_hwprot___tg_clk___lsb 4 -#define reg_pinmux_rw_hwprot___tg_clk___width 1 -#define reg_pinmux_rw_hwprot___tg_clk___bit 4 -#define reg_pinmux_rw_hwprot___vout___lsb 5 -#define reg_pinmux_rw_hwprot___vout___width 1 -#define reg_pinmux_rw_hwprot___vout___bit 5 -#define reg_pinmux_rw_hwprot___vout_sync___lsb 6 -#define reg_pinmux_rw_hwprot___vout_sync___width 1 -#define reg_pinmux_rw_hwprot___vout_sync___bit 6 -#define reg_pinmux_rw_hwprot___ser1___lsb 7 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 7 -#define reg_pinmux_rw_hwprot___ser2___lsb 8 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 8 -#define reg_pinmux_rw_hwprot___ser3___lsb 9 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 9 -#define reg_pinmux_rw_hwprot___ser4___lsb 10 -#define reg_pinmux_rw_hwprot___ser4___width 1 -#define reg_pinmux_rw_hwprot___ser4___bit 10 -#define reg_pinmux_rw_hwprot___sser___lsb 11 -#define reg_pinmux_rw_hwprot___sser___width 1 -#define reg_pinmux_rw_hwprot___sser___bit 11 -#define reg_pinmux_rw_hwprot___pwm0___lsb 12 -#define reg_pinmux_rw_hwprot___pwm0___width 1 -#define reg_pinmux_rw_hwprot___pwm0___bit 12 -#define reg_pinmux_rw_hwprot___pwm1___lsb 13 -#define reg_pinmux_rw_hwprot___pwm1___width 1 -#define reg_pinmux_rw_hwprot___pwm1___bit 13 -#define reg_pinmux_rw_hwprot___pwm2___lsb 14 -#define reg_pinmux_rw_hwprot___pwm2___width 1 -#define reg_pinmux_rw_hwprot___pwm2___bit 14 -#define reg_pinmux_rw_hwprot___timer0___lsb 15 -#define reg_pinmux_rw_hwprot___timer0___width 1 -#define reg_pinmux_rw_hwprot___timer0___bit 15 -#define reg_pinmux_rw_hwprot___timer1___lsb 16 -#define reg_pinmux_rw_hwprot___timer1___width 1 -#define reg_pinmux_rw_hwprot___timer1___bit 16 -#define reg_pinmux_rw_hwprot___pio___lsb 17 -#define reg_pinmux_rw_hwprot___pio___width 1 -#define reg_pinmux_rw_hwprot___pio___bit 17 -#define reg_pinmux_rw_hwprot___i2c0___lsb 18 -#define reg_pinmux_rw_hwprot___i2c0___width 1 -#define reg_pinmux_rw_hwprot___i2c0___bit 18 -#define reg_pinmux_rw_hwprot___i2c1___lsb 19 -#define reg_pinmux_rw_hwprot___i2c1___width 1 -#define reg_pinmux_rw_hwprot___i2c1___bit 19 -#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 -#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 -#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 -#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 -#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 -#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 -#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 -#define reg_pinmux_rw_hwprot___i2c1_sen___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 -#define reg_pinmux_rw_hwprot_offset 0 - -/* Register rw_gio_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pa___pa0___lsb 0 -#define reg_pinmux_rw_gio_pa___pa0___width 1 -#define reg_pinmux_rw_gio_pa___pa0___bit 0 -#define reg_pinmux_rw_gio_pa___pa1___lsb 1 -#define reg_pinmux_rw_gio_pa___pa1___width 1 -#define reg_pinmux_rw_gio_pa___pa1___bit 1 -#define reg_pinmux_rw_gio_pa___pa2___lsb 2 -#define reg_pinmux_rw_gio_pa___pa2___width 1 -#define reg_pinmux_rw_gio_pa___pa2___bit 2 -#define reg_pinmux_rw_gio_pa___pa3___lsb 3 -#define reg_pinmux_rw_gio_pa___pa3___width 1 -#define reg_pinmux_rw_gio_pa___pa3___bit 3 -#define reg_pinmux_rw_gio_pa___pa4___lsb 4 -#define reg_pinmux_rw_gio_pa___pa4___width 1 -#define reg_pinmux_rw_gio_pa___pa4___bit 4 -#define reg_pinmux_rw_gio_pa___pa5___lsb 5 -#define reg_pinmux_rw_gio_pa___pa5___width 1 -#define reg_pinmux_rw_gio_pa___pa5___bit 5 -#define reg_pinmux_rw_gio_pa___pa6___lsb 6 -#define reg_pinmux_rw_gio_pa___pa6___width 1 -#define reg_pinmux_rw_gio_pa___pa6___bit 6 -#define reg_pinmux_rw_gio_pa___pa7___lsb 7 -#define reg_pinmux_rw_gio_pa___pa7___width 1 -#define reg_pinmux_rw_gio_pa___pa7___bit 7 -#define reg_pinmux_rw_gio_pa___pa8___lsb 8 -#define reg_pinmux_rw_gio_pa___pa8___width 1 -#define reg_pinmux_rw_gio_pa___pa8___bit 8 -#define reg_pinmux_rw_gio_pa___pa9___lsb 9 -#define reg_pinmux_rw_gio_pa___pa9___width 1 -#define reg_pinmux_rw_gio_pa___pa9___bit 9 -#define reg_pinmux_rw_gio_pa___pa10___lsb 10 -#define reg_pinmux_rw_gio_pa___pa10___width 1 -#define reg_pinmux_rw_gio_pa___pa10___bit 10 -#define reg_pinmux_rw_gio_pa___pa11___lsb 11 -#define reg_pinmux_rw_gio_pa___pa11___width 1 -#define reg_pinmux_rw_gio_pa___pa11___bit 11 -#define reg_pinmux_rw_gio_pa___pa12___lsb 12 -#define reg_pinmux_rw_gio_pa___pa12___width 1 -#define reg_pinmux_rw_gio_pa___pa12___bit 12 -#define reg_pinmux_rw_gio_pa___pa13___lsb 13 -#define reg_pinmux_rw_gio_pa___pa13___width 1 -#define reg_pinmux_rw_gio_pa___pa13___bit 13 -#define reg_pinmux_rw_gio_pa___pa14___lsb 14 -#define reg_pinmux_rw_gio_pa___pa14___width 1 -#define reg_pinmux_rw_gio_pa___pa14___bit 14 -#define reg_pinmux_rw_gio_pa___pa15___lsb 15 -#define reg_pinmux_rw_gio_pa___pa15___width 1 -#define reg_pinmux_rw_gio_pa___pa15___bit 15 -#define reg_pinmux_rw_gio_pa___pa16___lsb 16 -#define reg_pinmux_rw_gio_pa___pa16___width 1 -#define reg_pinmux_rw_gio_pa___pa16___bit 16 -#define reg_pinmux_rw_gio_pa___pa17___lsb 17 -#define reg_pinmux_rw_gio_pa___pa17___width 1 -#define reg_pinmux_rw_gio_pa___pa17___bit 17 -#define reg_pinmux_rw_gio_pa___pa18___lsb 18 -#define reg_pinmux_rw_gio_pa___pa18___width 1 -#define reg_pinmux_rw_gio_pa___pa18___bit 18 -#define reg_pinmux_rw_gio_pa___pa19___lsb 19 -#define reg_pinmux_rw_gio_pa___pa19___width 1 -#define reg_pinmux_rw_gio_pa___pa19___bit 19 -#define reg_pinmux_rw_gio_pa___pa20___lsb 20 -#define reg_pinmux_rw_gio_pa___pa20___width 1 -#define reg_pinmux_rw_gio_pa___pa20___bit 20 -#define reg_pinmux_rw_gio_pa___pa21___lsb 21 -#define reg_pinmux_rw_gio_pa___pa21___width 1 -#define reg_pinmux_rw_gio_pa___pa21___bit 21 -#define reg_pinmux_rw_gio_pa___pa22___lsb 22 -#define reg_pinmux_rw_gio_pa___pa22___width 1 -#define reg_pinmux_rw_gio_pa___pa22___bit 22 -#define reg_pinmux_rw_gio_pa___pa23___lsb 23 -#define reg_pinmux_rw_gio_pa___pa23___width 1 -#define reg_pinmux_rw_gio_pa___pa23___bit 23 -#define reg_pinmux_rw_gio_pa___pa24___lsb 24 -#define reg_pinmux_rw_gio_pa___pa24___width 1 -#define reg_pinmux_rw_gio_pa___pa24___bit 24 -#define reg_pinmux_rw_gio_pa___pa25___lsb 25 -#define reg_pinmux_rw_gio_pa___pa25___width 1 -#define reg_pinmux_rw_gio_pa___pa25___bit 25 -#define reg_pinmux_rw_gio_pa___pa26___lsb 26 -#define reg_pinmux_rw_gio_pa___pa26___width 1 -#define reg_pinmux_rw_gio_pa___pa26___bit 26 -#define reg_pinmux_rw_gio_pa___pa27___lsb 27 -#define reg_pinmux_rw_gio_pa___pa27___width 1 -#define reg_pinmux_rw_gio_pa___pa27___bit 27 -#define reg_pinmux_rw_gio_pa___pa28___lsb 28 -#define reg_pinmux_rw_gio_pa___pa28___width 1 -#define reg_pinmux_rw_gio_pa___pa28___bit 28 -#define reg_pinmux_rw_gio_pa___pa29___lsb 29 -#define reg_pinmux_rw_gio_pa___pa29___width 1 -#define reg_pinmux_rw_gio_pa___pa29___bit 29 -#define reg_pinmux_rw_gio_pa___pa30___lsb 30 -#define reg_pinmux_rw_gio_pa___pa30___width 1 -#define reg_pinmux_rw_gio_pa___pa30___bit 30 -#define reg_pinmux_rw_gio_pa___pa31___lsb 31 -#define reg_pinmux_rw_gio_pa___pa31___width 1 -#define reg_pinmux_rw_gio_pa___pa31___bit 31 -#define reg_pinmux_rw_gio_pa_offset 4 - -/* Register rw_gio_pb, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pb___pb0___lsb 0 -#define reg_pinmux_rw_gio_pb___pb0___width 1 -#define reg_pinmux_rw_gio_pb___pb0___bit 0 -#define reg_pinmux_rw_gio_pb___pb1___lsb 1 -#define reg_pinmux_rw_gio_pb___pb1___width 1 -#define reg_pinmux_rw_gio_pb___pb1___bit 1 -#define reg_pinmux_rw_gio_pb___pb2___lsb 2 -#define reg_pinmux_rw_gio_pb___pb2___width 1 -#define reg_pinmux_rw_gio_pb___pb2___bit 2 -#define reg_pinmux_rw_gio_pb___pb3___lsb 3 -#define reg_pinmux_rw_gio_pb___pb3___width 1 -#define reg_pinmux_rw_gio_pb___pb3___bit 3 -#define reg_pinmux_rw_gio_pb___pb4___lsb 4 -#define reg_pinmux_rw_gio_pb___pb4___width 1 -#define reg_pinmux_rw_gio_pb___pb4___bit 4 -#define reg_pinmux_rw_gio_pb___pb5___lsb 5 -#define reg_pinmux_rw_gio_pb___pb5___width 1 -#define reg_pinmux_rw_gio_pb___pb5___bit 5 -#define reg_pinmux_rw_gio_pb___pb6___lsb 6 -#define reg_pinmux_rw_gio_pb___pb6___width 1 -#define reg_pinmux_rw_gio_pb___pb6___bit 6 -#define reg_pinmux_rw_gio_pb___pb7___lsb 7 -#define reg_pinmux_rw_gio_pb___pb7___width 1 -#define reg_pinmux_rw_gio_pb___pb7___bit 7 -#define reg_pinmux_rw_gio_pb___pb8___lsb 8 -#define reg_pinmux_rw_gio_pb___pb8___width 1 -#define reg_pinmux_rw_gio_pb___pb8___bit 8 -#define reg_pinmux_rw_gio_pb___pb9___lsb 9 -#define reg_pinmux_rw_gio_pb___pb9___width 1 -#define reg_pinmux_rw_gio_pb___pb9___bit 9 -#define reg_pinmux_rw_gio_pb___pb10___lsb 10 -#define reg_pinmux_rw_gio_pb___pb10___width 1 -#define reg_pinmux_rw_gio_pb___pb10___bit 10 -#define reg_pinmux_rw_gio_pb___pb11___lsb 11 -#define reg_pinmux_rw_gio_pb___pb11___width 1 -#define reg_pinmux_rw_gio_pb___pb11___bit 11 -#define reg_pinmux_rw_gio_pb___pb12___lsb 12 -#define reg_pinmux_rw_gio_pb___pb12___width 1 -#define reg_pinmux_rw_gio_pb___pb12___bit 12 -#define reg_pinmux_rw_gio_pb___pb13___lsb 13 -#define reg_pinmux_rw_gio_pb___pb13___width 1 -#define reg_pinmux_rw_gio_pb___pb13___bit 13 -#define reg_pinmux_rw_gio_pb___pb14___lsb 14 -#define reg_pinmux_rw_gio_pb___pb14___width 1 -#define reg_pinmux_rw_gio_pb___pb14___bit 14 -#define reg_pinmux_rw_gio_pb___pb15___lsb 15 -#define reg_pinmux_rw_gio_pb___pb15___width 1 -#define reg_pinmux_rw_gio_pb___pb15___bit 15 -#define reg_pinmux_rw_gio_pb___pb16___lsb 16 -#define reg_pinmux_rw_gio_pb___pb16___width 1 -#define reg_pinmux_rw_gio_pb___pb16___bit 16 -#define reg_pinmux_rw_gio_pb___pb17___lsb 17 -#define reg_pinmux_rw_gio_pb___pb17___width 1 -#define reg_pinmux_rw_gio_pb___pb17___bit 17 -#define reg_pinmux_rw_gio_pb___pb18___lsb 18 -#define reg_pinmux_rw_gio_pb___pb18___width 1 -#define reg_pinmux_rw_gio_pb___pb18___bit 18 -#define reg_pinmux_rw_gio_pb___pb19___lsb 19 -#define reg_pinmux_rw_gio_pb___pb19___width 1 -#define reg_pinmux_rw_gio_pb___pb19___bit 19 -#define reg_pinmux_rw_gio_pb___pb20___lsb 20 -#define reg_pinmux_rw_gio_pb___pb20___width 1 -#define reg_pinmux_rw_gio_pb___pb20___bit 20 -#define reg_pinmux_rw_gio_pb___pb21___lsb 21 -#define reg_pinmux_rw_gio_pb___pb21___width 1 -#define reg_pinmux_rw_gio_pb___pb21___bit 21 -#define reg_pinmux_rw_gio_pb___pb22___lsb 22 -#define reg_pinmux_rw_gio_pb___pb22___width 1 -#define reg_pinmux_rw_gio_pb___pb22___bit 22 -#define reg_pinmux_rw_gio_pb___pb23___lsb 23 -#define reg_pinmux_rw_gio_pb___pb23___width 1 -#define reg_pinmux_rw_gio_pb___pb23___bit 23 -#define reg_pinmux_rw_gio_pb___pb24___lsb 24 -#define reg_pinmux_rw_gio_pb___pb24___width 1 -#define reg_pinmux_rw_gio_pb___pb24___bit 24 -#define reg_pinmux_rw_gio_pb___pb25___lsb 25 -#define reg_pinmux_rw_gio_pb___pb25___width 1 -#define reg_pinmux_rw_gio_pb___pb25___bit 25 -#define reg_pinmux_rw_gio_pb___pb26___lsb 26 -#define reg_pinmux_rw_gio_pb___pb26___width 1 -#define reg_pinmux_rw_gio_pb___pb26___bit 26 -#define reg_pinmux_rw_gio_pb___pb27___lsb 27 -#define reg_pinmux_rw_gio_pb___pb27___width 1 -#define reg_pinmux_rw_gio_pb___pb27___bit 27 -#define reg_pinmux_rw_gio_pb___pb28___lsb 28 -#define reg_pinmux_rw_gio_pb___pb28___width 1 -#define reg_pinmux_rw_gio_pb___pb28___bit 28 -#define reg_pinmux_rw_gio_pb___pb29___lsb 29 -#define reg_pinmux_rw_gio_pb___pb29___width 1 -#define reg_pinmux_rw_gio_pb___pb29___bit 29 -#define reg_pinmux_rw_gio_pb___pb30___lsb 30 -#define reg_pinmux_rw_gio_pb___pb30___width 1 -#define reg_pinmux_rw_gio_pb___pb30___bit 30 -#define reg_pinmux_rw_gio_pb___pb31___lsb 31 -#define reg_pinmux_rw_gio_pb___pb31___width 1 -#define reg_pinmux_rw_gio_pb___pb31___bit 31 -#define reg_pinmux_rw_gio_pb_offset 8 - -/* Register rw_gio_pc, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pc___pc0___lsb 0 -#define reg_pinmux_rw_gio_pc___pc0___width 1 -#define reg_pinmux_rw_gio_pc___pc0___bit 0 -#define reg_pinmux_rw_gio_pc___pc1___lsb 1 -#define reg_pinmux_rw_gio_pc___pc1___width 1 -#define reg_pinmux_rw_gio_pc___pc1___bit 1 -#define reg_pinmux_rw_gio_pc___pc2___lsb 2 -#define reg_pinmux_rw_gio_pc___pc2___width 1 -#define reg_pinmux_rw_gio_pc___pc2___bit 2 -#define reg_pinmux_rw_gio_pc___pc3___lsb 3 -#define reg_pinmux_rw_gio_pc___pc3___width 1 -#define reg_pinmux_rw_gio_pc___pc3___bit 3 -#define reg_pinmux_rw_gio_pc___pc4___lsb 4 -#define reg_pinmux_rw_gio_pc___pc4___width 1 -#define reg_pinmux_rw_gio_pc___pc4___bit 4 -#define reg_pinmux_rw_gio_pc___pc5___lsb 5 -#define reg_pinmux_rw_gio_pc___pc5___width 1 -#define reg_pinmux_rw_gio_pc___pc5___bit 5 -#define reg_pinmux_rw_gio_pc___pc6___lsb 6 -#define reg_pinmux_rw_gio_pc___pc6___width 1 -#define reg_pinmux_rw_gio_pc___pc6___bit 6 -#define reg_pinmux_rw_gio_pc___pc7___lsb 7 -#define reg_pinmux_rw_gio_pc___pc7___width 1 -#define reg_pinmux_rw_gio_pc___pc7___bit 7 -#define reg_pinmux_rw_gio_pc___pc8___lsb 8 -#define reg_pinmux_rw_gio_pc___pc8___width 1 -#define reg_pinmux_rw_gio_pc___pc8___bit 8 -#define reg_pinmux_rw_gio_pc___pc9___lsb 9 -#define reg_pinmux_rw_gio_pc___pc9___width 1 -#define reg_pinmux_rw_gio_pc___pc9___bit 9 -#define reg_pinmux_rw_gio_pc___pc10___lsb 10 -#define reg_pinmux_rw_gio_pc___pc10___width 1 -#define reg_pinmux_rw_gio_pc___pc10___bit 10 -#define reg_pinmux_rw_gio_pc___pc11___lsb 11 -#define reg_pinmux_rw_gio_pc___pc11___width 1 -#define reg_pinmux_rw_gio_pc___pc11___bit 11 -#define reg_pinmux_rw_gio_pc___pc12___lsb 12 -#define reg_pinmux_rw_gio_pc___pc12___width 1 -#define reg_pinmux_rw_gio_pc___pc12___bit 12 -#define reg_pinmux_rw_gio_pc___pc13___lsb 13 -#define reg_pinmux_rw_gio_pc___pc13___width 1 -#define reg_pinmux_rw_gio_pc___pc13___bit 13 -#define reg_pinmux_rw_gio_pc___pc14___lsb 14 -#define reg_pinmux_rw_gio_pc___pc14___width 1 -#define reg_pinmux_rw_gio_pc___pc14___bit 14 -#define reg_pinmux_rw_gio_pc___pc15___lsb 15 -#define reg_pinmux_rw_gio_pc___pc15___width 1 -#define reg_pinmux_rw_gio_pc___pc15___bit 15 -#define reg_pinmux_rw_gio_pc_offset 12 - -/* Register rw_iop_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pa___pa0___lsb 0 -#define reg_pinmux_rw_iop_pa___pa0___width 1 -#define reg_pinmux_rw_iop_pa___pa0___bit 0 -#define reg_pinmux_rw_iop_pa___pa1___lsb 1 -#define reg_pinmux_rw_iop_pa___pa1___width 1 -#define reg_pinmux_rw_iop_pa___pa1___bit 1 -#define reg_pinmux_rw_iop_pa___pa2___lsb 2 -#define reg_pinmux_rw_iop_pa___pa2___width 1 -#define reg_pinmux_rw_iop_pa___pa2___bit 2 -#define reg_pinmux_rw_iop_pa___pa3___lsb 3 -#define reg_pinmux_rw_iop_pa___pa3___width 1 -#define reg_pinmux_rw_iop_pa___pa3___bit 3 -#define reg_pinmux_rw_iop_pa___pa4___lsb 4 -#define reg_pinmux_rw_iop_pa___pa4___width 1 -#define reg_pinmux_rw_iop_pa___pa4___bit 4 -#define reg_pinmux_rw_iop_pa___pa5___lsb 5 -#define reg_pinmux_rw_iop_pa___pa5___width 1 -#define reg_pinmux_rw_iop_pa___pa5___bit 5 -#define reg_pinmux_rw_iop_pa___pa6___lsb 6 -#define reg_pinmux_rw_iop_pa___pa6___width 1 -#define reg_pinmux_rw_iop_pa___pa6___bit 6 -#define reg_pinmux_rw_iop_pa___pa7___lsb 7 -#define reg_pinmux_rw_iop_pa___pa7___width 1 -#define reg_pinmux_rw_iop_pa___pa7___bit 7 -#define reg_pinmux_rw_iop_pa___pa8___lsb 8 -#define reg_pinmux_rw_iop_pa___pa8___width 1 -#define reg_pinmux_rw_iop_pa___pa8___bit 8 -#define reg_pinmux_rw_iop_pa___pa9___lsb 9 -#define reg_pinmux_rw_iop_pa___pa9___width 1 -#define reg_pinmux_rw_iop_pa___pa9___bit 9 -#define reg_pinmux_rw_iop_pa___pa10___lsb 10 -#define reg_pinmux_rw_iop_pa___pa10___width 1 -#define reg_pinmux_rw_iop_pa___pa10___bit 10 -#define reg_pinmux_rw_iop_pa___pa11___lsb 11 -#define reg_pinmux_rw_iop_pa___pa11___width 1 -#define reg_pinmux_rw_iop_pa___pa11___bit 11 -#define reg_pinmux_rw_iop_pa___pa12___lsb 12 -#define reg_pinmux_rw_iop_pa___pa12___width 1 -#define reg_pinmux_rw_iop_pa___pa12___bit 12 -#define reg_pinmux_rw_iop_pa___pa13___lsb 13 -#define reg_pinmux_rw_iop_pa___pa13___width 1 -#define reg_pinmux_rw_iop_pa___pa13___bit 13 -#define reg_pinmux_rw_iop_pa___pa14___lsb 14 -#define reg_pinmux_rw_iop_pa___pa14___width 1 -#define reg_pinmux_rw_iop_pa___pa14___bit 14 -#define reg_pinmux_rw_iop_pa___pa15___lsb 15 -#define reg_pinmux_rw_iop_pa___pa15___width 1 -#define reg_pinmux_rw_iop_pa___pa15___bit 15 -#define reg_pinmux_rw_iop_pa___pa16___lsb 16 -#define reg_pinmux_rw_iop_pa___pa16___width 1 -#define reg_pinmux_rw_iop_pa___pa16___bit 16 -#define reg_pinmux_rw_iop_pa___pa17___lsb 17 -#define reg_pinmux_rw_iop_pa___pa17___width 1 -#define reg_pinmux_rw_iop_pa___pa17___bit 17 -#define reg_pinmux_rw_iop_pa___pa18___lsb 18 -#define reg_pinmux_rw_iop_pa___pa18___width 1 -#define reg_pinmux_rw_iop_pa___pa18___bit 18 -#define reg_pinmux_rw_iop_pa___pa19___lsb 19 -#define reg_pinmux_rw_iop_pa___pa19___width 1 -#define reg_pinmux_rw_iop_pa___pa19___bit 19 -#define reg_pinmux_rw_iop_pa___pa20___lsb 20 -#define reg_pinmux_rw_iop_pa___pa20___width 1 -#define reg_pinmux_rw_iop_pa___pa20___bit 20 -#define reg_pinmux_rw_iop_pa___pa21___lsb 21 -#define reg_pinmux_rw_iop_pa___pa21___width 1 -#define reg_pinmux_rw_iop_pa___pa21___bit 21 -#define reg_pinmux_rw_iop_pa___pa22___lsb 22 -#define reg_pinmux_rw_iop_pa___pa22___width 1 -#define reg_pinmux_rw_iop_pa___pa22___bit 22 -#define reg_pinmux_rw_iop_pa___pa23___lsb 23 -#define reg_pinmux_rw_iop_pa___pa23___width 1 -#define reg_pinmux_rw_iop_pa___pa23___bit 23 -#define reg_pinmux_rw_iop_pa___pa24___lsb 24 -#define reg_pinmux_rw_iop_pa___pa24___width 1 -#define reg_pinmux_rw_iop_pa___pa24___bit 24 -#define reg_pinmux_rw_iop_pa___pa25___lsb 25 -#define reg_pinmux_rw_iop_pa___pa25___width 1 -#define reg_pinmux_rw_iop_pa___pa25___bit 25 -#define reg_pinmux_rw_iop_pa___pa26___lsb 26 -#define reg_pinmux_rw_iop_pa___pa26___width 1 -#define reg_pinmux_rw_iop_pa___pa26___bit 26 -#define reg_pinmux_rw_iop_pa___pa27___lsb 27 -#define reg_pinmux_rw_iop_pa___pa27___width 1 -#define reg_pinmux_rw_iop_pa___pa27___bit 27 -#define reg_pinmux_rw_iop_pa___pa28___lsb 28 -#define reg_pinmux_rw_iop_pa___pa28___width 1 -#define reg_pinmux_rw_iop_pa___pa28___bit 28 -#define reg_pinmux_rw_iop_pa___pa29___lsb 29 -#define reg_pinmux_rw_iop_pa___pa29___width 1 -#define reg_pinmux_rw_iop_pa___pa29___bit 29 -#define reg_pinmux_rw_iop_pa___pa30___lsb 30 -#define reg_pinmux_rw_iop_pa___pa30___width 1 -#define reg_pinmux_rw_iop_pa___pa30___bit 30 -#define reg_pinmux_rw_iop_pa___pa31___lsb 31 -#define reg_pinmux_rw_iop_pa___pa31___width 1 -#define reg_pinmux_rw_iop_pa___pa31___bit 31 -#define reg_pinmux_rw_iop_pa_offset 16 - -/* Register rw_iop_pb, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pb___pb0___lsb 0 -#define reg_pinmux_rw_iop_pb___pb0___width 1 -#define reg_pinmux_rw_iop_pb___pb0___bit 0 -#define reg_pinmux_rw_iop_pb___pb1___lsb 1 -#define reg_pinmux_rw_iop_pb___pb1___width 1 -#define reg_pinmux_rw_iop_pb___pb1___bit 1 -#define reg_pinmux_rw_iop_pb___pb2___lsb 2 -#define reg_pinmux_rw_iop_pb___pb2___width 1 -#define reg_pinmux_rw_iop_pb___pb2___bit 2 -#define reg_pinmux_rw_iop_pb___pb3___lsb 3 -#define reg_pinmux_rw_iop_pb___pb3___width 1 -#define reg_pinmux_rw_iop_pb___pb3___bit 3 -#define reg_pinmux_rw_iop_pb___pb4___lsb 4 -#define reg_pinmux_rw_iop_pb___pb4___width 1 -#define reg_pinmux_rw_iop_pb___pb4___bit 4 -#define reg_pinmux_rw_iop_pb___pb5___lsb 5 -#define reg_pinmux_rw_iop_pb___pb5___width 1 -#define reg_pinmux_rw_iop_pb___pb5___bit 5 -#define reg_pinmux_rw_iop_pb___pb6___lsb 6 -#define reg_pinmux_rw_iop_pb___pb6___width 1 -#define reg_pinmux_rw_iop_pb___pb6___bit 6 -#define reg_pinmux_rw_iop_pb___pb7___lsb 7 -#define reg_pinmux_rw_iop_pb___pb7___width 1 -#define reg_pinmux_rw_iop_pb___pb7___bit 7 -#define reg_pinmux_rw_iop_pb_offset 20 - -/* Register rw_iop_pio, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pio___d0___lsb 0 -#define reg_pinmux_rw_iop_pio___d0___width 1 -#define reg_pinmux_rw_iop_pio___d0___bit 0 -#define reg_pinmux_rw_iop_pio___d1___lsb 1 -#define reg_pinmux_rw_iop_pio___d1___width 1 -#define reg_pinmux_rw_iop_pio___d1___bit 1 -#define reg_pinmux_rw_iop_pio___d2___lsb 2 -#define reg_pinmux_rw_iop_pio___d2___width 1 -#define reg_pinmux_rw_iop_pio___d2___bit 2 -#define reg_pinmux_rw_iop_pio___d3___lsb 3 -#define reg_pinmux_rw_iop_pio___d3___width 1 -#define reg_pinmux_rw_iop_pio___d3___bit 3 -#define reg_pinmux_rw_iop_pio___d4___lsb 4 -#define reg_pinmux_rw_iop_pio___d4___width 1 -#define reg_pinmux_rw_iop_pio___d4___bit 4 -#define reg_pinmux_rw_iop_pio___d5___lsb 5 -#define reg_pinmux_rw_iop_pio___d5___width 1 -#define reg_pinmux_rw_iop_pio___d5___bit 5 -#define reg_pinmux_rw_iop_pio___d6___lsb 6 -#define reg_pinmux_rw_iop_pio___d6___width 1 -#define reg_pinmux_rw_iop_pio___d6___bit 6 -#define reg_pinmux_rw_iop_pio___d7___lsb 7 -#define reg_pinmux_rw_iop_pio___d7___width 1 -#define reg_pinmux_rw_iop_pio___d7___bit 7 -#define reg_pinmux_rw_iop_pio___rd_n___lsb 8 -#define reg_pinmux_rw_iop_pio___rd_n___width 1 -#define reg_pinmux_rw_iop_pio___rd_n___bit 8 -#define reg_pinmux_rw_iop_pio___wr_n___lsb 9 -#define reg_pinmux_rw_iop_pio___wr_n___width 1 -#define reg_pinmux_rw_iop_pio___wr_n___bit 9 -#define reg_pinmux_rw_iop_pio___a0___lsb 10 -#define reg_pinmux_rw_iop_pio___a0___width 1 -#define reg_pinmux_rw_iop_pio___a0___bit 10 -#define reg_pinmux_rw_iop_pio___a1___lsb 11 -#define reg_pinmux_rw_iop_pio___a1___width 1 -#define reg_pinmux_rw_iop_pio___a1___bit 11 -#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 -#define reg_pinmux_rw_iop_pio___ce0_n___width 1 -#define reg_pinmux_rw_iop_pio___ce0_n___bit 12 -#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 -#define reg_pinmux_rw_iop_pio___ce1_n___width 1 -#define reg_pinmux_rw_iop_pio___ce1_n___bit 13 -#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 -#define reg_pinmux_rw_iop_pio___ce2_n___width 1 -#define reg_pinmux_rw_iop_pio___ce2_n___bit 14 -#define reg_pinmux_rw_iop_pio___rdy___lsb 15 -#define reg_pinmux_rw_iop_pio___rdy___width 1 -#define reg_pinmux_rw_iop_pio___rdy___bit 15 -#define reg_pinmux_rw_iop_pio_offset 24 - -/* Register rw_iop_usb, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_usb___usb0___lsb 0 -#define reg_pinmux_rw_iop_usb___usb0___width 1 -#define reg_pinmux_rw_iop_usb___usb0___bit 0 -#define reg_pinmux_rw_iop_usb_offset 28 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_gio_pa_default 0x00000000 -#define regk_pinmux_rw_gio_pb_default 0x00000000 -#define regk_pinmux_rw_gio_pc_default 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_iop_pa_default 0x00000000 -#define regk_pinmux_rw_iop_pb_default 0x00000000 -#define regk_pinmux_rw_iop_pio_default 0x00000000 -#define regk_pinmux_rw_iop_usb_default 0x00000001 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h deleted file mode 100644 index 3907ef4921c8..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h +++ /dev/null @@ -1,337 +0,0 @@ -#ifndef __pio_defs_asm_h -#define __pio_defs_asm_h - -/* - * This file is autogenerated from - * file: pio.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope pio, type rw */ -#define reg_pio_rw_data_offset 64 - -/* Register rw_io_access0, scope pio, type rw */ -#define reg_pio_rw_io_access0___data___lsb 0 -#define reg_pio_rw_io_access0___data___width 8 -#define reg_pio_rw_io_access0_offset 0 - -/* Register rw_io_access1, scope pio, type rw */ -#define reg_pio_rw_io_access1___data___lsb 0 -#define reg_pio_rw_io_access1___data___width 8 -#define reg_pio_rw_io_access1_offset 4 - -/* Register rw_io_access2, scope pio, type rw */ -#define reg_pio_rw_io_access2___data___lsb 0 -#define reg_pio_rw_io_access2___data___width 8 -#define reg_pio_rw_io_access2_offset 8 - -/* Register rw_io_access3, scope pio, type rw */ -#define reg_pio_rw_io_access3___data___lsb 0 -#define reg_pio_rw_io_access3___data___width 8 -#define reg_pio_rw_io_access3_offset 12 - -/* Register rw_io_access4, scope pio, type rw */ -#define reg_pio_rw_io_access4___data___lsb 0 -#define reg_pio_rw_io_access4___data___width 8 -#define reg_pio_rw_io_access4_offset 16 - -/* Register rw_io_access5, scope pio, type rw */ -#define reg_pio_rw_io_access5___data___lsb 0 -#define reg_pio_rw_io_access5___data___width 8 -#define reg_pio_rw_io_access5_offset 20 - -/* Register rw_io_access6, scope pio, type rw */ -#define reg_pio_rw_io_access6___data___lsb 0 -#define reg_pio_rw_io_access6___data___width 8 -#define reg_pio_rw_io_access6_offset 24 - -/* Register rw_io_access7, scope pio, type rw */ -#define reg_pio_rw_io_access7___data___lsb 0 -#define reg_pio_rw_io_access7___data___width 8 -#define reg_pio_rw_io_access7_offset 28 - -/* Register rw_io_access8, scope pio, type rw */ -#define reg_pio_rw_io_access8___data___lsb 0 -#define reg_pio_rw_io_access8___data___width 8 -#define reg_pio_rw_io_access8_offset 32 - -/* Register rw_io_access9, scope pio, type rw */ -#define reg_pio_rw_io_access9___data___lsb 0 -#define reg_pio_rw_io_access9___data___width 8 -#define reg_pio_rw_io_access9_offset 36 - -/* Register rw_io_access10, scope pio, type rw */ -#define reg_pio_rw_io_access10___data___lsb 0 -#define reg_pio_rw_io_access10___data___width 8 -#define reg_pio_rw_io_access10_offset 40 - -/* Register rw_io_access11, scope pio, type rw */ -#define reg_pio_rw_io_access11___data___lsb 0 -#define reg_pio_rw_io_access11___data___width 8 -#define reg_pio_rw_io_access11_offset 44 - -/* Register rw_io_access12, scope pio, type rw */ -#define reg_pio_rw_io_access12___data___lsb 0 -#define reg_pio_rw_io_access12___data___width 8 -#define reg_pio_rw_io_access12_offset 48 - -/* Register rw_io_access13, scope pio, type rw */ -#define reg_pio_rw_io_access13___data___lsb 0 -#define reg_pio_rw_io_access13___data___width 8 -#define reg_pio_rw_io_access13_offset 52 - -/* Register rw_io_access14, scope pio, type rw */ -#define reg_pio_rw_io_access14___data___lsb 0 -#define reg_pio_rw_io_access14___data___width 8 -#define reg_pio_rw_io_access14_offset 56 - -/* Register rw_io_access15, scope pio, type rw */ -#define reg_pio_rw_io_access15___data___lsb 0 -#define reg_pio_rw_io_access15___data___width 8 -#define reg_pio_rw_io_access15_offset 60 - -/* Register rw_ce0_cfg, scope pio, type rw */ -#define reg_pio_rw_ce0_cfg___lw___lsb 0 -#define reg_pio_rw_ce0_cfg___lw___width 6 -#define reg_pio_rw_ce0_cfg___ew___lsb 6 -#define reg_pio_rw_ce0_cfg___ew___width 3 -#define reg_pio_rw_ce0_cfg___zw___lsb 9 -#define reg_pio_rw_ce0_cfg___zw___width 3 -#define reg_pio_rw_ce0_cfg___aw___lsb 12 -#define reg_pio_rw_ce0_cfg___aw___width 2 -#define reg_pio_rw_ce0_cfg___mode___lsb 14 -#define reg_pio_rw_ce0_cfg___mode___width 2 -#define reg_pio_rw_ce0_cfg_offset 68 - -/* Register rw_ce1_cfg, scope pio, type rw */ -#define reg_pio_rw_ce1_cfg___lw___lsb 0 -#define reg_pio_rw_ce1_cfg___lw___width 6 -#define reg_pio_rw_ce1_cfg___ew___lsb 6 -#define reg_pio_rw_ce1_cfg___ew___width 3 -#define reg_pio_rw_ce1_cfg___zw___lsb 9 -#define reg_pio_rw_ce1_cfg___zw___width 3 -#define reg_pio_rw_ce1_cfg___aw___lsb 12 -#define reg_pio_rw_ce1_cfg___aw___width 2 -#define reg_pio_rw_ce1_cfg___mode___lsb 14 -#define reg_pio_rw_ce1_cfg___mode___width 2 -#define reg_pio_rw_ce1_cfg_offset 72 - -/* Register rw_ce2_cfg, scope pio, type rw */ -#define reg_pio_rw_ce2_cfg___lw___lsb 0 -#define reg_pio_rw_ce2_cfg___lw___width 6 -#define reg_pio_rw_ce2_cfg___ew___lsb 6 -#define reg_pio_rw_ce2_cfg___ew___width 3 -#define reg_pio_rw_ce2_cfg___zw___lsb 9 -#define reg_pio_rw_ce2_cfg___zw___width 3 -#define reg_pio_rw_ce2_cfg___aw___lsb 12 -#define reg_pio_rw_ce2_cfg___aw___width 2 -#define reg_pio_rw_ce2_cfg___mode___lsb 14 -#define reg_pio_rw_ce2_cfg___mode___width 2 -#define reg_pio_rw_ce2_cfg_offset 76 - -/* Register rw_dout, scope pio, type rw */ -#define reg_pio_rw_dout___data___lsb 0 -#define reg_pio_rw_dout___data___width 8 -#define reg_pio_rw_dout___rd_n___lsb 8 -#define reg_pio_rw_dout___rd_n___width 1 -#define reg_pio_rw_dout___rd_n___bit 8 -#define reg_pio_rw_dout___wr_n___lsb 9 -#define reg_pio_rw_dout___wr_n___width 1 -#define reg_pio_rw_dout___wr_n___bit 9 -#define reg_pio_rw_dout___a0___lsb 10 -#define reg_pio_rw_dout___a0___width 1 -#define reg_pio_rw_dout___a0___bit 10 -#define reg_pio_rw_dout___a1___lsb 11 -#define reg_pio_rw_dout___a1___width 1 -#define reg_pio_rw_dout___a1___bit 11 -#define reg_pio_rw_dout___ce0_n___lsb 12 -#define reg_pio_rw_dout___ce0_n___width 1 -#define reg_pio_rw_dout___ce0_n___bit 12 -#define reg_pio_rw_dout___ce1_n___lsb 13 -#define reg_pio_rw_dout___ce1_n___width 1 -#define reg_pio_rw_dout___ce1_n___bit 13 -#define reg_pio_rw_dout___ce2_n___lsb 14 -#define reg_pio_rw_dout___ce2_n___width 1 -#define reg_pio_rw_dout___ce2_n___bit 14 -#define reg_pio_rw_dout___rdy___lsb 15 -#define reg_pio_rw_dout___rdy___width 1 -#define reg_pio_rw_dout___rdy___bit 15 -#define reg_pio_rw_dout_offset 80 - -/* Register rw_oe, scope pio, type rw */ -#define reg_pio_rw_oe___data___lsb 0 -#define reg_pio_rw_oe___data___width 8 -#define reg_pio_rw_oe___rd_n___lsb 8 -#define reg_pio_rw_oe___rd_n___width 1 -#define reg_pio_rw_oe___rd_n___bit 8 -#define reg_pio_rw_oe___wr_n___lsb 9 -#define reg_pio_rw_oe___wr_n___width 1 -#define reg_pio_rw_oe___wr_n___bit 9 -#define reg_pio_rw_oe___a0___lsb 10 -#define reg_pio_rw_oe___a0___width 1 -#define reg_pio_rw_oe___a0___bit 10 -#define reg_pio_rw_oe___a1___lsb 11 -#define reg_pio_rw_oe___a1___width 1 -#define reg_pio_rw_oe___a1___bit 11 -#define reg_pio_rw_oe___ce0_n___lsb 12 -#define reg_pio_rw_oe___ce0_n___width 1 -#define reg_pio_rw_oe___ce0_n___bit 12 -#define reg_pio_rw_oe___ce1_n___lsb 13 -#define reg_pio_rw_oe___ce1_n___width 1 -#define reg_pio_rw_oe___ce1_n___bit 13 -#define reg_pio_rw_oe___ce2_n___lsb 14 -#define reg_pio_rw_oe___ce2_n___width 1 -#define reg_pio_rw_oe___ce2_n___bit 14 -#define reg_pio_rw_oe___rdy___lsb 15 -#define reg_pio_rw_oe___rdy___width 1 -#define reg_pio_rw_oe___rdy___bit 15 -#define reg_pio_rw_oe_offset 84 - -/* Register rw_man_ctrl, scope pio, type rw */ -#define reg_pio_rw_man_ctrl___data___lsb 0 -#define reg_pio_rw_man_ctrl___data___width 8 -#define reg_pio_rw_man_ctrl___rd_n___lsb 8 -#define reg_pio_rw_man_ctrl___rd_n___width 1 -#define reg_pio_rw_man_ctrl___rd_n___bit 8 -#define reg_pio_rw_man_ctrl___wr_n___lsb 9 -#define reg_pio_rw_man_ctrl___wr_n___width 1 -#define reg_pio_rw_man_ctrl___wr_n___bit 9 -#define reg_pio_rw_man_ctrl___a0___lsb 10 -#define reg_pio_rw_man_ctrl___a0___width 1 -#define reg_pio_rw_man_ctrl___a0___bit 10 -#define reg_pio_rw_man_ctrl___a1___lsb 11 -#define reg_pio_rw_man_ctrl___a1___width 1 -#define reg_pio_rw_man_ctrl___a1___bit 11 -#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 -#define reg_pio_rw_man_ctrl___ce0_n___width 1 -#define reg_pio_rw_man_ctrl___ce0_n___bit 12 -#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 -#define reg_pio_rw_man_ctrl___ce1_n___width 1 -#define reg_pio_rw_man_ctrl___ce1_n___bit 13 -#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 -#define reg_pio_rw_man_ctrl___ce2_n___width 1 -#define reg_pio_rw_man_ctrl___ce2_n___bit 14 -#define reg_pio_rw_man_ctrl___rdy___lsb 15 -#define reg_pio_rw_man_ctrl___rdy___width 1 -#define reg_pio_rw_man_ctrl___rdy___bit 15 -#define reg_pio_rw_man_ctrl_offset 88 - -/* Register r_din, scope pio, type r */ -#define reg_pio_r_din___data___lsb 0 -#define reg_pio_r_din___data___width 8 -#define reg_pio_r_din___rd_n___lsb 8 -#define reg_pio_r_din___rd_n___width 1 -#define reg_pio_r_din___rd_n___bit 8 -#define reg_pio_r_din___wr_n___lsb 9 -#define reg_pio_r_din___wr_n___width 1 -#define reg_pio_r_din___wr_n___bit 9 -#define reg_pio_r_din___a0___lsb 10 -#define reg_pio_r_din___a0___width 1 -#define reg_pio_r_din___a0___bit 10 -#define reg_pio_r_din___a1___lsb 11 -#define reg_pio_r_din___a1___width 1 -#define reg_pio_r_din___a1___bit 11 -#define reg_pio_r_din___ce0_n___lsb 12 -#define reg_pio_r_din___ce0_n___width 1 -#define reg_pio_r_din___ce0_n___bit 12 -#define reg_pio_r_din___ce1_n___lsb 13 -#define reg_pio_r_din___ce1_n___width 1 -#define reg_pio_r_din___ce1_n___bit 13 -#define reg_pio_r_din___ce2_n___lsb 14 -#define reg_pio_r_din___ce2_n___width 1 -#define reg_pio_r_din___ce2_n___bit 14 -#define reg_pio_r_din___rdy___lsb 15 -#define reg_pio_r_din___rdy___width 1 -#define reg_pio_r_din___rdy___bit 15 -#define reg_pio_r_din_offset 92 - -/* Register r_stat, scope pio, type r */ -#define reg_pio_r_stat___busy___lsb 0 -#define reg_pio_r_stat___busy___width 1 -#define reg_pio_r_stat___busy___bit 0 -#define reg_pio_r_stat_offset 96 - -/* Register rw_intr_mask, scope pio, type rw */ -#define reg_pio_rw_intr_mask___rdy___lsb 0 -#define reg_pio_rw_intr_mask___rdy___width 1 -#define reg_pio_rw_intr_mask___rdy___bit 0 -#define reg_pio_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope pio, type rw */ -#define reg_pio_rw_ack_intr___rdy___lsb 0 -#define reg_pio_rw_ack_intr___rdy___width 1 -#define reg_pio_rw_ack_intr___rdy___bit 0 -#define reg_pio_rw_ack_intr_offset 104 - -/* Register r_intr, scope pio, type r */ -#define reg_pio_r_intr___rdy___lsb 0 -#define reg_pio_r_intr___rdy___width 1 -#define reg_pio_r_intr___rdy___bit 0 -#define reg_pio_r_intr_offset 108 - -/* Register r_masked_intr, scope pio, type r */ -#define reg_pio_r_masked_intr___rdy___lsb 0 -#define reg_pio_r_masked_intr___rdy___width 1 -#define reg_pio_r_masked_intr___rdy___bit 0 -#define reg_pio_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_pio_a2 0x00000003 -#define regk_pio_no 0x00000000 -#define regk_pio_normal 0x00000000 -#define regk_pio_rd 0x00000001 -#define regk_pio_rw_ce0_cfg_default 0x00000000 -#define regk_pio_rw_ce1_cfg_default 0x00000000 -#define regk_pio_rw_ce2_cfg_default 0x00000000 -#define regk_pio_rw_intr_mask_default 0x00000000 -#define regk_pio_rw_man_ctrl_default 0x00000000 -#define regk_pio_rw_oe_default 0x00000000 -#define regk_pio_wr 0x00000002 -#define regk_pio_wr_ce2 0x00000003 -#define regk_pio_yes 0x00000001 -#define regk_pio_yes_all 0x000000ff -#endif /* __pio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 89439e9610e2..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef __reg_map_asm_h -#define __reg_map_asm_h - -/* - * This file is autogenerated from - * file: reg.rmap - * - * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_ccd 0xb0000000 -#define regi_ccd_top 0xb0000000 -#define regi_ccd_dp 0xb0000400 -#define regi_ccd_stat 0xb0000800 -#define regi_ccd_tg 0xb0001000 -#define regi_cfg 0xb0002000 -#define regi_clkgen 0xb0004000 -#define regi_ddr2_ctrl 0xb0006000 -#define regi_dma0 0xb0008000 -#define regi_dma1 0xb000a000 -#define regi_dma11 0xb000c000 -#define regi_dma2 0xb000e000 -#define regi_dma3 0xb0010000 -#define regi_dma4 0xb0012000 -#define regi_dma5 0xb0014000 -#define regi_dma6 0xb0016000 -#define regi_dma7 0xb0018000 -#define regi_dma9 0xb001a000 -#define regi_eth 0xb001c000 -#define regi_gio 0xb0020000 -#define regi_h264 0xb0022000 -#define regi_hist 0xb0026000 -#define regi_iop 0xb0028000 -#define regi_iop_version 0xb0028000 -#define regi_iop_fifo_in_extra 0xb0028040 -#define regi_iop_fifo_out_extra 0xb0028080 -#define regi_iop_trigger_grp0 0xb00280c0 -#define regi_iop_trigger_grp1 0xb0028100 -#define regi_iop_trigger_grp2 0xb0028140 -#define regi_iop_trigger_grp3 0xb0028180 -#define regi_iop_trigger_grp4 0xb00281c0 -#define regi_iop_trigger_grp5 0xb0028200 -#define regi_iop_trigger_grp6 0xb0028240 -#define regi_iop_trigger_grp7 0xb0028280 -#define regi_iop_crc_par 0xb0028300 -#define regi_iop_dmc_in 0xb0028380 -#define regi_iop_dmc_out 0xb0028400 -#define regi_iop_fifo_in 0xb0028480 -#define regi_iop_fifo_out 0xb0028500 -#define regi_iop_scrc_in 0xb0028580 -#define regi_iop_scrc_out 0xb0028600 -#define regi_iop_timer_grp0 0xb0028680 -#define regi_iop_timer_grp1 0xb0028700 -#define regi_iop_sap_in 0xb0028800 -#define regi_iop_sap_out 0xb0028900 -#define regi_iop_spu 0xb0028a00 -#define regi_iop_sw_cfg 0xb0028b00 -#define regi_iop_sw_cpu 0xb0028c00 -#define regi_iop_sw_mpu 0xb0028d00 -#define regi_iop_sw_spu 0xb0028e00 -#define regi_iop_mpu 0xb0029000 -#define regi_irq 0xb002a000 -#define regi_jpeg 0xb002c000 -#define regi_l2cache 0xb0030000 -#define regi_marb_bar 0xb0032000 -#define regi_marb_bar_bp0 0xb0032140 -#define regi_marb_bar_bp1 0xb0032180 -#define regi_marb_bar_bp2 0xb00321c0 -#define regi_marb_bar_bp3 0xb0032200 -#define regi_marb_foo 0xb0034000 -#define regi_marb_foo_bp0 0xb0034280 -#define regi_marb_foo_bp1 0xb00342c0 -#define regi_marb_foo_bp2 0xb0034300 -#define regi_marb_foo_bp3 0xb0034340 -#define regi_pinmux 0xb0038000 -#define regi_pio 0xb0036000 -#define regi_sclr 0xb003a000 -#define regi_sclr_fifo 0xb003c000 -#define regi_ser0 0xb003e000 -#define regi_ser1 0xb0040000 -#define regi_ser2 0xb0042000 -#define regi_ser3 0xb0044000 -#define regi_ser4 0xb0046000 -#define regi_sser 0xb0048000 -#define regi_strcop 0xb004a000 -#define regi_strdma0 0xb004e000 -#define regi_strdma1 0xb0050000 -#define regi_strdma2 0xb0052000 -#define regi_strdma3 0xb0054000 -#define regi_strdma5 0xb0056000 -#define regi_strmux 0xb004c000 -#define regi_timer0 0xb0058000 -#define regi_timer1 0xb005a000 -#define regi_trace 0xb005c000 -#define regi_vin 0xb005e000 -#define regi_vout 0xb0060000 -#endif /* __reg_map_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index b129e826fc34..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: timer.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_f90 0x00000003 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_vclk 0x00000002 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h deleted file mode 100644 index c1e9ba93b3a3..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h +++ /dev/null @@ -1,159 +0,0 @@ -#ifndef __clkgen_defs_h -#define __clkgen_defs_h - -/* - * This file is autogenerated from - * file: clkgen.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope clkgen */ - -/* Register r_bootsel, scope clkgen, type r */ -typedef struct { - unsigned int boot_mode : 5; - unsigned int intern_main_clk : 1; - unsigned int extern_usb2_clk : 1; - unsigned int dummy1 : 25; -} reg_clkgen_r_bootsel; -#define REG_RD_ADDR_clkgen_r_bootsel 0 - -/* Register rw_clk_ctrl, scope clkgen, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop_usb : 1; - unsigned int vin : 1; - unsigned int sclr : 1; - unsigned int h264 : 1; - unsigned int ddr2 : 1; - unsigned int vout_hist : 1; - unsigned int eth : 1; - unsigned int ccd_tg_200 : 1; - unsigned int dma0_1_eth : 1; - unsigned int ccd_tg_100 : 1; - unsigned int jpeg : 1; - unsigned int sser_ser_dma6_7 : 1; - unsigned int strdma0_2_video : 1; - unsigned int dma2_3_strcop : 1; - unsigned int dma4_5_iop : 1; - unsigned int dma9_11 : 1; - unsigned int memarb_bar_ddr : 1; - unsigned int sclr_h264 : 1; - unsigned int dummy1 : 12; -} reg_clkgen_rw_clk_ctrl; -#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 -#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 - - -/* Constants */ -enum { - regk_clkgen_eth1000_rx = 0x0000000c, - regk_clkgen_eth1000_tx = 0x0000000e, - regk_clkgen_eth100_rx = 0x0000001d, - regk_clkgen_eth100_rx_half = 0x0000001c, - regk_clkgen_eth100_tx = 0x0000001f, - regk_clkgen_eth100_tx_half = 0x0000001e, - regk_clkgen_nand_3_2 = 0x00000000, - regk_clkgen_nand_3_2_0x30 = 0x00000002, - regk_clkgen_nand_3_2_0x30_pll = 0x00000012, - regk_clkgen_nand_3_2_pll = 0x00000010, - regk_clkgen_nand_3_3 = 0x00000001, - regk_clkgen_nand_3_3_0x30 = 0x00000003, - regk_clkgen_nand_3_3_0x30_pll = 0x00000013, - regk_clkgen_nand_3_3_pll = 0x00000011, - regk_clkgen_nand_4_2 = 0x00000004, - regk_clkgen_nand_4_2_0x30 = 0x00000006, - regk_clkgen_nand_4_2_0x30_pll = 0x00000016, - regk_clkgen_nand_4_2_pll = 0x00000014, - regk_clkgen_nand_4_3 = 0x00000005, - regk_clkgen_nand_4_3_0x30 = 0x00000007, - regk_clkgen_nand_4_3_0x30_pll = 0x00000017, - regk_clkgen_nand_4_3_pll = 0x00000015, - regk_clkgen_nand_5_2 = 0x00000008, - regk_clkgen_nand_5_2_0x30 = 0x0000000a, - regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, - regk_clkgen_nand_5_2_pll = 0x00000018, - regk_clkgen_nand_5_3 = 0x00000009, - regk_clkgen_nand_5_3_0x30 = 0x0000000b, - regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, - regk_clkgen_nand_5_3_pll = 0x00000019, - regk_clkgen_no = 0x00000000, - regk_clkgen_rw_clk_ctrl_default = 0x00000002, - regk_clkgen_ser = 0x0000000d, - regk_clkgen_ser_pll = 0x0000000f, - regk_clkgen_yes = 0x00000001 -}; -#endif /* __clkgen_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h deleted file mode 100644 index 0f30e8bf946d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h +++ /dev/null @@ -1,281 +0,0 @@ -#ifndef __ddr2_defs_h -#define __ddr2_defs_h - -/* - * This file is autogenerated from - * file: ddr2.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ddr2 */ - -/* Register rw_cfg, scope ddr2, type rw */ -typedef struct { - unsigned int col_width : 4; - unsigned int nr_banks : 1; - unsigned int bw : 1; - unsigned int nr_ref : 4; - unsigned int ref_interval : 11; - unsigned int odt_ctrl : 2; - unsigned int odt_mem : 1; - unsigned int imp_strength : 1; - unsigned int auto_imp_cal : 1; - unsigned int imp_cal_override : 1; - unsigned int dll_override : 1; - unsigned int dummy1 : 4; -} reg_ddr2_rw_cfg; -#define REG_RD_ADDR_ddr2_rw_cfg 0 -#define REG_WR_ADDR_ddr2_rw_cfg 0 - -/* Register rw_timing, scope ddr2, type rw */ -typedef struct { - unsigned int wr : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int ras : 4; - unsigned int rfc : 7; - unsigned int rc : 5; - unsigned int rtp : 2; - unsigned int rtw : 3; - unsigned int wtr : 2; -} reg_ddr2_rw_timing; -#define REG_RD_ADDR_ddr2_rw_timing 4 -#define REG_WR_ADDR_ddr2_rw_timing 4 - -/* Register rw_latency, scope ddr2, type rw */ -typedef struct { - unsigned int cas : 3; - unsigned int additive : 3; - unsigned int dummy1 : 26; -} reg_ddr2_rw_latency; -#define REG_RD_ADDR_ddr2_rw_latency 8 -#define REG_WR_ADDR_ddr2_rw_latency 8 - -/* Register rw_phy_cfg, scope ddr2, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ddr2_rw_phy_cfg; -#define REG_RD_ADDR_ddr2_rw_phy_cfg 12 -#define REG_WR_ADDR_ddr2_rw_phy_cfg 12 - -/* Register rw_phy_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int rst : 1; - unsigned int cal_rst : 1; - unsigned int cal_start : 1; - unsigned int dummy1 : 29; -} reg_ddr2_rw_phy_ctrl; -#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 -#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 - -/* Register rw_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int mrs_data : 16; - unsigned int cmd : 8; - unsigned int dummy1 : 8; -} reg_ddr2_rw_ctrl; -#define REG_RD_ADDR_ddr2_rw_ctrl 20 -#define REG_WR_ADDR_ddr2_rw_ctrl 20 - -/* Register rw_pwr_down, scope ddr2, type rw */ -typedef struct { - unsigned int self_ref : 2; - unsigned int phy_en : 1; - unsigned int dummy1 : 29; -} reg_ddr2_rw_pwr_down; -#define REG_RD_ADDR_ddr2_rw_pwr_down 24 -#define REG_WR_ADDR_ddr2_rw_pwr_down 24 - -/* Register r_stat, scope ddr2, type r */ -typedef struct { - unsigned int dll_lock : 1; - unsigned int dll_delay_code : 7; - unsigned int imp_cal_done : 1; - unsigned int imp_cal_fault : 1; - unsigned int cal_imp_pu : 4; - unsigned int cal_imp_pd : 4; - unsigned int dummy1 : 14; -} reg_ddr2_r_stat; -#define REG_RD_ADDR_ddr2_r_stat 28 - -/* Register rw_imp_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int imp_pu : 4; - unsigned int imp_pd : 4; - unsigned int dummy1 : 24; -} reg_ddr2_rw_imp_ctrl; -#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 -#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 - -#define STRIDE_ddr2_rw_dll_ctrl 4 -/* Register rw_dll_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int clk_delay : 7; - unsigned int dummy1 : 24; -} reg_ddr2_rw_dll_ctrl; -#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 -#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 - -#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 -/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int dqs90_delay : 7; - unsigned int dqs180_delay : 7; - unsigned int dqs270_delay : 7; - unsigned int dqs360_delay : 7; - unsigned int dummy1 : 4; -} reg_ddr2_rw_dqs_dll_ctrl; -#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 -#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 - - -/* Constants */ -enum { - regk_ddr2_al0 = 0x00000000, - regk_ddr2_al1 = 0x00000008, - regk_ddr2_al2 = 0x00000010, - regk_ddr2_al3 = 0x00000018, - regk_ddr2_al4 = 0x00000020, - regk_ddr2_auto = 0x00000003, - regk_ddr2_bank4 = 0x00000000, - regk_ddr2_bank8 = 0x00000001, - regk_ddr2_bl4 = 0x00000002, - regk_ddr2_bl8 = 0x00000003, - regk_ddr2_bt_il = 0x00000008, - regk_ddr2_bt_seq = 0x00000000, - regk_ddr2_bw16 = 0x00000001, - regk_ddr2_bw32 = 0x00000000, - regk_ddr2_cas2 = 0x00000020, - regk_ddr2_cas3 = 0x00000030, - regk_ddr2_cas4 = 0x00000040, - regk_ddr2_cas5 = 0x00000050, - regk_ddr2_deselect = 0x000000c0, - regk_ddr2_dic_weak = 0x00000002, - regk_ddr2_direct = 0x00000001, - regk_ddr2_dis = 0x00000000, - regk_ddr2_dll_dis = 0x00000001, - regk_ddr2_dll_en = 0x00000000, - regk_ddr2_dll_rst = 0x00000100, - regk_ddr2_emrs = 0x00000081, - regk_ddr2_emrs2 = 0x00000082, - regk_ddr2_emrs3 = 0x00000083, - regk_ddr2_full = 0x00000001, - regk_ddr2_hi_ref_rate = 0x00000080, - regk_ddr2_mrs = 0x00000080, - regk_ddr2_no = 0x00000000, - regk_ddr2_nop = 0x000000b8, - regk_ddr2_ocd_adj = 0x00000200, - regk_ddr2_ocd_default = 0x00000380, - regk_ddr2_ocd_drive0 = 0x00000100, - regk_ddr2_ocd_drive1 = 0x00000080, - regk_ddr2_ocd_exit = 0x00000000, - regk_ddr2_odt_dis = 0x00000000, - regk_ddr2_offs = 0x00000000, - regk_ddr2_pre = 0x00000090, - regk_ddr2_pre_all = 0x00000400, - regk_ddr2_pwr_down_fast = 0x00000000, - regk_ddr2_pwr_down_slow = 0x00001000, - regk_ddr2_ref = 0x00000088, - regk_ddr2_rtt150 = 0x00000040, - regk_ddr2_rtt50 = 0x00000044, - regk_ddr2_rtt75 = 0x00000004, - regk_ddr2_rw_cfg_default = 0x00186000, - regk_ddr2_rw_dll_ctrl_default = 0x00000000, - regk_ddr2_rw_dll_ctrl_size = 0x00000004, - regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, - regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, - regk_ddr2_rw_latency_default = 0x00000000, - regk_ddr2_rw_phy_cfg_default = 0x00000000, - regk_ddr2_rw_pwr_down_default = 0x00000000, - regk_ddr2_rw_timing_default = 0x00000000, - regk_ddr2_s1Gb = 0x0000001a, - regk_ddr2_s256Mb = 0x0000000f, - regk_ddr2_s2Gb = 0x00000027, - regk_ddr2_s4Gb = 0x00000042, - regk_ddr2_s512Mb = 0x00000015, - regk_ddr2_temp0_85 = 0x00000618, - regk_ddr2_temp85_95 = 0x0000030c, - regk_ddr2_term150 = 0x00000002, - regk_ddr2_term50 = 0x00000003, - regk_ddr2_term75 = 0x00000001, - regk_ddr2_test = 0x00000080, - regk_ddr2_weak = 0x00000000, - regk_ddr2_wr2 = 0x00000200, - regk_ddr2_wr3 = 0x00000400, - regk_ddr2_yes = 0x00000001 -}; -#endif /* __ddr2_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h deleted file mode 100644 index 5d88e0db23ae..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h +++ /dev/null @@ -1,837 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: gio.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 0 - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 32; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 4 -#define REG_WR_ADDR_gio_rw_pa_dout 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 32; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_pa_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte0_dout; -#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 -#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 - -/* Register rw_pa_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte0_oe; -#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 -#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 - -/* Register rw_pa_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte1_dout; -#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 -#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 - -/* Register rw_pa_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte1_oe; -#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 -#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 - -/* Register rw_pa_byte2_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte2_dout; -#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 -#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 - -/* Register rw_pa_byte2_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte2_oe; -#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 -#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 - -/* Register rw_pa_byte3_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte3_dout; -#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 -#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 - -/* Register rw_pa_byte3_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte3_oe; -#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 -#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 44 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 32; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 48 -#define REG_WR_ADDR_gio_rw_pb_dout 48 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 32; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 52 -#define REG_WR_ADDR_gio_rw_pb_oe 52 - -/* Register rw_pb_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte0_dout; -#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 -#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 - -/* Register rw_pb_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte0_oe; -#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 -#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 - -/* Register rw_pb_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte1_dout; -#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 -#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 - -/* Register rw_pb_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte1_oe; -#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 -#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 - -/* Register rw_pb_byte2_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte2_dout; -#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 -#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 - -/* Register rw_pb_byte2_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte2_oe; -#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 -#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 - -/* Register rw_pb_byte3_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte3_dout; -#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 -#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 - -/* Register rw_pb_byte3_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte3_oe; -#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 -#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 88 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 92 -#define REG_WR_ADDR_gio_rw_pc_dout 92 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 16; - unsigned int dummy1 : 16; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 96 -#define REG_WR_ADDR_gio_rw_pc_oe 96 - -/* Register rw_pc_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte0_dout; -#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 -#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 - -/* Register rw_pc_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte0_oe; -#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 -#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 - -/* Register rw_pc_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte1_dout; -#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 -#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 - -/* Register rw_pc_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte1_oe; -#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 -#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 116 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 3; - unsigned int intr1 : 3; - unsigned int intr2 : 3; - unsigned int intr3 : 3; - unsigned int intr4 : 3; - unsigned int intr5 : 3; - unsigned int intr6 : 3; - unsigned int intr7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 120 -#define REG_WR_ADDR_gio_rw_intr_cfg 120 - -/* Register rw_intr_pins, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 4; - unsigned int intr1 : 4; - unsigned int intr2 : 4; - unsigned int intr3 : 4; - unsigned int intr4 : 4; - unsigned int intr5 : 4; - unsigned int intr6 : 4; - unsigned int intr7 : 4; -} reg_gio_rw_intr_pins; -#define REG_RD_ADDR_gio_rw_intr_pins 124 -#define REG_WR_ADDR_gio_rw_intr_pins 124 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 128 -#define REG_WR_ADDR_gio_rw_intr_mask 128 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 132 -#define REG_WR_ADDR_gio_rw_ack_intr 132 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 136 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 140 - -/* Register rw_i2c0_start, scope gio, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_gio_rw_i2c0_start; -#define REG_RD_ADDR_gio_rw_i2c0_start 144 -#define REG_WR_ADDR_gio_rw_i2c0_start 144 - -/* Register rw_i2c0_cfg, scope gio, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int bit_order : 1; - unsigned int scl_io : 1; - unsigned int scl_inv : 1; - unsigned int sda_io : 1; - unsigned int sda_idle : 1; - unsigned int dummy1 : 26; -} reg_gio_rw_i2c0_cfg; -#define REG_RD_ADDR_gio_rw_i2c0_cfg 148 -#define REG_WR_ADDR_gio_rw_i2c0_cfg 148 - -/* Register rw_i2c0_ctrl, scope gio, type rw */ -typedef struct { - unsigned int trf_bits : 6; - unsigned int switch_dir : 6; - unsigned int extra_start : 3; - unsigned int early_end : 1; - unsigned int start_stop : 1; - unsigned int ack_dir0 : 1; - unsigned int ack_dir1 : 1; - unsigned int ack_dir2 : 1; - unsigned int ack_dir3 : 1; - unsigned int ack_dir4 : 1; - unsigned int ack_dir5 : 1; - unsigned int ack_bit : 1; - unsigned int start_bit : 1; - unsigned int freq : 2; - unsigned int dummy1 : 5; -} reg_gio_rw_i2c0_ctrl; -#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 -#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 - -/* Register rw_i2c0_data, scope gio, type rw */ -typedef struct { - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int data2 : 8; - unsigned int data3 : 8; -} reg_gio_rw_i2c0_data; -#define REG_RD_ADDR_gio_rw_i2c0_data 156 -#define REG_WR_ADDR_gio_rw_i2c0_data 156 - -/* Register rw_i2c0_data2, scope gio, type rw */ -typedef struct { - unsigned int data4 : 8; - unsigned int data5 : 8; - unsigned int start_val : 6; - unsigned int ack_val : 6; - unsigned int dummy1 : 4; -} reg_gio_rw_i2c0_data2; -#define REG_RD_ADDR_gio_rw_i2c0_data2 160 -#define REG_WR_ADDR_gio_rw_i2c0_data2 160 - -/* Register rw_i2c1_start, scope gio, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_gio_rw_i2c1_start; -#define REG_RD_ADDR_gio_rw_i2c1_start 164 -#define REG_WR_ADDR_gio_rw_i2c1_start 164 - -/* Register rw_i2c1_cfg, scope gio, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int bit_order : 1; - unsigned int scl_io : 1; - unsigned int scl_inv : 1; - unsigned int sda0_io : 1; - unsigned int sda0_idle : 1; - unsigned int sda1_io : 1; - unsigned int sda1_idle : 1; - unsigned int sda2_io : 1; - unsigned int sda2_idle : 1; - unsigned int sda3_io : 1; - unsigned int sda3_idle : 1; - unsigned int sda_sel : 2; - unsigned int sen_idle : 1; - unsigned int sen_inv : 1; - unsigned int sen_sel : 2; - unsigned int dummy1 : 14; -} reg_gio_rw_i2c1_cfg; -#define REG_RD_ADDR_gio_rw_i2c1_cfg 168 -#define REG_WR_ADDR_gio_rw_i2c1_cfg 168 - -/* Register rw_i2c1_ctrl, scope gio, type rw */ -typedef struct { - unsigned int trf_bits : 6; - unsigned int switch_dir : 6; - unsigned int extra_start : 3; - unsigned int early_end : 1; - unsigned int start_stop : 1; - unsigned int ack_dir0 : 1; - unsigned int ack_dir1 : 1; - unsigned int ack_dir2 : 1; - unsigned int ack_dir3 : 1; - unsigned int ack_dir4 : 1; - unsigned int ack_dir5 : 1; - unsigned int ack_bit : 1; - unsigned int start_bit : 1; - unsigned int freq : 2; - unsigned int dummy1 : 5; -} reg_gio_rw_i2c1_ctrl; -#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 -#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 - -/* Register rw_i2c1_data, scope gio, type rw */ -typedef struct { - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int data2 : 8; - unsigned int data3 : 8; -} reg_gio_rw_i2c1_data; -#define REG_RD_ADDR_gio_rw_i2c1_data 176 -#define REG_WR_ADDR_gio_rw_i2c1_data 176 - -/* Register rw_i2c1_data2, scope gio, type rw */ -typedef struct { - unsigned int data4 : 8; - unsigned int data5 : 8; - unsigned int start_val : 6; - unsigned int ack_val : 6; - unsigned int dummy1 : 4; -} reg_gio_rw_i2c1_data2; -#define REG_RD_ADDR_gio_rw_i2c1_data2 180 -#define REG_WR_ADDR_gio_rw_i2c1_data2 180 - -/* Register r_ppwm_stat, scope gio, type r */ -typedef struct { - unsigned int freq : 2; - unsigned int dummy1 : 30; -} reg_gio_r_ppwm_stat; -#define REG_RD_ADDR_gio_r_ppwm_stat 184 - -/* Register rw_ppwm_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_ppwm_data; -#define REG_RD_ADDR_gio_rw_ppwm_data 188 -#define REG_WR_ADDR_gio_rw_ppwm_data 188 - -/* Register rw_pwm0_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm0_ctrl; -#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 -#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 - -/* Register rw_pwm0_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm0_var; -#define REG_RD_ADDR_gio_rw_pwm0_var 196 -#define REG_WR_ADDR_gio_rw_pwm0_var 196 - -/* Register rw_pwm0_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm0_data; -#define REG_RD_ADDR_gio_rw_pwm0_data 200 -#define REG_WR_ADDR_gio_rw_pwm0_data 200 - -/* Register rw_pwm1_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm1_ctrl; -#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 -#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 - -/* Register rw_pwm1_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm1_var; -#define REG_RD_ADDR_gio_rw_pwm1_var 208 -#define REG_WR_ADDR_gio_rw_pwm1_var 208 - -/* Register rw_pwm1_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm1_data; -#define REG_RD_ADDR_gio_rw_pwm1_data 212 -#define REG_WR_ADDR_gio_rw_pwm1_data 212 - -/* Register rw_pwm2_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm2_ctrl; -#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 -#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 - -/* Register rw_pwm2_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm2_var; -#define REG_RD_ADDR_gio_rw_pwm2_var 220 -#define REG_WR_ADDR_gio_rw_pwm2_var 220 - -/* Register rw_pwm2_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm2_data; -#define REG_RD_ADDR_gio_rw_pwm2_data 224 -#define REG_WR_ADDR_gio_rw_pwm2_data 224 - -/* Register rw_pwm_in_cfg, scope gio, type rw */ -typedef struct { - unsigned int pin : 3; - unsigned int dummy1 : 29; -} reg_gio_rw_pwm_in_cfg; -#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 -#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 - -/* Register r_pwm_in_lo, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_lo; -#define REG_RD_ADDR_gio_r_pwm_in_lo 232 - -/* Register r_pwm_in_hi, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_hi; -#define REG_RD_ADDR_gio_r_pwm_in_hi 236 - -/* Register r_pwm_in_cnt, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_cnt; -#define REG_RD_ADDR_gio_r_pwm_in_cnt 240 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_f100k = 0x00000000, - regk_gio_f1562 = 0x00000000, - regk_gio_f195 = 0x00000003, - regk_gio_f1m = 0x00000002, - regk_gio_f390 = 0x00000002, - regk_gio_f400k = 0x00000001, - regk_gio_f5m = 0x00000003, - regk_gio_f781 = 0x00000001, - regk_gio_hi = 0x00000001, - regk_gio_in = 0x00000000, - regk_gio_intr_pa0 = 0x00000000, - regk_gio_intr_pa1 = 0x00000000, - regk_gio_intr_pa10 = 0x00000001, - regk_gio_intr_pa11 = 0x00000001, - regk_gio_intr_pa12 = 0x00000001, - regk_gio_intr_pa13 = 0x00000001, - regk_gio_intr_pa14 = 0x00000001, - regk_gio_intr_pa15 = 0x00000001, - regk_gio_intr_pa16 = 0x00000002, - regk_gio_intr_pa17 = 0x00000002, - regk_gio_intr_pa18 = 0x00000002, - regk_gio_intr_pa19 = 0x00000002, - regk_gio_intr_pa2 = 0x00000000, - regk_gio_intr_pa20 = 0x00000002, - regk_gio_intr_pa21 = 0x00000002, - regk_gio_intr_pa22 = 0x00000002, - regk_gio_intr_pa23 = 0x00000002, - regk_gio_intr_pa24 = 0x00000003, - regk_gio_intr_pa25 = 0x00000003, - regk_gio_intr_pa26 = 0x00000003, - regk_gio_intr_pa27 = 0x00000003, - regk_gio_intr_pa28 = 0x00000003, - regk_gio_intr_pa29 = 0x00000003, - regk_gio_intr_pa3 = 0x00000000, - regk_gio_intr_pa30 = 0x00000003, - regk_gio_intr_pa31 = 0x00000003, - regk_gio_intr_pa4 = 0x00000000, - regk_gio_intr_pa5 = 0x00000000, - regk_gio_intr_pa6 = 0x00000000, - regk_gio_intr_pa7 = 0x00000000, - regk_gio_intr_pa8 = 0x00000001, - regk_gio_intr_pa9 = 0x00000001, - regk_gio_intr_pb0 = 0x00000004, - regk_gio_intr_pb1 = 0x00000004, - regk_gio_intr_pb10 = 0x00000005, - regk_gio_intr_pb11 = 0x00000005, - regk_gio_intr_pb12 = 0x00000005, - regk_gio_intr_pb13 = 0x00000005, - regk_gio_intr_pb14 = 0x00000005, - regk_gio_intr_pb15 = 0x00000005, - regk_gio_intr_pb16 = 0x00000006, - regk_gio_intr_pb17 = 0x00000006, - regk_gio_intr_pb18 = 0x00000006, - regk_gio_intr_pb19 = 0x00000006, - regk_gio_intr_pb2 = 0x00000004, - regk_gio_intr_pb20 = 0x00000006, - regk_gio_intr_pb21 = 0x00000006, - regk_gio_intr_pb22 = 0x00000006, - regk_gio_intr_pb23 = 0x00000006, - regk_gio_intr_pb24 = 0x00000007, - regk_gio_intr_pb25 = 0x00000007, - regk_gio_intr_pb26 = 0x00000007, - regk_gio_intr_pb27 = 0x00000007, - regk_gio_intr_pb28 = 0x00000007, - regk_gio_intr_pb29 = 0x00000007, - regk_gio_intr_pb3 = 0x00000004, - regk_gio_intr_pb30 = 0x00000007, - regk_gio_intr_pb31 = 0x00000007, - regk_gio_intr_pb4 = 0x00000004, - regk_gio_intr_pb5 = 0x00000004, - regk_gio_intr_pb6 = 0x00000004, - regk_gio_intr_pb7 = 0x00000004, - regk_gio_intr_pb8 = 0x00000005, - regk_gio_intr_pb9 = 0x00000005, - regk_gio_intr_pc0 = 0x00000008, - regk_gio_intr_pc1 = 0x00000008, - regk_gio_intr_pc10 = 0x00000009, - regk_gio_intr_pc11 = 0x00000009, - regk_gio_intr_pc12 = 0x00000009, - regk_gio_intr_pc13 = 0x00000009, - regk_gio_intr_pc14 = 0x00000009, - regk_gio_intr_pc15 = 0x00000009, - regk_gio_intr_pc2 = 0x00000008, - regk_gio_intr_pc3 = 0x00000008, - regk_gio_intr_pc4 = 0x00000008, - regk_gio_intr_pc5 = 0x00000008, - regk_gio_intr_pc6 = 0x00000008, - regk_gio_intr_pc7 = 0x00000008, - regk_gio_intr_pc8 = 0x00000009, - regk_gio_intr_pc9 = 0x00000009, - regk_gio_intr_pd0 = 0x0000000c, - regk_gio_intr_pd1 = 0x0000000c, - regk_gio_intr_pd10 = 0x0000000d, - regk_gio_intr_pd11 = 0x0000000d, - regk_gio_intr_pd12 = 0x0000000d, - regk_gio_intr_pd13 = 0x0000000d, - regk_gio_intr_pd14 = 0x0000000d, - regk_gio_intr_pd15 = 0x0000000d, - regk_gio_intr_pd16 = 0x0000000e, - regk_gio_intr_pd17 = 0x0000000e, - regk_gio_intr_pd18 = 0x0000000e, - regk_gio_intr_pd19 = 0x0000000e, - regk_gio_intr_pd2 = 0x0000000c, - regk_gio_intr_pd20 = 0x0000000e, - regk_gio_intr_pd21 = 0x0000000e, - regk_gio_intr_pd22 = 0x0000000e, - regk_gio_intr_pd23 = 0x0000000e, - regk_gio_intr_pd24 = 0x0000000f, - regk_gio_intr_pd25 = 0x0000000f, - regk_gio_intr_pd26 = 0x0000000f, - regk_gio_intr_pd27 = 0x0000000f, - regk_gio_intr_pd28 = 0x0000000f, - regk_gio_intr_pd29 = 0x0000000f, - regk_gio_intr_pd3 = 0x0000000c, - regk_gio_intr_pd30 = 0x0000000f, - regk_gio_intr_pd31 = 0x0000000f, - regk_gio_intr_pd4 = 0x0000000c, - regk_gio_intr_pd5 = 0x0000000c, - regk_gio_intr_pd6 = 0x0000000c, - regk_gio_intr_pd7 = 0x0000000c, - regk_gio_intr_pd8 = 0x0000000d, - regk_gio_intr_pd9 = 0x0000000d, - regk_gio_lo = 0x00000002, - regk_gio_lsb = 0x00000000, - regk_gio_msb = 0x00000001, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_no_switch = 0x0000003f, - regk_gio_none = 0x00000007, - regk_gio_off = 0x00000000, - regk_gio_opendrain = 0x00000000, - regk_gio_out = 0x00000001, - regk_gio_posedge = 0x00000005, - regk_gio_pwm_hfp = 0x00000002, - regk_gio_pwm_pa0 = 0x00000001, - regk_gio_pwm_pa19 = 0x00000004, - regk_gio_pwm_pa6 = 0x00000002, - regk_gio_pwm_pa7 = 0x00000003, - regk_gio_pwm_pb26 = 0x00000005, - regk_gio_pwm_pd23 = 0x00000006, - regk_gio_pwm_pd31 = 0x00000007, - regk_gio_pwm_std = 0x00000001, - regk_gio_pwm_var = 0x00000003, - regk_gio_rw_i2c0_cfg_default = 0x00000020, - regk_gio_rw_i2c0_ctrl_default = 0x00010000, - regk_gio_rw_i2c0_start_default = 0x00000000, - regk_gio_rw_i2c1_cfg_default = 0x00000aa0, - regk_gio_rw_i2c1_ctrl_default = 0x00010000, - regk_gio_rw_i2c1_start_default = 0x00000000, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_ppwm_data_default = 0x00000000, - regk_gio_rw_pwm0_ctrl_default = 0x00000000, - regk_gio_rw_pwm1_ctrl_default = 0x00000000, - regk_gio_rw_pwm2_ctrl_default = 0x00000000, - regk_gio_rw_pwm_in_cfg_default = 0x00000000, - regk_gio_sda0 = 0x00000000, - regk_gio_sda1 = 0x00000001, - regk_gio_sda2 = 0x00000002, - regk_gio_sda3 = 0x00000003, - regk_gio_sen = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h deleted file mode 100644 index bea699aa480e..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr - from intr_vect.r */ - -#ifndef _INTR_VECT_R -#define _INTR_VECT_R -#define TIMER0_INTR_VECT 0x31 -#define TIMER1_INTR_VECT 0x32 -#define DMA0_INTR_VECT 0x33 -#define DMA1_INTR_VECT 0x34 -#define DMA2_INTR_VECT 0x35 -#define DMA3_INTR_VECT 0x36 -#define DMA4_INTR_VECT 0x37 -#define DMA5_INTR_VECT 0x38 -#define DMA6_INTR_VECT 0x39 -#define DMA7_INTR_VECT 0x3a -#define DMA9_INTR_VECT 0x3b -#define DMA11_INTR_VECT 0x3c -#define GIO_INTR_VECT 0x3d -#define IOP0_INTR_VECT 0x3e -#define IOP1_INTR_VECT 0x3f -#define SER0_INTR_VECT 0x40 -#define SER1_INTR_VECT 0x41 -#define SER2_INTR_VECT 0x42 -#define SER3_INTR_VECT 0x43 -#define SER4_INTR_VECT 0x44 -#define SSER_INTR_VECT 0x45 -#define STRDMA0_INTR_VECT 0x46 -#define STRDMA1_INTR_VECT 0x47 -#define STRDMA2_INTR_VECT 0x48 -#define STRDMA3_INTR_VECT 0x49 -#define STRDMA5_INTR_VECT 0x4a -#define VIN_INTR_VECT 0x4b -#define VOUT_INTR_VECT 0x4c -#define JPEG_INTR_VECT 0x4d -#define H264_INTR_VECT 0x4e -#define HISTO_INTR_VECT 0x4f -#define CCD_INTR_VECT 0x50 -#define ETH_INTR_VECT 0x51 -#define MEMARB_BAR_INTR_VECT 0x52 -#define MEMARB_FOO_INTR_VECT 0x53 -#define PIO_INTR_VECT 0x54 -#define SCLR_INTR_VECT 0x55 -#define SCLR_FIFO_INTR_VECT 0x56 -#define IPI_INTR_VECT 0x57 -#define NBR_INTR_VECT 0x58 -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h deleted file mode 100644 index b820f6347c74..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,341 +0,0 @@ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: intr_vect.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - - -#define STRIDE_intr_vect_rw_mask 4 -/* Register rw_mask0, scope intr_vect, type rw */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_rw_mask0; -#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 -#define REG_RD_ADDR_intr_vect_rw_mask0 0 -#define REG_WR_ADDR_intr_vect_rw_mask0 0 - -#define STRIDE_intr_vect_r_vect 4 -/* Register r_vect0, scope intr_vect, type r */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_r_vect0; -#define reg_intr_vect_r_vect reg_intr_vect_r_vect0 -#define REG_RD_ADDR_intr_vect_r_vect 8 -#define REG_RD_ADDR_intr_vect_r_vect0 8 - -#define STRIDE_intr_vect_r_masked_vect 4 -/* Register r_masked_vect0, scope intr_vect, type r */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_r_masked_vect0; -#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 -#define REG_RD_ADDR_intr_vect_r_masked_vect0 16 -#define REG_RD_ADDR_intr_vect_r_masked_vect 16 - -#define STRIDE_intr_vect_rw_xmask 4 -/* Register rw_xmask0, scope intr_vect, type rw */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_rw_xmask0; -#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 -#define REG_RD_ADDR_intr_vect_rw_xmask0 24 -#define REG_WR_ADDR_intr_vect_rw_xmask0 24 -#define REG_RD_ADDR_intr_vect_rw_xmask 24 -#define REG_WR_ADDR_intr_vect_rw_xmask 24 - -/* Register rw_mask1, scope intr_vect, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_rw_mask1; -#define REG_RD_ADDR_intr_vect_rw_mask1 4 -#define REG_WR_ADDR_intr_vect_rw_mask1 4 - -/* Register r_vect1, scope intr_vect, type r */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_r_vect1; -#define REG_RD_ADDR_intr_vect_r_vect1 12 - -/* Register r_masked_vect1, scope intr_vect, type r */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_r_masked_vect1; -#define REG_RD_ADDR_intr_vect_r_masked_vect1 20 - -/* Register rw_xmask1, scope intr_vect, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_rw_xmask1; -#define REG_RD_ADDR_intr_vect_rw_xmask1 28 -#define REG_WR_ADDR_intr_vect_rw_xmask1 28 - -/* Register rw_xmask_ctrl, scope intr_vect, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_rw_xmask_ctrl; -#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 -#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int watchdog0 : 1; - unsigned int watchdog1 : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 64 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 68 - - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 72 -#define REG_WR_ADDR_intr_vect_rw_ipi 72 - -/* Constants */ -enum { - regk_intr_vect_no = 0x00000000, - regk_intr_vect_rw_mask0_default = 0x00000000, - regk_intr_vect_rw_mask1_default = 0x00000000, - regk_intr_vect_rw_xmask0_default = 0x00000000, - regk_intr_vect_rw_xmask1_default = 0x00000000, - regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, - regk_intr_vect_yes = 0x00000001 -}; -#endif /* __intr_vect_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index d75a74e90458..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in_extra 64 -#define iop_fifo_out_extra 128 -#define iop_trigger_grp0 192 -#define iop_trigger_grp1 256 -#define iop_trigger_grp2 320 -#define iop_trigger_grp3 384 -#define iop_trigger_grp4 448 -#define iop_trigger_grp5 512 -#define iop_trigger_grp6 576 -#define iop_trigger_grp7 640 -#define iop_crc_par 768 -#define iop_dmc_in 896 -#define iop_dmc_out 1024 -#define iop_fifo_in 1152 -#define iop_fifo_out 1280 -#define iop_scrc_in 1408 -#define iop_scrc_out 1536 -#define iop_timer_grp0 1664 -#define iop_timer_grp1 1792 -#define iop_sap_in 2048 -#define iop_sap_out 2304 -#define iop_spu 2560 -#define iop_sw_cfg 2816 -#define iop_sw_cpu 3072 -#define iop_sw_mpu 3328 -#define iop_sw_spu 3584 -#define iop_mpu 4096 diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index 7f90b5a0460d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 -#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 -#define reg_iop_sap_in_rw_bus_byte___delay___width 2 -#define reg_iop_sap_in_rw_bus_byte_offset 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 2 -#define reg_iop_sap_in_rw_gio___logic___lsb 9 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio0 0x00000000 -#define regk_iop_sap_in_gio12 0x00000003 -#define regk_iop_sap_in_gio16 0x00000004 -#define regk_iop_sap_in_gio20 0x00000005 -#define regk_iop_sap_in_gio24 0x00000006 -#define regk_iop_sap_in_gio28 0x00000007 -#define regk_iop_sap_in_gio4 0x00000001 -#define regk_iop_sap_in_gio8 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_one 0x00000001 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 -#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 -#define regk_iop_sap_in_rw_gio_default 0x00000000 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 -#define regk_iop_sap_in_tmr_clk200 0x00000001 -#define regk_iop_sap_in_two 0x00000002 -#define regk_iop_sap_in_two_clk200 0x00000000 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 399bd656406b..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 -#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 -#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 -#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 -#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 -#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 -#define reg_iop_sap_out_rw_bus_offset 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 -#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 -#define reg_iop_sap_out_rw_gio___out_delay___width 1 -#define reg_iop_sap_out_rw_gio___out_delay___bit 7 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 -#define reg_iop_sap_out_rw_gio___out_logic___width 2 -#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 -#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_delay___width 1 -#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 -#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 -#define reg_iop_sap_out_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_out_always 0x00000001 -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000004 -#define regk_iop_sap_out_clk200 0x00000000 -#define regk_iop_sap_out_ext 0x00000002 -#define regk_iop_sap_out_gated 0x00000003 -#define regk_iop_sap_out_gio0 0x00000000 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio16 0x00000002 -#define regk_iop_sap_out_gio17 0x00000002 -#define regk_iop_sap_out_gio24 0x00000003 -#define regk_iop_sap_out_gio25 0x00000003 -#define regk_iop_sap_out_gio8 0x00000001 -#define regk_iop_sap_out_gio9 0x00000001 -#define regk_iop_sap_out_gio_out10 0x00000005 -#define regk_iop_sap_out_gio_out18 0x00000006 -#define regk_iop_sap_out_gio_out2 0x00000004 -#define regk_iop_sap_out_gio_out26 0x00000007 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_one 0x00000001 -#define regk_iop_sap_out_rw_bus_default 0x00000000 -#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu_gio6 0x00000002 -#define regk_iop_sap_out_spu_gio7 0x00000003 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 -#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 -#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 -#define regk_iop_sap_out_tmr200 0x00000001 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 3b3949b51a66..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,739 +0,0 @@ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 -#define reg_iop_sw_cfg_rw_spu_owner_offset 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus_mask_offset 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 -#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus 0x00000000 -#define regk_iop_sw_cfg_bus_rot16 0x00000002 -#define regk_iop_sw_cfg_bus_rot24 0x00000003 -#define regk_iop_sw_cfg_bus_rot8 0x00000001 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_gated_clk0 0x0000000e -#define regk_iop_sw_cfg_gated_clk1 0x0000000f -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_pdp_out 0x00000001 -#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 -#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out 0x00000004 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 -#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 -#define regk_iop_sw_cfg_spu_g0 0x00000007 -#define regk_iop_sw_cfg_spu_g1 0x00000007 -#define regk_iop_sw_cfg_spu_g2 0x00000007 -#define regk_iop_sw_cfg_spu_g3 0x00000007 -#define regk_iop_sw_cfg_spu_g4 0x00000007 -#define regk_iop_sw_cfg_spu_g5 0x00000007 -#define regk_iop_sw_cfg_spu_g6 0x00000007 -#define regk_iop_sw_cfg_spu_g7 0x00000007 -#define regk_iop_sw_cfg_spu_gio0 0x00000000 -#define regk_iop_sw_cfg_spu_gio1 0x00000001 -#define regk_iop_sw_cfg_spu_gio5 0x00000005 -#define regk_iop_sw_cfg_spu_gio6 0x00000006 -#define regk_iop_sw_cfg_spu_gio7 0x00000007 -#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu_gioout10 0x00000007 -#define regk_iop_sw_cfg_spu_gioout11 0x00000007 -#define regk_iop_sw_cfg_spu_gioout12 0x00000007 -#define regk_iop_sw_cfg_spu_gioout13 0x00000007 -#define regk_iop_sw_cfg_spu_gioout14 0x00000007 -#define regk_iop_sw_cfg_spu_gioout15 0x00000007 -#define regk_iop_sw_cfg_spu_gioout16 0x00000007 -#define regk_iop_sw_cfg_spu_gioout17 0x00000007 -#define regk_iop_sw_cfg_spu_gioout18 0x00000007 -#define regk_iop_sw_cfg_spu_gioout19 0x00000007 -#define regk_iop_sw_cfg_spu_gioout2 0x00000001 -#define regk_iop_sw_cfg_spu_gioout20 0x00000007 -#define regk_iop_sw_cfg_spu_gioout21 0x00000007 -#define regk_iop_sw_cfg_spu_gioout22 0x00000007 -#define regk_iop_sw_cfg_spu_gioout23 0x00000007 -#define regk_iop_sw_cfg_spu_gioout24 0x00000007 -#define regk_iop_sw_cfg_spu_gioout25 0x00000007 -#define regk_iop_sw_cfg_spu_gioout26 0x00000007 -#define regk_iop_sw_cfg_spu_gioout27 0x00000007 -#define regk_iop_sw_cfg_spu_gioout28 0x00000007 -#define regk_iop_sw_cfg_spu_gioout29 0x00000007 -#define regk_iop_sw_cfg_spu_gioout3 0x00000001 -#define regk_iop_sw_cfg_spu_gioout30 0x00000007 -#define regk_iop_sw_cfg_spu_gioout31 0x00000007 -#define regk_iop_sw_cfg_spu_gioout4 0x00000002 -#define regk_iop_sw_cfg_spu_gioout5 0x00000002 -#define regk_iop_sw_cfg_spu_gioout6 0x00000003 -#define regk_iop_sw_cfg_spu_gioout7 0x00000003 -#define regk_iop_sw_cfg_spu_gioout8 0x00000007 -#define regk_iop_sw_cfg_spu_gioout9 0x00000007 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000001 -#define regk_iop_sw_cfg_trig2_1 0x00000001 -#define regk_iop_sw_cfg_trig2_2 0x00000001 -#define regk_iop_sw_cfg_trig2_3 0x00000001 -#define regk_iop_sw_cfg_trig3_0 0x00000001 -#define regk_iop_sw_cfg_trig3_1 0x00000001 -#define regk_iop_sw_cfg_trig3_2 0x00000001 -#define regk_iop_sw_cfg_trig3_3 0x00000001 -#define regk_iop_sw_cfg_trig4_0 0x00000002 -#define regk_iop_sw_cfg_trig4_1 0x00000002 -#define regk_iop_sw_cfg_trig4_2 0x00000002 -#define regk_iop_sw_cfg_trig4_3 0x00000002 -#define regk_iop_sw_cfg_trig5_0 0x00000002 -#define regk_iop_sw_cfg_trig5_1 0x00000002 -#define regk_iop_sw_cfg_trig5_2 0x00000002 -#define regk_iop_sw_cfg_trig5_3 0x00000002 -#define regk_iop_sw_cfg_trig6_0 0x00000003 -#define regk_iop_sw_cfg_trig6_1 0x00000003 -#define regk_iop_sw_cfg_trig6_2 0x00000003 -#define regk_iop_sw_cfg_trig6_3 0x00000003 -#define regk_iop_sw_cfg_trig7_0 0x00000003 -#define regk_iop_sw_cfg_trig7_1 0x00000003 -#define regk_iop_sw_cfg_trig7_2 0x00000003 -#define regk_iop_sw_cfg_trig7_3 0x00000003 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index 3f4fe1b31815..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,950 +0,0 @@ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mpu_trace_offset 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 104 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index ffcc83b22d21..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1086 +0,0 @@ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0_offset 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1_offset 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2_offset 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3_offset 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu 0x00000002 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 67a745338087..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,523 +0,0 @@ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_trace_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_spu_r_mc_stat_offset 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus_in_offset 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 -#define reg_iop_sw_spu_r_hw_intr_offset 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr_offset 132 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index 4ad671202af0..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v2_0 0x00000002 -#endif /* __iop_version_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h deleted file mode 100644 index af3196c60a46..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in_extra (regi_iop + 64) -#define regi_iop_fifo_out_extra (regi_iop + 128) -#define regi_iop_trigger_grp0 (regi_iop + 192) -#define regi_iop_trigger_grp1 (regi_iop + 256) -#define regi_iop_trigger_grp2 (regi_iop + 320) -#define regi_iop_trigger_grp3 (regi_iop + 384) -#define regi_iop_trigger_grp4 (regi_iop + 448) -#define regi_iop_trigger_grp5 (regi_iop + 512) -#define regi_iop_trigger_grp6 (regi_iop + 576) -#define regi_iop_trigger_grp7 (regi_iop + 640) -#define regi_iop_crc_par (regi_iop + 768) -#define regi_iop_dmc_in (regi_iop + 896) -#define regi_iop_dmc_out (regi_iop + 1024) -#define regi_iop_fifo_in (regi_iop + 1152) -#define regi_iop_fifo_out (regi_iop + 1280) -#define regi_iop_scrc_in (regi_iop + 1408) -#define regi_iop_scrc_out (regi_iop + 1536) -#define regi_iop_timer_grp0 (regi_iop + 1664) -#define regi_iop_timer_grp1 (regi_iop + 1792) -#define regi_iop_sap_in (regi_iop + 2048) -#define regi_iop_sap_out (regi_iop + 2304) -#define regi_iop_spu (regi_iop + 2560) -#define regi_iop_sw_cfg (regi_iop + 2816) -#define regi_iop_sw_cpu (regi_iop + 3072) -#define regi_iop_sw_mpu (regi_iop + 3328) -#define regi_iop_sw_spu (regi_iop + 3584) -#define regi_iop_mpu (regi_iop + 4096) diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 51dde016c03a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,141 +0,0 @@ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int dummy1 : 23; -} reg_iop_sap_in_rw_bus_byte; -#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int logic : 2; - unsigned int dummy1 : 21; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 16 -#define REG_WR_ADDR_iop_sap_in_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio0 = 0x00000000, - regk_iop_sap_in_gio12 = 0x00000003, - regk_iop_sap_in_gio16 = 0x00000004, - regk_iop_sap_in_gio20 = 0x00000005, - regk_iop_sap_in_gio24 = 0x00000006, - regk_iop_sap_in_gio28 = 0x00000007, - regk_iop_sap_in_gio4 = 0x00000001, - regk_iop_sap_in_gio8 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_one = 0x00000001, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus_byte_default = 0x00000000, - regk_iop_sap_in_rw_bus_byte_size = 0x00000004, - regk_iop_sap_in_rw_gio_default = 0x00000000, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, - regk_iop_sap_in_tmr_clk200 = 0x00000001, - regk_iop_sap_in_two = 0x00000002, - regk_iop_sap_in_two_clk200 = 0x00000000 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 5af88baa2ac1..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,231 +0,0 @@ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int dummy1 : 18; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_bus; -#define REG_RD_ADDR_iop_sap_out_rw_bus 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte0_logic : 2; - unsigned int byte0_logic_src : 2; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte1_logic : 2; - unsigned int byte1_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte2_logic : 2; - unsigned int byte2_logic_src : 2; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int byte3_logic : 2; - unsigned int byte3_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 2; - unsigned int out_gated_clk : 1; - unsigned int out_clk_inv : 1; - unsigned int out_delay : 1; - unsigned int out_logic : 2; - unsigned int out_logic_src : 2; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 2; - unsigned int oe_gated_clk : 1; - unsigned int oe_clk_inv : 1; - unsigned int oe_delay : 1; - unsigned int oe_logic : 2; - unsigned int oe_logic_src : 2; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 16 -#define REG_WR_ADDR_iop_sap_out_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_out_always = 0x00000001, - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000004, - regk_iop_sap_out_clk200 = 0x00000000, - regk_iop_sap_out_ext = 0x00000002, - regk_iop_sap_out_gated = 0x00000003, - regk_iop_sap_out_gio0 = 0x00000000, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio16 = 0x00000002, - regk_iop_sap_out_gio17 = 0x00000002, - regk_iop_sap_out_gio24 = 0x00000003, - regk_iop_sap_out_gio25 = 0x00000003, - regk_iop_sap_out_gio8 = 0x00000001, - regk_iop_sap_out_gio9 = 0x00000001, - regk_iop_sap_out_gio_out10 = 0x00000005, - regk_iop_sap_out_gio_out18 = 0x00000006, - regk_iop_sap_out_gio_out2 = 0x00000004, - regk_iop_sap_out_gio_out26 = 0x00000007, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_one = 0x00000001, - regk_iop_sap_out_rw_bus_default = 0x00000000, - regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu_gio6 = 0x00000002, - regk_iop_sap_out_spu_gio7 = 0x00000003, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, - regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, - regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, - regk_iop_sap_out_tmr200 = 0x00000001, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index 98ac95275a1c..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,725 +0,0 @@ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 1; - unsigned int dummy1 : 31; -} reg_iop_sw_cfg_rw_spu_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_byte0 : 2; - unsigned int bus_byte1 : 2; - unsigned int bus_byte2 : 2; - unsigned int bus_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_lo : 2; - unsigned int bus_hi : 2; - unsigned int bus_lo_oe : 2; - unsigned int bus_hi_oe : 2; - unsigned int dummy1 : 24; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 3; - unsigned int gio0_oe : 1; - unsigned int gio1 : 3; - unsigned int gio1_oe : 1; - unsigned int gio2 : 3; - unsigned int gio2_oe : 1; - unsigned int gio3 : 3; - unsigned int gio3_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 3; - unsigned int gio4_oe : 1; - unsigned int gio5 : 3; - unsigned int gio5_oe : 1; - unsigned int gio6 : 3; - unsigned int gio6_oe : 1; - unsigned int gio7 : 3; - unsigned int gio7_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 3; - unsigned int gio8_oe : 1; - unsigned int gio9 : 3; - unsigned int gio9_oe : 1; - unsigned int gio10 : 3; - unsigned int gio10_oe : 1; - unsigned int gio11 : 3; - unsigned int gio11_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 3; - unsigned int gio12_oe : 1; - unsigned int gio13 : 3; - unsigned int gio13_oe : 1; - unsigned int gio14 : 3; - unsigned int gio14_oe : 1; - unsigned int gio15 : 3; - unsigned int gio15_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 3; - unsigned int gio16_oe : 1; - unsigned int gio17 : 3; - unsigned int gio17_oe : 1; - unsigned int gio18 : 3; - unsigned int gio18_oe : 1; - unsigned int gio19 : 3; - unsigned int gio19_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 3; - unsigned int gio20_oe : 1; - unsigned int gio21 : 3; - unsigned int gio21_oe : 1; - unsigned int gio22 : 3; - unsigned int gio22_oe : 1; - unsigned int gio23 : 3; - unsigned int gio23_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 3; - unsigned int gio24_oe : 1; - unsigned int gio25 : 3; - unsigned int gio25_oe : 1; - unsigned int gio26 : 3; - unsigned int gio26_oe : 1; - unsigned int gio27 : 3; - unsigned int gio27_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 3; - unsigned int gio28_oe : 1; - unsigned int gio29 : 3; - unsigned int gio29_oe : 1; - unsigned int gio30 : 3; - unsigned int gio30_oe : 1; - unsigned int gio31 : 3; - unsigned int gio31_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 1; - unsigned int bus1_in : 1; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int out_strb : 4; - unsigned int in_src : 2; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int dummy1 : 17; -} reg_iop_sw_cfg_rw_pdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out_strb : 3; - unsigned int sdp_in_data : 3; - unsigned int sdp_in_last : 2; - unsigned int sdp_in_strb : 3; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus = 0x00000000, - regk_iop_sw_cfg_bus_rot16 = 0x00000002, - regk_iop_sw_cfg_bus_rot24 = 0x00000003, - regk_iop_sw_cfg_bus_rot8 = 0x00000001, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_gated_clk0 = 0x0000000e, - regk_iop_sw_cfg_gated_clk1 = 0x0000000f, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_pdp_out = 0x00000001, - regk_iop_sw_cfg_pdp_out_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out_lo = 0x00000000, - regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out = 0x00000004, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, - regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, - regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, - regk_iop_sw_cfg_spu_g0 = 0x00000007, - regk_iop_sw_cfg_spu_g1 = 0x00000007, - regk_iop_sw_cfg_spu_g2 = 0x00000007, - regk_iop_sw_cfg_spu_g3 = 0x00000007, - regk_iop_sw_cfg_spu_g4 = 0x00000007, - regk_iop_sw_cfg_spu_g5 = 0x00000007, - regk_iop_sw_cfg_spu_g6 = 0x00000007, - regk_iop_sw_cfg_spu_g7 = 0x00000007, - regk_iop_sw_cfg_spu_gio0 = 0x00000000, - regk_iop_sw_cfg_spu_gio1 = 0x00000001, - regk_iop_sw_cfg_spu_gio5 = 0x00000005, - regk_iop_sw_cfg_spu_gio6 = 0x00000006, - regk_iop_sw_cfg_spu_gio7 = 0x00000007, - regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu_gioout10 = 0x00000007, - regk_iop_sw_cfg_spu_gioout11 = 0x00000007, - regk_iop_sw_cfg_spu_gioout12 = 0x00000007, - regk_iop_sw_cfg_spu_gioout13 = 0x00000007, - regk_iop_sw_cfg_spu_gioout14 = 0x00000007, - regk_iop_sw_cfg_spu_gioout15 = 0x00000007, - regk_iop_sw_cfg_spu_gioout16 = 0x00000007, - regk_iop_sw_cfg_spu_gioout17 = 0x00000007, - regk_iop_sw_cfg_spu_gioout18 = 0x00000007, - regk_iop_sw_cfg_spu_gioout19 = 0x00000007, - regk_iop_sw_cfg_spu_gioout2 = 0x00000001, - regk_iop_sw_cfg_spu_gioout20 = 0x00000007, - regk_iop_sw_cfg_spu_gioout21 = 0x00000007, - regk_iop_sw_cfg_spu_gioout22 = 0x00000007, - regk_iop_sw_cfg_spu_gioout23 = 0x00000007, - regk_iop_sw_cfg_spu_gioout24 = 0x00000007, - regk_iop_sw_cfg_spu_gioout25 = 0x00000007, - regk_iop_sw_cfg_spu_gioout26 = 0x00000007, - regk_iop_sw_cfg_spu_gioout27 = 0x00000007, - regk_iop_sw_cfg_spu_gioout28 = 0x00000007, - regk_iop_sw_cfg_spu_gioout29 = 0x00000007, - regk_iop_sw_cfg_spu_gioout3 = 0x00000001, - regk_iop_sw_cfg_spu_gioout30 = 0x00000007, - regk_iop_sw_cfg_spu_gioout31 = 0x00000007, - regk_iop_sw_cfg_spu_gioout4 = 0x00000002, - regk_iop_sw_cfg_spu_gioout5 = 0x00000002, - regk_iop_sw_cfg_spu_gioout6 = 0x00000003, - regk_iop_sw_cfg_spu_gioout7 = 0x00000003, - regk_iop_sw_cfg_spu_gioout8 = 0x00000007, - regk_iop_sw_cfg_spu_gioout9 = 0x00000007, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000001, - regk_iop_sw_cfg_trig2_1 = 0x00000001, - regk_iop_sw_cfg_trig2_2 = 0x00000001, - regk_iop_sw_cfg_trig2_3 = 0x00000001, - regk_iop_sw_cfg_trig3_0 = 0x00000001, - regk_iop_sw_cfg_trig3_1 = 0x00000001, - regk_iop_sw_cfg_trig3_2 = 0x00000001, - regk_iop_sw_cfg_trig3_3 = 0x00000001, - regk_iop_sw_cfg_trig4_0 = 0x00000002, - regk_iop_sw_cfg_trig4_1 = 0x00000002, - regk_iop_sw_cfg_trig4_2 = 0x00000002, - regk_iop_sw_cfg_trig4_3 = 0x00000002, - regk_iop_sw_cfg_trig5_0 = 0x00000002, - regk_iop_sw_cfg_trig5_1 = 0x00000002, - regk_iop_sw_cfg_trig5_2 = 0x00000002, - regk_iop_sw_cfg_trig5_3 = 0x00000002, - regk_iop_sw_cfg_trig6_0 = 0x00000003, - regk_iop_sw_cfg_trig6_1 = 0x00000003, - regk_iop_sw_cfg_trig6_2 = 0x00000003, - regk_iop_sw_cfg_trig6_3 = 0x00000003, - regk_iop_sw_cfg_trig7_0 = 0x00000003, - regk_iop_sw_cfg_trig7_1 = 0x00000003, - regk_iop_sw_cfg_trig7_2 = 0x00000003, - regk_iop_sw_cfg_trig7_3 = 0x00000003 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index a16f556370eb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,522 +0,0 @@ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index a2e4e1a33e57..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,648 +0,0 @@ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr1 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr2 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr3 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr5 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr6 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr7 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr9 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr10 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr11 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr13 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr14 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr15 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu = 0x00000002, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index c8560b865a1a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,441 +0,0 @@ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out : 1; - unsigned int fifo_out_extra : 1; - unsigned int fifo_in : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_out : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h deleted file mode 100644 index 20de425e652b..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v2_0 = 0x00000002 -}; -#endif /* __iop_version_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h deleted file mode 100644 index 243ac3c882cb..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __l2cache_defs_h -#define __l2cache_defs_h - -/* - * This file is autogenerated from - * file: l2cache.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope l2cache */ - -/* Register rw_cfg, scope l2cache, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_l2cache_rw_cfg; -#define REG_RD_ADDR_l2cache_rw_cfg 0 -#define REG_WR_ADDR_l2cache_rw_cfg 0 - -/* Register rw_ctrl, scope l2cache, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int cbase : 9; - unsigned int dummy2 : 4; - unsigned int csize : 10; - unsigned int dummy3 : 2; -} reg_l2cache_rw_ctrl; -#define REG_RD_ADDR_l2cache_rw_ctrl 4 -#define REG_WR_ADDR_l2cache_rw_ctrl 4 - -/* Register rw_idxop, scope l2cache, type rw */ -typedef struct { - unsigned int idx : 10; - unsigned int dummy1 : 14; - unsigned int way : 3; - unsigned int dummy2 : 2; - unsigned int cmd : 3; -} reg_l2cache_rw_idxop; -#define REG_RD_ADDR_l2cache_rw_idxop 8 -#define REG_WR_ADDR_l2cache_rw_idxop 8 - -/* Register rw_addrop_addr, scope l2cache, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_l2cache_rw_addrop_addr; -#define REG_RD_ADDR_l2cache_rw_addrop_addr 12 -#define REG_WR_ADDR_l2cache_rw_addrop_addr 12 - -/* Register rw_addrop_ctrl, scope l2cache, type rw */ -typedef struct { - unsigned int size : 16; - unsigned int dummy1 : 13; - unsigned int cmd : 3; -} reg_l2cache_rw_addrop_ctrl; -#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 -#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 - - -/* Constants */ -enum { - regk_l2cache_flush = 0x00000001, - regk_l2cache_no = 0x00000000, - regk_l2cache_rw_addrop_addr_default = 0x00000000, - regk_l2cache_rw_addrop_ctrl_default = 0x00000000, - regk_l2cache_rw_cfg_default = 0x00000000, - regk_l2cache_rw_ctrl_default = 0x00000000, - regk_l2cache_rw_idxop_default = 0x00000000, - regk_l2cache_yes = 0x00000001 -}; -#endif /* __l2cache_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h deleted file mode 100644 index c0e7628cbf7d..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h +++ /dev/null @@ -1,482 +0,0 @@ -#ifndef __marb_bar_defs_h -#define __marb_bar_defs_h - -/* - * This file is autogenerated from - * file: marb_bar.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bar */ - -#define STRIDE_marb_bar_rw_ddr2_slots 4 -/* Register rw_ddr2_slots, scope marb_bar, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_ddr2_slots; -#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 -#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 - -/* Register rw_h264_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_h264_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 -#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 - -/* Register rw_h264_wr_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_h264_wr_burst; -#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 -#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 - -/* Register rw_ccd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_ccd_burst; -#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 -#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 - -/* Register rw_vin_wr_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vin_wr_burst; -#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 -#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 - -/* Register rw_vin_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vin_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 -#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 - -/* Register rw_sclr_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_sclr_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 -#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 - -/* Register rw_vout_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vout_burst; -#define REG_RD_ADDR_marb_bar_rw_vout_burst 280 -#define REG_WR_ADDR_marb_bar_rw_vout_burst 280 - -/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_sclr_fifo_burst; -#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 -#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 - -/* Register rw_l2cache_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_l2cache_burst; -#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 -#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 - -/* Register rw_intr_mask, scope marb_bar, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_intr_mask; -#define REG_RD_ADDR_marb_bar_rw_intr_mask 292 -#define REG_WR_ADDR_marb_bar_rw_intr_mask 292 - -/* Register rw_ack_intr, scope marb_bar, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_ack_intr; -#define REG_RD_ADDR_marb_bar_rw_ack_intr 296 -#define REG_WR_ADDR_marb_bar_rw_ack_intr 296 - -/* Register r_intr, scope marb_bar, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_r_intr; -#define REG_RD_ADDR_marb_bar_r_intr 300 - -/* Register r_masked_intr, scope marb_bar, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_r_masked_intr; -#define REG_RD_ADDR_marb_bar_r_masked_intr 304 - -/* Register rw_stop_mask, scope marb_bar, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_rw_stop_mask; -#define REG_RD_ADDR_marb_bar_rw_stop_mask 308 -#define REG_WR_ADDR_marb_bar_rw_stop_mask 308 - -/* Register r_stopped, scope marb_bar, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_r_stopped; -#define REG_RD_ADDR_marb_bar_r_stopped 312 - -/* Register rw_no_snoop, scope marb_bar, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_rw_no_snoop; -#define REG_RD_ADDR_marb_bar_rw_no_snoop 576 -#define REG_WR_ADDR_marb_bar_rw_no_snoop 576 - - -/* Constants */ -enum { - regk_marb_bar_ccd = 0x00000002, - regk_marb_bar_h264_rd = 0x00000000, - regk_marb_bar_h264_wr = 0x00000001, - regk_marb_bar_l2cache = 0x00000008, - regk_marb_bar_no = 0x00000000, - regk_marb_bar_r_stopped_default = 0x00000000, - regk_marb_bar_rw_ccd_burst_default = 0x00000000, - regk_marb_bar_rw_ddr2_slots_default = 0x00000000, - regk_marb_bar_rw_ddr2_slots_size = 0x00000040, - regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, - regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, - regk_marb_bar_rw_intr_mask_default = 0x00000000, - regk_marb_bar_rw_l2cache_burst_default = 0x00000000, - regk_marb_bar_rw_no_snoop_default = 0x00000000, - regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, - regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, - regk_marb_bar_rw_stop_mask_default = 0x00000000, - regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, - regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, - regk_marb_bar_rw_vout_burst_default = 0x00000000, - regk_marb_bar_sclr_fifo = 0x00000007, - regk_marb_bar_sclr_rd = 0x00000005, - regk_marb_bar_vin_rd = 0x00000004, - regk_marb_bar_vin_wr = 0x00000003, - regk_marb_bar_vout = 0x00000006, - regk_marb_bar_yes = 0x00000001 -}; -#endif /* __marb_bar_defs_h */ -#ifndef __marb_bar_bp_defs_h -#define __marb_bar_bp_defs_h - -/* - * This file is autogenerated from - * file: marb_bar.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bar_bp */ - -/* Register rw_first_addr, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bar_bp_rw_op; -#define REG_RD_ADDR_marb_bar_bp_rw_op 8 -#define REG_WR_ADDR_marb_bar_bp_rw_op 8 - -/* Register rw_clients, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_rw_clients; -#define REG_RD_ADDR_marb_bar_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bar_bp_rw_clients 12 - -/* Register rw_options, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bar_bp_rw_options; -#define REG_RD_ADDR_marb_bar_bp_rw_options 16 -#define REG_WR_ADDR_marb_bar_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bar_bp, type r */ -typedef unsigned int reg_marb_bar_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bar_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bar_bp_r_brk_op; -#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bar_bp, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bar_bp, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bar_bp, type r */ -typedef unsigned int reg_marb_bar_bp_r_brk_size; -#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_ack; -#define REG_RD_ADDR_marb_bar_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bar_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bar_bp_no = 0x00000000, - regk_marb_bar_bp_rw_op_default = 0x00000000, - regk_marb_bar_bp_rw_options_default = 0x00000000, - regk_marb_bar_bp_yes = 0x00000001 -}; -#endif /* __marb_bar_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h deleted file mode 100644 index 2baa833f109a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h +++ /dev/null @@ -1,626 +0,0 @@ -#ifndef __marb_foo_defs_h -#define __marb_foo_defs_h - -/* - * This file is autogenerated from - * file: marb_foo.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_foo */ - -#define STRIDE_marb_foo_rw_intm_slots 4 -/* Register rw_intm_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_intm_slots; -#define REG_RD_ADDR_marb_foo_rw_intm_slots 0 -#define REG_WR_ADDR_marb_foo_rw_intm_slots 0 - -#define STRIDE_marb_foo_rw_l2_slots 4 -/* Register rw_l2_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_l2_slots; -#define REG_RD_ADDR_marb_foo_rw_l2_slots 256 -#define REG_WR_ADDR_marb_foo_rw_l2_slots 256 - -#define STRIDE_marb_foo_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_regs_slots; -#define REG_RD_ADDR_marb_foo_rw_regs_slots 512 -#define REG_WR_ADDR_marb_foo_rw_regs_slots 512 - -/* Register rw_sclr_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_sclr_burst; -#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 -#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 - -/* Register rw_dma0_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma0_burst; -#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 -#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 - -/* Register rw_dma1_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma1_burst; -#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 -#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 - -/* Register rw_dma2_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma2_burst; -#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 -#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 - -/* Register rw_dma3_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma3_burst; -#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 -#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 - -/* Register rw_dma4_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma4_burst; -#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 -#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 - -/* Register rw_dma5_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma5_burst; -#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 -#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 - -/* Register rw_dma6_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma6_burst; -#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 -#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 - -/* Register rw_dma7_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma7_burst; -#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 -#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 - -/* Register rw_dma9_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma9_burst; -#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 -#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 - -/* Register rw_dma11_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma11_burst; -#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 -#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 - -/* Register rw_cpui_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_cpui_burst; -#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 -#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 - -/* Register rw_cpud_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_cpud_burst; -#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 -#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 - -/* Register rw_iop_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_iop_burst; -#define REG_RD_ADDR_marb_foo_rw_iop_burst 580 -#define REG_WR_ADDR_marb_foo_rw_iop_burst 580 - -/* Register rw_ccdstat_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_ccdstat_burst; -#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 -#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 - -/* Register rw_intr_mask, scope marb_foo, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_intr_mask; -#define REG_RD_ADDR_marb_foo_rw_intr_mask 588 -#define REG_WR_ADDR_marb_foo_rw_intr_mask 588 - -/* Register rw_ack_intr, scope marb_foo, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_ack_intr; -#define REG_RD_ADDR_marb_foo_rw_ack_intr 592 -#define REG_WR_ADDR_marb_foo_rw_ack_intr 592 - -/* Register r_intr, scope marb_foo, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_r_intr; -#define REG_RD_ADDR_marb_foo_r_intr 596 - -/* Register r_masked_intr, scope marb_foo, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_r_masked_intr; -#define REG_RD_ADDR_marb_foo_r_masked_intr 600 - -/* Register rw_stop_mask, scope marb_foo, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_rw_stop_mask; -#define REG_RD_ADDR_marb_foo_rw_stop_mask 604 -#define REG_WR_ADDR_marb_foo_rw_stop_mask 604 - -/* Register r_stopped, scope marb_foo, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_r_stopped; -#define REG_RD_ADDR_marb_foo_r_stopped 608 - -/* Register rw_no_snoop, scope marb_foo, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_rw_no_snoop; -#define REG_RD_ADDR_marb_foo_rw_no_snoop 896 -#define REG_WR_ADDR_marb_foo_rw_no_snoop 896 - -/* Register rw_no_snoop_rq, scope marb_foo, type rw */ -typedef struct { - unsigned int dummy1 : 11; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 19; -} reg_marb_foo_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 -#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 - - -/* Constants */ -enum { - regk_marb_foo_ccdstat = 0x0000000e, - regk_marb_foo_cpud = 0x0000000c, - regk_marb_foo_cpui = 0x0000000b, - regk_marb_foo_dma0 = 0x00000001, - regk_marb_foo_dma1 = 0x00000002, - regk_marb_foo_dma11 = 0x0000000a, - regk_marb_foo_dma2 = 0x00000003, - regk_marb_foo_dma3 = 0x00000004, - regk_marb_foo_dma4 = 0x00000005, - regk_marb_foo_dma5 = 0x00000006, - regk_marb_foo_dma6 = 0x00000007, - regk_marb_foo_dma7 = 0x00000008, - regk_marb_foo_dma9 = 0x00000009, - regk_marb_foo_iop = 0x0000000d, - regk_marb_foo_no = 0x00000000, - regk_marb_foo_r_stopped_default = 0x00000000, - regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, - regk_marb_foo_rw_cpud_burst_default = 0x00000000, - regk_marb_foo_rw_cpui_burst_default = 0x00000000, - regk_marb_foo_rw_dma0_burst_default = 0x00000000, - regk_marb_foo_rw_dma11_burst_default = 0x00000000, - regk_marb_foo_rw_dma1_burst_default = 0x00000000, - regk_marb_foo_rw_dma2_burst_default = 0x00000000, - regk_marb_foo_rw_dma3_burst_default = 0x00000000, - regk_marb_foo_rw_dma4_burst_default = 0x00000000, - regk_marb_foo_rw_dma5_burst_default = 0x00000000, - regk_marb_foo_rw_dma6_burst_default = 0x00000000, - regk_marb_foo_rw_dma7_burst_default = 0x00000000, - regk_marb_foo_rw_dma9_burst_default = 0x00000000, - regk_marb_foo_rw_intm_slots_default = 0x00000000, - regk_marb_foo_rw_intm_slots_size = 0x00000040, - regk_marb_foo_rw_intr_mask_default = 0x00000000, - regk_marb_foo_rw_iop_burst_default = 0x00000000, - regk_marb_foo_rw_l2_slots_default = 0x00000000, - regk_marb_foo_rw_l2_slots_size = 0x00000040, - regk_marb_foo_rw_no_snoop_default = 0x00000000, - regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, - regk_marb_foo_rw_regs_slots_default = 0x00000000, - regk_marb_foo_rw_regs_slots_size = 0x00000004, - regk_marb_foo_rw_sclr_burst_default = 0x00000000, - regk_marb_foo_rw_stop_mask_default = 0x00000000, - regk_marb_foo_sclr = 0x00000000, - regk_marb_foo_yes = 0x00000001 -}; -#endif /* __marb_foo_defs_h */ -#ifndef __marb_foo_bp_defs_h -#define __marb_foo_bp_defs_h - -/* - * This file is autogenerated from - * file: marb_foo.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_foo_bp */ - -/* Register rw_first_addr, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_first_addr; -#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_last_addr; -#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_foo_bp_rw_op; -#define REG_RD_ADDR_marb_foo_bp_rw_op 8 -#define REG_WR_ADDR_marb_foo_bp_rw_op 8 - -/* Register rw_clients, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_rw_clients; -#define REG_RD_ADDR_marb_foo_bp_rw_clients 12 -#define REG_WR_ADDR_marb_foo_bp_rw_clients 12 - -/* Register rw_options, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_foo_bp_rw_options; -#define REG_RD_ADDR_marb_foo_bp_rw_options 16 -#define REG_WR_ADDR_marb_foo_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_foo_bp, type r */ -typedef unsigned int reg_marb_foo_bp_r_brk_addr; -#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_foo_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_foo_bp_r_brk_op; -#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_foo_bp, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_r_brk_clients; -#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_foo_bp, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_foo_bp, type r */ -typedef unsigned int reg_marb_foo_bp_r_brk_size; -#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_ack; -#define REG_RD_ADDR_marb_foo_bp_rw_ack 40 -#define REG_WR_ADDR_marb_foo_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_foo_bp_no = 0x00000000, - regk_marb_foo_bp_rw_op_default = 0x00000000, - regk_marb_foo_bp_rw_options_default = 0x00000000, - regk_marb_foo_bp_yes = 0x00000001 -}; -#endif /* __marb_foo_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h deleted file mode 100644 index 4b96cd2cba8a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h +++ /dev/null @@ -1,312 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: pinmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int eth_mdio : 1; - unsigned int geth : 1; - unsigned int tg : 1; - unsigned int tg_clk : 1; - unsigned int vout : 1; - unsigned int vout_sync : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int pwm0 : 1; - unsigned int pwm1 : 1; - unsigned int pwm2 : 1; - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int pio : 1; - unsigned int i2c0 : 1; - unsigned int i2c1 : 1; - unsigned int i2c1_sda1 : 1; - unsigned int i2c1_sda2 : 1; - unsigned int i2c1_sda3 : 1; - unsigned int i2c1_sen : 1; - unsigned int dummy1 : 8; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 0 -#define REG_WR_ADDR_pinmux_rw_hwprot 0 - -/* Register rw_gio_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int pa8 : 1; - unsigned int pa9 : 1; - unsigned int pa10 : 1; - unsigned int pa11 : 1; - unsigned int pa12 : 1; - unsigned int pa13 : 1; - unsigned int pa14 : 1; - unsigned int pa15 : 1; - unsigned int pa16 : 1; - unsigned int pa17 : 1; - unsigned int pa18 : 1; - unsigned int pa19 : 1; - unsigned int pa20 : 1; - unsigned int pa21 : 1; - unsigned int pa22 : 1; - unsigned int pa23 : 1; - unsigned int pa24 : 1; - unsigned int pa25 : 1; - unsigned int pa26 : 1; - unsigned int pa27 : 1; - unsigned int pa28 : 1; - unsigned int pa29 : 1; - unsigned int pa30 : 1; - unsigned int pa31 : 1; -} reg_pinmux_rw_gio_pa; -#define REG_RD_ADDR_pinmux_rw_gio_pa 4 -#define REG_WR_ADDR_pinmux_rw_gio_pa 4 - -/* Register rw_gio_pb, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int pb18 : 1; - unsigned int pb19 : 1; - unsigned int pb20 : 1; - unsigned int pb21 : 1; - unsigned int pb22 : 1; - unsigned int pb23 : 1; - unsigned int pb24 : 1; - unsigned int pb25 : 1; - unsigned int pb26 : 1; - unsigned int pb27 : 1; - unsigned int pb28 : 1; - unsigned int pb29 : 1; - unsigned int pb30 : 1; - unsigned int pb31 : 1; -} reg_pinmux_rw_gio_pb; -#define REG_RD_ADDR_pinmux_rw_gio_pb 8 -#define REG_WR_ADDR_pinmux_rw_gio_pb 8 - -/* Register rw_gio_pc, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_gio_pc; -#define REG_RD_ADDR_pinmux_rw_gio_pc 12 -#define REG_WR_ADDR_pinmux_rw_gio_pc 12 - -/* Register rw_iop_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int pa8 : 1; - unsigned int pa9 : 1; - unsigned int pa10 : 1; - unsigned int pa11 : 1; - unsigned int pa12 : 1; - unsigned int pa13 : 1; - unsigned int pa14 : 1; - unsigned int pa15 : 1; - unsigned int pa16 : 1; - unsigned int pa17 : 1; - unsigned int pa18 : 1; - unsigned int pa19 : 1; - unsigned int pa20 : 1; - unsigned int pa21 : 1; - unsigned int pa22 : 1; - unsigned int pa23 : 1; - unsigned int pa24 : 1; - unsigned int pa25 : 1; - unsigned int pa26 : 1; - unsigned int pa27 : 1; - unsigned int pa28 : 1; - unsigned int pa29 : 1; - unsigned int pa30 : 1; - unsigned int pa31 : 1; -} reg_pinmux_rw_iop_pa; -#define REG_RD_ADDR_pinmux_rw_iop_pa 16 -#define REG_WR_ADDR_pinmux_rw_iop_pa 16 - -/* Register rw_iop_pb, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int dummy1 : 24; -} reg_pinmux_rw_iop_pb; -#define REG_RD_ADDR_pinmux_rw_iop_pb 20 -#define REG_WR_ADDR_pinmux_rw_iop_pb 20 - -/* Register rw_iop_pio, scope pinmux, type rw */ -typedef struct { - unsigned int d0 : 1; - unsigned int d1 : 1; - unsigned int d2 : 1; - unsigned int d3 : 1; - unsigned int d4 : 1; - unsigned int d5 : 1; - unsigned int d6 : 1; - unsigned int d7 : 1; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_iop_pio; -#define REG_RD_ADDR_pinmux_rw_iop_pio 24 -#define REG_WR_ADDR_pinmux_rw_iop_pio 24 - -/* Register rw_iop_usb, scope pinmux, type rw */ -typedef struct { - unsigned int usb0 : 1; - unsigned int dummy1 : 31; -} reg_pinmux_rw_iop_usb; -#define REG_RD_ADDR_pinmux_rw_iop_usb 28 -#define REG_WR_ADDR_pinmux_rw_iop_usb 28 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_gio_pa_default = 0x00000000, - regk_pinmux_rw_gio_pb_default = 0x00000000, - regk_pinmux_rw_gio_pc_default = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_iop_pa_default = 0x00000000, - regk_pinmux_rw_iop_pb_default = 0x00000000, - regk_pinmux_rw_iop_pio_default = 0x00000000, - regk_pinmux_rw_iop_usb_default = 0x00000001, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h deleted file mode 100644 index 2d8e4b4cc602..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h +++ /dev/null @@ -1,371 +0,0 @@ -#ifndef __pio_defs_h -#define __pio_defs_h - -/* - * This file is autogenerated from - * file: pio.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pio */ - -/* Register rw_data, scope pio, type rw */ -typedef unsigned int reg_pio_rw_data; -#define REG_RD_ADDR_pio_rw_data 64 -#define REG_WR_ADDR_pio_rw_data 64 - -/* Register rw_io_access0, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access0; -#define REG_RD_ADDR_pio_rw_io_access0 0 -#define REG_WR_ADDR_pio_rw_io_access0 0 - -/* Register rw_io_access1, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access1; -#define REG_RD_ADDR_pio_rw_io_access1 4 -#define REG_WR_ADDR_pio_rw_io_access1 4 - -/* Register rw_io_access2, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access2; -#define REG_RD_ADDR_pio_rw_io_access2 8 -#define REG_WR_ADDR_pio_rw_io_access2 8 - -/* Register rw_io_access3, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access3; -#define REG_RD_ADDR_pio_rw_io_access3 12 -#define REG_WR_ADDR_pio_rw_io_access3 12 - -/* Register rw_io_access4, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access4; -#define REG_RD_ADDR_pio_rw_io_access4 16 -#define REG_WR_ADDR_pio_rw_io_access4 16 - -/* Register rw_io_access5, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access5; -#define REG_RD_ADDR_pio_rw_io_access5 20 -#define REG_WR_ADDR_pio_rw_io_access5 20 - -/* Register rw_io_access6, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access6; -#define REG_RD_ADDR_pio_rw_io_access6 24 -#define REG_WR_ADDR_pio_rw_io_access6 24 - -/* Register rw_io_access7, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access7; -#define REG_RD_ADDR_pio_rw_io_access7 28 -#define REG_WR_ADDR_pio_rw_io_access7 28 - -/* Register rw_io_access8, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access8; -#define REG_RD_ADDR_pio_rw_io_access8 32 -#define REG_WR_ADDR_pio_rw_io_access8 32 - -/* Register rw_io_access9, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access9; -#define REG_RD_ADDR_pio_rw_io_access9 36 -#define REG_WR_ADDR_pio_rw_io_access9 36 - -/* Register rw_io_access10, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access10; -#define REG_RD_ADDR_pio_rw_io_access10 40 -#define REG_WR_ADDR_pio_rw_io_access10 40 - -/* Register rw_io_access11, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access11; -#define REG_RD_ADDR_pio_rw_io_access11 44 -#define REG_WR_ADDR_pio_rw_io_access11 44 - -/* Register rw_io_access12, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access12; -#define REG_RD_ADDR_pio_rw_io_access12 48 -#define REG_WR_ADDR_pio_rw_io_access12 48 - -/* Register rw_io_access13, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access13; -#define REG_RD_ADDR_pio_rw_io_access13 52 -#define REG_WR_ADDR_pio_rw_io_access13 52 - -/* Register rw_io_access14, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access14; -#define REG_RD_ADDR_pio_rw_io_access14 56 -#define REG_WR_ADDR_pio_rw_io_access14 56 - -/* Register rw_io_access15, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access15; -#define REG_RD_ADDR_pio_rw_io_access15 60 -#define REG_WR_ADDR_pio_rw_io_access15 60 - -/* Register rw_ce0_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce0_cfg; -#define REG_RD_ADDR_pio_rw_ce0_cfg 68 -#define REG_WR_ADDR_pio_rw_ce0_cfg 68 - -/* Register rw_ce1_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce1_cfg; -#define REG_RD_ADDR_pio_rw_ce1_cfg 72 -#define REG_WR_ADDR_pio_rw_ce1_cfg 72 - -/* Register rw_ce2_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce2_cfg; -#define REG_RD_ADDR_pio_rw_ce2_cfg 76 -#define REG_WR_ADDR_pio_rw_ce2_cfg 76 - -/* Register rw_dout, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_dout; -#define REG_RD_ADDR_pio_rw_dout 80 -#define REG_WR_ADDR_pio_rw_dout 80 - -/* Register rw_oe, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_oe; -#define REG_RD_ADDR_pio_rw_oe 84 -#define REG_WR_ADDR_pio_rw_oe 84 - -/* Register rw_man_ctrl, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_man_ctrl; -#define REG_RD_ADDR_pio_rw_man_ctrl 88 -#define REG_WR_ADDR_pio_rw_man_ctrl 88 - -/* Register r_din, scope pio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_r_din; -#define REG_RD_ADDR_pio_r_din 92 - -/* Register r_stat, scope pio, type r */ -typedef struct { - unsigned int busy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_stat; -#define REG_RD_ADDR_pio_r_stat 96 - -/* Register rw_intr_mask, scope pio, type rw */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_rw_intr_mask; -#define REG_RD_ADDR_pio_rw_intr_mask 100 -#define REG_WR_ADDR_pio_rw_intr_mask 100 - -/* Register rw_ack_intr, scope pio, type rw */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_rw_ack_intr; -#define REG_RD_ADDR_pio_rw_ack_intr 104 -#define REG_WR_ADDR_pio_rw_ack_intr 104 - -/* Register r_intr, scope pio, type r */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_intr; -#define REG_RD_ADDR_pio_r_intr 108 - -/* Register r_masked_intr, scope pio, type r */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_masked_intr; -#define REG_RD_ADDR_pio_r_masked_intr 112 - - -/* Constants */ -enum { - regk_pio_a2 = 0x00000003, - regk_pio_no = 0x00000000, - regk_pio_normal = 0x00000000, - regk_pio_rd = 0x00000001, - regk_pio_rw_ce0_cfg_default = 0x00000000, - regk_pio_rw_ce1_cfg_default = 0x00000000, - regk_pio_rw_ce2_cfg_default = 0x00000000, - regk_pio_rw_intr_mask_default = 0x00000000, - regk_pio_rw_man_ctrl_default = 0x00000000, - regk_pio_rw_oe_default = 0x00000000, - regk_pio_wr = 0x00000002, - regk_pio_wr_ce2 = 0x00000003, - regk_pio_yes = 0x00000001, - regk_pio_yes_all = 0x000000ff -}; -#endif /* __pio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h deleted file mode 100644 index 36e59d6e96b6..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: reg.rmap - * - * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ccd = 0xb0000000, - regi_ccd_top = 0xb0000000, - regi_ccd_dp = 0xb0000400, - regi_ccd_stat = 0xb0000800, - regi_ccd_tg = 0xb0001000, - regi_cfg = 0xb0002000, - regi_clkgen = 0xb0004000, - regi_ddr2_ctrl = 0xb0006000, - regi_dma0 = 0xb0008000, - regi_dma1 = 0xb000a000, - regi_dma11 = 0xb000c000, - regi_dma2 = 0xb000e000, - regi_dma3 = 0xb0010000, - regi_dma4 = 0xb0012000, - regi_dma5 = 0xb0014000, - regi_dma6 = 0xb0016000, - regi_dma7 = 0xb0018000, - regi_dma9 = 0xb001a000, - regi_eth = 0xb001c000, - regi_gio = 0xb0020000, - regi_h264 = 0xb0022000, - regi_hist = 0xb0026000, - regi_iop = 0xb0028000, - regi_iop_version = 0xb0028000, - regi_iop_fifo_in_extra = 0xb0028040, - regi_iop_fifo_out_extra = 0xb0028080, - regi_iop_trigger_grp0 = 0xb00280c0, - regi_iop_trigger_grp1 = 0xb0028100, - regi_iop_trigger_grp2 = 0xb0028140, - regi_iop_trigger_grp3 = 0xb0028180, - regi_iop_trigger_grp4 = 0xb00281c0, - regi_iop_trigger_grp5 = 0xb0028200, - regi_iop_trigger_grp6 = 0xb0028240, - regi_iop_trigger_grp7 = 0xb0028280, - regi_iop_crc_par = 0xb0028300, - regi_iop_dmc_in = 0xb0028380, - regi_iop_dmc_out = 0xb0028400, - regi_iop_fifo_in = 0xb0028480, - regi_iop_fifo_out = 0xb0028500, - regi_iop_scrc_in = 0xb0028580, - regi_iop_scrc_out = 0xb0028600, - regi_iop_timer_grp0 = 0xb0028680, - regi_iop_timer_grp1 = 0xb0028700, - regi_iop_sap_in = 0xb0028800, - regi_iop_sap_out = 0xb0028900, - regi_iop_spu = 0xb0028a00, - regi_iop_sw_cfg = 0xb0028b00, - regi_iop_sw_cpu = 0xb0028c00, - regi_iop_sw_mpu = 0xb0028d00, - regi_iop_sw_spu = 0xb0028e00, - regi_iop_mpu = 0xb0029000, - regi_irq = 0xb002a000, - regi_irq2 = 0xb006a000, - regi_jpeg = 0xb002c000, - regi_l2cache = 0xb0030000, - regi_marb_bar = 0xb0032000, - regi_marb_bar_bp0 = 0xb0032140, - regi_marb_bar_bp1 = 0xb0032180, - regi_marb_bar_bp2 = 0xb00321c0, - regi_marb_bar_bp3 = 0xb0032200, - regi_marb_foo = 0xb0034000, - regi_marb_foo_bp0 = 0xb0034280, - regi_marb_foo_bp1 = 0xb00342c0, - regi_marb_foo_bp2 = 0xb0034300, - regi_marb_foo_bp3 = 0xb0034340, - regi_pinmux = 0xb0038000, - regi_pio = 0xb0036000, - regi_sclr = 0xb003a000, - regi_sclr_fifo = 0xb003c000, - regi_ser0 = 0xb003e000, - regi_ser1 = 0xb0040000, - regi_ser2 = 0xb0042000, - regi_ser3 = 0xb0044000, - regi_ser4 = 0xb0046000, - regi_sser = 0xb0048000, - regi_strcop = 0xb004a000, - regi_strdma0 = 0xb004e000, - regi_strdma1 = 0xb0050000, - regi_strdma2 = 0xb0052000, - regi_strdma3 = 0xb0054000, - regi_strdma5 = 0xb0056000, - regi_strmux = 0xb004c000, - regi_timer0 = 0xb0058000, - regi_timer1 = 0xb005a000, - regi_timer2 = 0xb006e000, - regi_trace = 0xb005c000, - regi_vin = 0xb005e000, - regi_vout = 0xb0060000 -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h deleted file mode 100644 index 14f718a4ecc3..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: strmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 2; - unsigned int dma1 : 2; - unsigned int dma2 : 2; - unsigned int dma3 : 2; - unsigned int dma4 : 2; - unsigned int dma5 : 2; - unsigned int dma6 : 2; - unsigned int dma7 : 2; - unsigned int dummy1 : 2; - unsigned int dma9 : 2; - unsigned int dummy2 : 2; - unsigned int dma11 : 2; - unsigned int dummy3 : 8; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_eth = 0x00000001, - regk_strmux_h264 = 0x00000001, - regk_strmux_iop = 0x00000001, - regk_strmux_jpeg = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000002, - regk_strmux_ser3 = 0x00000002, - regk_strmux_ser4 = 0x00000002, - regk_strmux_sser = 0x00000001, - regk_strmux_strcop = 0x00000001 -}; -#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h deleted file mode 100644 index 2c33e097d60a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h +++ /dev/null @@ -1,265 +0,0 @@ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: timer.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_f90 = 0x00000003, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_vclk = 0x00000002, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h deleted file mode 100644 index 7e15c9eb4e49..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/memmap.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00018000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h deleted file mode 100644 index db42a7254584..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/pinmux.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_A 0 -#define PORT_B 1 -#define PORT_C 2 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_eth, - pinmux_geth, - pinmux_tg_ccd, - pinmux_tg_cmos, - pinmux_vout, - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_ser4, - pinmux_sser, - pinmux_pio, - pinmux_pwm0, - pinmux_pwm1, - pinmux_pwm2, - pinmux_i2c0, - pinmux_i2c1, - pinmux_i2c1_3wire, - pinmux_i2c1_sda1, - pinmux_i2c1_sda2, - pinmux_i2c1_sda3, -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc deleted file mode 100644 index 2f23e5e16f4a..000000000000 --- a/include/asm-cris/arch-v32/mach-a3/startup.inc +++ /dev/null @@ -1,60 +0,0 @@ -#include <hwregs/asm/reg_map_asm.h> -#include <hwregs/asm/gio_defs_asm.h> -#include <hwregs/asm/pio_defs_asm.h> -#include <hwregs/asm/clkgen_defs_asm.h> -#include <hwregs/asm/pinmux_defs_asm.h> - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d 0xFFFFFFFF, $r0 - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 - move.d $r0, [$r1] - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 - move.d $r0, [$r1] - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 - move.d $r0, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ - REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 - move.d $r1, [$r0] - .endm diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h deleted file mode 100644 index a2e0ec8faa7d..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/arbiter.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index 0a409c92837e..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,319 +0,0 @@ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h deleted file mode 100644 index a9908dfc2937..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index be4c63936d90..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 30cf5a936b64..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,632 +0,0 @@ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 87517aebd2cb..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index e1197194d5c1..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,229 +0,0 @@ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h deleted file mode 100644 index 44362a62b47c..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h +++ /dev/null @@ -1,284 +0,0 @@ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h deleted file mode 100644 index 3cb51a09dba7..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,473 +0,0 @@ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h deleted file mode 100644 index 0c434585a3f9..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,249 +0,0 @@ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h deleted file mode 100644 index abc5f20705f7..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h deleted file mode 100644 index 26aa3efcf91b..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h +++ /dev/null @@ -1,295 +0,0 @@ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h deleted file mode 100644 index bacc2a895c21..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define GIO_INTR_VECT GEN_IO_INTR_VECT -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define TIMER0_INTR_VECT TIMER_INTR_VECT -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f -#define NBR_INTR_VECT 0x50 -#endif diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h deleted file mode 100644 index aa65128ae1aa..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - -#define STRIDE_intr_vect_rw_mask 0 -/* Register rw_mask, scope intr_vect, type rw */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer0 : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_rw_mask; -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 - -#define STRIDE_intr_vect_r_vect 0 -/* Register r_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_vect; -#define REG_RD_ADDR_intr_vect_r_vect 4 - -#define STRIDE_intr_vect_r_masked_vect 0 -/* Register r_masked_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_masked_vect; -#define REG_RD_ADDR_intr_vect_r_masked_vect 8 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int ext : 1; - unsigned int watchdog : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 12 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 16 - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 20 -#define REG_WR_ADDR_intr_vect_rw_ipi 20 - -/* Constants */ -enum { - regk_intr_vect_off = 0x00000000, - regk_intr_vect_on = 0x00000001, - regk_intr_vect_rw_mask_default = 0x00000000 -}; -#endif /* __intr_vect_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h deleted file mode 100644 index dcaaec4620ba..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,205 +0,0 @@ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h deleted file mode 100644 index 254da0854986..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h +++ /dev/null @@ -1,475 +0,0 @@ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h deleted file mode 100644 index 751eab5f191c..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h +++ /dev/null @@ -1,357 +0,0 @@ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h deleted file mode 100644 index 4146973a58b3..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ata = 0xb0032000, - regi_bif_core = 0xb0014000, - regi_bif_dma = 0xb0016000, - regi_bif_slave = 0xb0018000, - regi_config = 0xb003c000, - regi_dma0 = 0xb0000000, - regi_dma1 = 0xb0002000, - regi_dma2 = 0xb0004000, - regi_dma3 = 0xb0006000, - regi_dma4 = 0xb0008000, - regi_dma5 = 0xb000a000, - regi_dma6 = 0xb000c000, - regi_dma7 = 0xb000e000, - regi_dma8 = 0xb0010000, - regi_dma9 = 0xb0012000, - regi_eth0 = 0xb0034000, - regi_eth1 = 0xb0036000, - regi_gio = 0xb001a000, - regi_iop = 0xb0020000, - regi_iop_version = 0xb0020000, - regi_iop_fifo_in0_extra = 0xb0020040, - regi_iop_fifo_in1_extra = 0xb0020080, - regi_iop_fifo_out0_extra = 0xb00200c0, - regi_iop_fifo_out1_extra = 0xb0020100, - regi_iop_trigger_grp0 = 0xb0020140, - regi_iop_trigger_grp1 = 0xb0020180, - regi_iop_trigger_grp2 = 0xb00201c0, - regi_iop_trigger_grp3 = 0xb0020200, - regi_iop_trigger_grp4 = 0xb0020240, - regi_iop_trigger_grp5 = 0xb0020280, - regi_iop_trigger_grp6 = 0xb00202c0, - regi_iop_trigger_grp7 = 0xb0020300, - regi_iop_crc_par0 = 0xb0020380, - regi_iop_crc_par1 = 0xb0020400, - regi_iop_dmc_in0 = 0xb0020480, - regi_iop_dmc_in1 = 0xb0020500, - regi_iop_dmc_out0 = 0xb0020580, - regi_iop_dmc_out1 = 0xb0020600, - regi_iop_fifo_in0 = 0xb0020680, - regi_iop_fifo_in1 = 0xb0020700, - regi_iop_fifo_out0 = 0xb0020780, - regi_iop_fifo_out1 = 0xb0020800, - regi_iop_scrc_in0 = 0xb0020880, - regi_iop_scrc_in1 = 0xb0020900, - regi_iop_scrc_out0 = 0xb0020980, - regi_iop_scrc_out1 = 0xb0020a00, - regi_iop_timer_grp0 = 0xb0020a80, - regi_iop_timer_grp1 = 0xb0020b00, - regi_iop_timer_grp2 = 0xb0020b80, - regi_iop_timer_grp3 = 0xb0020c00, - regi_iop_sap_in = 0xb0020d00, - regi_iop_sap_out = 0xb0020e00, - regi_iop_spu0 = 0xb0020f00, - regi_iop_spu1 = 0xb0021000, - regi_iop_sw_cfg = 0xb0021100, - regi_iop_sw_cpu = 0xb0021200, - regi_iop_sw_mpu = 0xb0021300, - regi_iop_sw_spu0 = 0xb0021400, - regi_iop_sw_spu1 = 0xb0021500, - regi_iop_mpu = 0xb0021600, - regi_irq = 0xb001c000, - regi_irq2 = 0xb005c000, - regi_marb = 0xb003e000, - regi_marb_bp0 = 0xb003e240, - regi_marb_bp1 = 0xb003e280, - regi_marb_bp2 = 0xb003e2c0, - regi_marb_bp3 = 0xb003e300, - regi_pinmux = 0xb0038000, - regi_ser0 = 0xb0026000, - regi_ser1 = 0xb0028000, - regi_ser2 = 0xb002a000, - regi_ser3 = 0xb002c000, - regi_sser0 = 0xb0022000, - regi_sser1 = 0xb0024000, - regi_strcop = 0xb0030000, - regi_strmux = 0xb003a000, - regi_timer = 0xb001e000, - regi_timer0 = 0xb001e000, - regi_timer2 = 0xb005e000, - regi_trace = 0xb0040000, -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h deleted file mode 100644 index cbfaa867829e..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h deleted file mode 100644 index 76bcc591921d..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h +++ /dev/null @@ -1,266 +0,0 @@ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h deleted file mode 100644 index c2b3036779df..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/pinmux.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc deleted file mode 100644 index 4a10ccbd6cc1..000000000000 --- a/include/asm-cris/arch-v32/mach-fs/startup.inc +++ /dev/null @@ -1,77 +0,0 @@ -#include <hwregs/asm/reg_map_asm.h> -#include <hwregs/asm/bif_core_defs_asm.h> -#include <hwregs/asm/gio_defs_asm.h> -#include <hwregs/asm/config_defs_asm.h> - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 - move.d $r0, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - ;; Set up waitstates etc - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 - move.d $r1, [$r0] -#ifdef CONFIG_ETRAX_VCS_SIM - ;; Set up minimal flash waitstates - move.d 0, $r10 - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 - move.d $r10, [$r11] -#endif - .endm diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h deleted file mode 100644 index d29df5644d3e..000000000000 --- a/include/asm-cris/arch-v32/memmap.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00020000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h deleted file mode 100644 index 6bcdc3fdf7dc..000000000000 --- a/include/asm-cris/arch-v32/mmu.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_MMU_H -#define _ASM_CRIS_ARCH_MMU_H - -/* MMU context type. */ -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* Kernel memory segments. */ -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* - * CRISv32 PTE bits: - * - * Bit: 31-13 12-5 4 3 2 1 0 - * +-----+------+--------+-------+--------+-------+---------+ - * | pfn | zero | global | valid | kernel | write | execute | - * +-----+------+--------+-------+--------+-------+---------+ - */ - -/* - * Defines for accessing the bits. Also define some synonyms for use with - * the software-based defined bits below. - */ -#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ -#define _PAGE_WE (1 << 1) /* Write bit. */ -#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ -#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ -#define _PAGE_VALID (1 << 3) /* Page is valid. */ -#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ -#define _PAGE_GLOBAL (1 << 4) /* Global page. */ - -/* - * The hardware doesn't care about these bits, but the kernel uses them in - * software. - */ -#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ -#define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */ -#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ -#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ -#define _PAGE_READ (1 << 8) /* Read enabled. */ -#define _PAGE_WRITE (1 << 9) /* Write enabled. */ - -/* Define some higher level generic page attributes. */ -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED | _PAGE_EXECUTE) - -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) - -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE) - -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* CRISv32 can do page protection for execute. - * Write permissions imply read permissions. - * Note that the numbers are in Execute-Write-Read order! - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY_EXEC -#define __P101 PAGE_READONLY_EXEC -#define __P110 PAGE_COPY_EXEC -#define __P111 PAGE_COPY_EXEC - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY_EXEC -#define __S101 PAGE_READONLY_EXEC -#define __S110 PAGE_SHARED_EXEC -#define __S111 PAGE_SHARED_EXEC - -#define PTE_FILE_MAX_BITS 25 - -#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h deleted file mode 100644 index 4442c4bd52f4..000000000000 --- a/include/asm-cris/arch-v32/offset.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ -#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ -#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ -#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ -#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ -#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ - -#define TASK_pid 151 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h deleted file mode 100644 index 20f1b4806bfe..000000000000 --- a/include/asm-cris/arch-v32/page.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PAGE_H -#define _ASM_CRIS_ARCH_PAGE_H - - -#ifdef __KERNEL__ - -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ - -/* - * Macros to convert between physical and virtual addresses. By stripping a - * selected bit it's possible to convert between KSEG_x and 0x40000000 where the - * DRAM really resides. DRAM is virtually at 0xc. - */ -#ifndef CONFIG_ETRAX_VCS_SIM -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) -#else -#define __pa(x) ((unsigned long)(x) & 0x3fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000)) -#endif - -#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ - VM_MAYREAD | VM_MAYWRITE) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h deleted file mode 100644 index 08cb7ff7e4e7..000000000000 --- a/include/asm-cris/arch-v32/pgtable.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PGTABLE_H -#define _ASM_CRIS_ARCH_PGTABLE_H - -/* Define the kernels virtual memory area. */ -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) - -#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h deleted file mode 100644 index bb09bce42e7a..000000000000 --- a/include/asm-cris/arch-v32/pinmux.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode -{ - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function -{ - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h deleted file mode 100644 index f80b47790ca6..000000000000 --- a/include/asm-cris/arch-v32/processor.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_PROCESSOR_H -#define _ASM_CRIS_ARCH_PROCESSOR_H - - -/* Return current instruction pointer. */ -#define current_text_addr() \ - ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) - -/* - * Since CRIS doesn't do hardware task-switching this hasn't really anything to - * do with the proccessor itself, it's just here for legacy reasons. This is - * used when task-switching using _resume defined in entry.S. The offsets here - * are hardcoded into _resume, so if this struct is changed, entry.S needs to be - * changed as well. - */ -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer. */ - unsigned long usp; /* User stack pointer. */ - unsigned long ccs; /* Saved flags register. */ -}; - -/* - * User-space process size. This is hardcoded into a few places, so don't - * changed it unless everything's clear! - */ -#ifndef CONFIG_ETRAX_VCS_SIM -#define TASK_SIZE (0xB0000000UL) -#else -#define TASK_SIZE (0xA0000000UL) -#endif - -/* CCS I=1, enable interrupts. */ -#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) } - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)task_pt_regs(tsk); \ - if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->erp; \ - eip; \ -}) - -/* - * Give the thread a program location, set user-mode and switch user - * stackpointer. - */ -#define start_thread(regs, ip, usp) \ -do { \ - set_fs(USER_DS); \ - regs->erp = ip; \ - regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ - wrusp(usp); \ -} while(0) - -/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ -#define arch_fixup(regs) {}; - -#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h deleted file mode 100644 index 41f4e8662bc2..000000000000 --- a/include/asm-cris/arch-v32/ptrace.h +++ /dev/null @@ -1,118 +0,0 @@ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Register numbers in the ptrace system call interface */ - -#define PT_ORIG_R10 0 -#define PT_R0 1 -#define PT_R1 2 -#define PT_R2 3 -#define PT_R3 4 -#define PT_R4 5 -#define PT_R5 6 -#define PT_R6 7 -#define PT_R7 8 -#define PT_R8 9 -#define PT_R9 10 -#define PT_R10 11 -#define PT_R11 12 -#define PT_R12 13 -#define PT_R13 14 -#define PT_ACR 15 -#define PT_SRS 16 -#define PT_MOF 17 -#define PT_SPC 18 -#define PT_CCS 19 -#define PT_SRP 20 -#define PT_ERP 21 /* This is actually the debugged process' PC */ -#define PT_EXS 22 -#define PT_EDA 23 -#define PT_USP 24 /* special case - USP is not in the pt_regs */ -#define PT_PPC 25 /* special case - pseudo PC */ -#define PT_BP 26 /* Base number for BP registers. */ -#define PT_BP_CTRL 26 /* BP control register. */ -#define PT_MAX 40 - -/* Condition code bit numbers. */ -#define C_CCS_BITNR 0 -#define V_CCS_BITNR 1 -#define Z_CCS_BITNR 2 -#define N_CCS_BITNR 3 -#define X_CCS_BITNR 4 -#define I_CCS_BITNR 5 -#define U_CCS_BITNR 6 -#define P_CCS_BITNR 7 -#define R_CCS_BITNR 8 -#define S_CCS_BITNR 9 -#define M_CCS_BITNR 30 -#define Q_CCS_BITNR 31 -#define CCS_SHIFT 10 /* Shift count for each level in CCS */ - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL. */ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long acr; - unsigned long srs; - unsigned long mof; - unsigned long spc; - unsigned long ccs; - unsigned long srp; - unsigned long erp; /* This is actually the debugged process' PC */ - /* For debugging purposes; saved only when needed. */ - unsigned long exs; - unsigned long eda; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) -#define instruction_pointer(regs) ((regs)->erp) -extern void show_regs(struct pt_regs *); -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h deleted file mode 100644 index 0d5709b983a1..000000000000 --- a/include/asm-cris/arch-v32/spinlock.h +++ /dev/null @@ -1,129 +0,0 @@ -#ifndef __ASM_ARCH_SPINLOCK_H -#define __ASM_ARCH_SPINLOCK_H - -#include <linux/spinlock_types.h> - -#define RW_LOCK_BIAS 0x01000000 - -extern void cris_spin_unlock(void *l, int val); -extern void cris_spin_lock(void *l); -extern int cris_spin_trylock(void *l); - -static inline int __raw_spin_is_locked(raw_spinlock_t *x) -{ - return *(volatile signed char *)(&(x)->slock) <= 0; -} - -static inline void __raw_spin_unlock(raw_spinlock_t *lock) -{ - __asm__ volatile ("move.d %1,%0" \ - : "=m" (lock->slock) \ - : "r" (1) \ - : "memory"); -} - -static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) -{ - while (__raw_spin_is_locked(lock)) - cpu_relax(); -} - -static inline int __raw_spin_trylock(raw_spinlock_t *lock) -{ - return cris_spin_trylock((void *)&lock->slock); -} - -static inline void __raw_spin_lock(raw_spinlock_t *lock) -{ - cris_spin_lock((void *)&lock->slock); -} - -static inline void -__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) -{ - __raw_spin_lock(lock); -} - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - * - */ - -static inline int __raw_read_can_lock(raw_rwlock_t *x) -{ - return (int)(x)->lock > 0; -} - -static inline int __raw_write_can_lock(raw_rwlock_t *x) -{ - return (x)->lock == RW_LOCK_BIAS; -} - -static inline void __raw_read_lock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - while (rw->lock == 0); - rw->lock--; - __raw_spin_unlock(&rw->slock); -} - -static inline void __raw_write_lock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - while (rw->lock != RW_LOCK_BIAS); - rw->lock == 0; - __raw_spin_unlock(&rw->slock); -} - -static inline void __raw_read_unlock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - rw->lock++; - __raw_spin_unlock(&rw->slock); -} - -static inline void __raw_write_unlock(raw_rwlock_t *rw) -{ - __raw_spin_lock(&rw->slock); - while (rw->lock != RW_LOCK_BIAS); - rw->lock == RW_LOCK_BIAS; - __raw_spin_unlock(&rw->slock); -} - -static inline int __raw_read_trylock(raw_rwlock_t *rw) -{ - int ret = 0; - __raw_spin_lock(&rw->slock); - if (rw->lock != 0) { - rw->lock--; - ret = 1; - } - __raw_spin_unlock(&rw->slock); - return ret; -} - -static inline int __raw_write_trylock(raw_rwlock_t *rw) -{ - int ret = 0; - __raw_spin_lock(&rw->slock); - if (rw->lock == RW_LOCK_BIAS) { - rw->lock == 0; - ret = 1; - } - __raw_spin_unlock(&rw->slock); - return 1; -} - - -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() - -#endif /* __ASM_ARCH_SPINLOCK_H */ diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h deleted file mode 100644 index 6ca90f1f110a..000000000000 --- a/include/asm-cris/arch-v32/system.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_SYSTEM_H -#define _ASM_CRIS_ARCH_SYSTEM_H - - -/* Read the CPU version register. */ -static inline unsigned long rdvr(void) -{ - unsigned char vr; - - __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "crisv32" - -/* Read the user-mode stack pointer. */ -static inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); - return usp; -} - -/* Read the current stack pointer. */ -static inline unsigned long rdsp(void) -{ - unsigned long sp; - - __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); - return sp; -} - -/* Write the user-mode stack pointer. */ -#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) - -#define nop() __asm__ __volatile__ ("nop"); - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr)))) - -#define tas(ptr) (xchg((ptr),1)) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* Used for interrupt control. */ -#define local_save_flags(x) \ - __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); - -#define local_irq_restore(x) \ - __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); - -#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); -#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - \ - local_save_flags(flags);\ - !(flags & (1 << I_CCS_BITNR)); \ -}) - -/* Used for spinlocks, etc. */ -#define local_irq_save(x) \ - __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); - -#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h deleted file mode 100644 index d6936956a3c6..000000000000 --- a/include/asm-cris/arch-v32/thread_info.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H -#define _ASM_CRIS_ARCH_THREAD_INFO_H - -/* Return a thread_info struct. */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - - __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h deleted file mode 100644 index 2591d3c5ed9d..000000000000 --- a/include/asm-cris/arch-v32/timex.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -#include <hwregs/reg_map.h> -#include <hwregs/reg_rdwr.h> -#include <hwregs/timer_defs.h> - -/* - * The clock runs at 100MHz, we divide it by 1000000. If you change anything - * here you must check time.c as well. - */ - -#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ - -/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - -/* Convert the value in step of 10 ns to 1us without overflow: */ -#define GET_JIFFIES_USEC() \ - ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) - -extern unsigned long get_ns_in_jiffie(void); - -static inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie() / 1000; -} - -#endif - diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h deleted file mode 100644 index 4effb1253660..000000000000 --- a/include/asm-cris/arch-v32/tlb.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* - * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used - * to store the "process" it belongs to (=> fast mm context switch). The - * last page_id is never used so we can make TLB entries that never matches. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 256 -#define INVALID_PAGEID 255 -#define NO_CONTEXT -1 - -#endif /* _CRIS_ARCH_TLB_H */ diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h deleted file mode 100644 index 6b207f1b6622..000000000000 --- a/include/asm-cris/arch-v32/uaccess.h +++ /dev/null @@ -1,748 +0,0 @@ -/* - * Authors: Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *at* the faulting - * instruction for CRISv32. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" %1,[%2]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " nop\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) do { \ - int dummy_for_put_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d %M2,[%1+]\n" \ - "4: move.d %H2,[%1]\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ - : "r" (x), "1" (addr), "g" (-EFAULT), \ - "0" (err)); \ - } while (0) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" [%2],%1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) do { \ - int dummy_for_get_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d [%2+],%M1\n" \ - "4: move.d [%2],%H1\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x), \ - "=b" (dummy_for_get_user_asm_64_) \ - : "2" (addr), "g" (-EFAULT), "0" (err));\ - } while (0) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -static inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3; - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - "5: move.b [%2+],$acr\n" - "1: beq 2f\n" - " move.b $acr,[%1+]\n" - - " subq 1,%0\n" - "2: bne 1b\n" - " move.b [%2+],$acr\n" - - " sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - " nop\n" - - /* The address for a fault at the first move is trivial. - The address for a fault at the second move is that of - the preceding branch insn, since the move insn is in - its delay-slot. That address is also a branch - target. Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 5b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "acr"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address for the insn, or for the preceding branch when in a delay-slot. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=b" (to), "=b" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "acr", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - "2: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "3: addq 1,%2\n" \ - " jump 1b\n" \ - " clear.b [%0+]\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "3: addq 2,%2\n" \ - " jump 1b\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "3: addq 4,%2\n" \ - " jump 1b\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n" \ - " clear.w [%0+]\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - "10: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n" \ - " clear.b [%0+]\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - COPY \ - "10: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - COPY \ - "12: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n" \ - " clear.d [%0+]\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "2: move.b $acr,[%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "2: move.w $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 2,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "2: move.d $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "4: move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "4: move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "6: move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "6: move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "8: move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "10: move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "8: move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "10: move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "12: move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=b" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.b [%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n", \ - "3: jump 1b\n" \ - " addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n" \ - "3: clear.b [%0+]\n", \ - "4: addq 2,%1\n" \ - "5: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - CLEAR \ - "2: clear.d [%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%1\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - CLEAR \ - "4: clear.d [%0+]\n", \ - FIXUP \ - "5: addq 4,%1\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - CLEAR \ - "6: clear.d [%0+]\n", \ - FIXUP \ - "7: addq 4,%1\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - CLEAR \ - "8: clear.d [%0+]\n", \ - FIXUP \ - "9: addq 4,%1\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - CLEAR \ - "10: clear.d [%0+]\n", \ - FIXUP \ - "11: addq 4,%1\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - CLEAR \ - "12: clear.d [%0+]\n", \ - FIXUP \ - "13: addq 4,%1\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -static inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$acr\n" - " cmpq 0,$acr\n" - "0:\n" - " ble 1f\n" - " subq 1,$acr\n" - - "4: test.b [%0+]\n" - " bne 0b\n" - " cmpq 0,$acr\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $acr,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: jump 2b\n" - " clear.d %0\n" - - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 4b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "acr"); - - return res; -} - -#endif diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h deleted file mode 100644 index 0051114c63c7..000000000000 --- a/include/asm-cris/arch-v32/unistd.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)\ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __f __asm__ ("srp") = (long) arg6; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h deleted file mode 100644 index 03fa1f3c3c00..000000000000 --- a/include/asm-cris/arch-v32/user.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_USER_H -#define _ASM_CRIS_ARCH_USER_H - -/* User-mode register used for core dumps. */ - -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* R14, Stack pointer. */ - unsigned long acr; /* R15, Address calculation register. */ - unsigned long bz; /* P0, Constant zero (8-bits). */ - unsigned long vr; /* P1, Version register (8-bits). */ - unsigned long pid; /* P2, Process ID (8-bits). */ - unsigned long srs; /* P3, Support register select (8-bits). */ - unsigned long wz; /* P4, Constant zero (16-bits). */ - unsigned long exs; /* P5, Exception status. */ - unsigned long eda; /* P6, Exception data address. */ - unsigned long mof; /* P7, Multiply overflow regiter. */ - unsigned long dz; /* P8, Constant zero (32-bits). */ - unsigned long ebp; /* P9, Exception base pointer. */ - unsigned long erp; /* P10, Exception return pointer. */ - unsigned long srp; /* P11, Subroutine return pointer. */ - unsigned long nrp; /* P12, NMI return pointer. */ - unsigned long ccs; /* P13, Condition code stack. */ - unsigned long usp; /* P14, User mode stack pointer. */ - unsigned long spc; /* P15, Single step PC. */ -}; - -#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h deleted file mode 100644 index 5fc87768774a..000000000000 --- a/include/asm-cris/atomic.h +++ /dev/null @@ -1,164 +0,0 @@ -/* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */ - -#ifndef __ASM_CRIS_ATOMIC__ -#define __ASM_CRIS_ATOMIC__ - -#include <linux/compiler.h> - -#include <asm/system.h> -#include <asm/arch/atomic.h> - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -/* These should be written in asm but we do it in C for now. */ - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - v->counter += i; - cris_atomic_restore(v, flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - v->counter -= i; - cris_atomic_restore(v, flags); -} - -static inline int atomic_add_return(int i, volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = (v->counter += i); - cris_atomic_restore(v, flags); - return retval; -} - -#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) - -static inline int atomic_sub_return(int i, volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = (v->counter -= i); - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_sub_and_test(int i, volatile atomic_t *v) -{ - int retval; - unsigned long flags; - cris_atomic_save(v, flags); - retval = (v->counter -= i) == 0; - cris_atomic_restore(v, flags); - return retval; -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - (v->counter)++; - cris_atomic_restore(v, flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - cris_atomic_save(v, flags); - (v->counter)--; - cris_atomic_restore(v, flags); -} - -static inline int atomic_inc_return(volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = ++(v->counter); - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_dec_return(volatile atomic_t *v) -{ - unsigned long flags; - int retval; - cris_atomic_save(v, flags); - retval = --(v->counter); - cris_atomic_restore(v, flags); - return retval; -} -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - int retval; - unsigned long flags; - cris_atomic_save(v, flags); - retval = --(v->counter) == 0; - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_inc_and_test(volatile atomic_t *v) -{ - int retval; - unsigned long flags; - cris_atomic_save(v, flags); - retval = ++(v->counter) == 0; - cris_atomic_restore(v, flags); - return retval; -} - -static inline int atomic_cmpxchg(atomic_t *v, int old, int new) -{ - int ret; - unsigned long flags; - - cris_atomic_save(v, flags); - ret = v->counter; - if (likely(ret == old)) - v->counter = new; - cris_atomic_restore(v, flags); - return ret; -} - -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - -static inline int atomic_add_unless(atomic_t *v, int a, int u) -{ - int ret; - unsigned long flags; - - cris_atomic_save(v, flags); - ret = v->counter; - if (ret != u) - v->counter += a; - cris_atomic_restore(v, flags); - return ret != u; -} -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#include <asm-generic/atomic.h> -#endif diff --git a/include/asm-cris/auxvec.h b/include/asm-cris/auxvec.h deleted file mode 100644 index cb30b01bf19f..000000000000 --- a/include/asm-cris/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASMCRIS_AUXVEC_H -#define __ASMCRIS_AUXVEC_H - -#endif diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h deleted file mode 100644 index 015ca5445ddd..000000000000 --- a/include/asm-cris/axisflashmap.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __ASM_AXISFLASHMAP_H -#define __ASM_AXISFLASHMAP_H - -/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC - * as start, it ends with 0xFFFFFFFF */ -#define FLASH_BOOT_MAGIC 0xbeefcace -#define BOOTPARAM_OFFSET 0xc000 -/* apps/bootblocktool is used to read and write the parameters, - * and it has nothing to do with the partition table. - */ - -#define PARTITION_TABLE_OFFSET 10 -#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ - -/* The partitiontable_head is located at offset +10: */ -struct partitiontable_head { - __u16 magic; /* PARTITION_TABLE_MAGIC */ - __u16 size; /* Length of ptable block (entries + end marker) */ - __u32 checksum; /* simple longword sum, over entries + end marker */ -}; - -/* And followed by partition table entries */ -struct partitiontable_entry { - __u32 offset; /* relative to the sector the ptable is in */ - __u32 size; /* in bytes */ - __u32 checksum; /* simple longword sum */ - __u16 type; /* see type codes below */ - __u16 flags; /* bit 0: ro/rw = 1/0 */ - __u32 future0; /* 16 bytes reserved for future use */ - __u32 future1; - __u32 future2; - __u32 future3; -}; -/* ended by an end marker: */ -#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF -#define PARTITIONTABLE_END_MARKER_SIZE 4 - -#define PARTITIONTABLE_END_PAD 10 - -/* Complete structure for whole partition table */ -/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting - * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. - */ -struct partitiontable { - __u8 skip[PARTITION_TABLE_OFFSET]; - struct partitiontable_head head; - struct partitiontable_entry entries[]; -}; - -#define PARTITION_TYPE_PARAM 0x0001 -#define PARTITION_TYPE_KERNEL 0x0002 -#define PARTITION_TYPE_JFFS 0x0003 -#define PARTITION_TYPE_JFFS2 0x0000 - -#define PARTITION_FLAGS_READONLY_MASK 0x0001 -#define PARTITION_FLAGS_READONLY 0x0001 - -/* The master mtd for the entire flash. */ -extern struct mtd_info *axisflash_mtd; - -#endif diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h deleted file mode 100644 index 75ea6e096483..000000000000 --- a/include/asm-cris/bitops.h +++ /dev/null @@ -1,166 +0,0 @@ -/* asm/bitops.h for Linux/CRIS - * - * TODO: asm versions if speed is needed - * - * All bit operations return 0 if the bit was cleared before the - * operation and != 0 if it was not. - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - */ - -#ifndef _CRIS_BITOPS_H -#define _CRIS_BITOPS_H - -/* Currently this is unsuitable for consumption outside the kernel. */ -#ifdef __KERNEL__ - -#ifndef _LINUX_BITOPS_H -#error only <linux/bitops.h> can be included directly -#endif - -#include <asm/arch/bitops.h> -#include <asm/system.h> -#include <asm/atomic.h> -#include <linux/compiler.h> - -/* - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ - -#define set_bit(nr, addr) (void)test_and_set_bit(nr, addr) - -/* - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ - -#define clear_bit(nr, addr) (void)test_and_clear_bit(nr, addr) - -/* - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ - -#define change_bit(nr, addr) (void)test_and_change_bit(nr, addr) - -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ - -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned int mask, retval; - unsigned long flags; - unsigned int *adr = (unsigned int *)addr; - - adr += nr >> 5; - mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); - retval = (mask & *adr) != 0; - *adr |= mask; - cris_atomic_restore(addr, flags); - return retval; -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ - -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned int mask, retval; - unsigned long flags; - unsigned int *adr = (unsigned int *)addr; - - adr += nr >> 5; - mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); - retval = (mask & *adr) != 0; - *adr &= ~mask; - cris_atomic_restore(addr, flags); - return retval; -} - -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ - -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) -{ - unsigned int mask, retval; - unsigned long flags; - unsigned int *adr = (unsigned int *)addr; - adr += nr >> 5; - mask = 1 << (nr & 0x1f); - cris_atomic_save(addr, flags); - retval = (mask & *adr) != 0; - *adr ^= mask; - cris_atomic_restore(addr, flags); - return retval; -} - -#include <asm-generic/bitops/non-atomic.h> - -/* - * Since we define it "external", it collides with the built-in - * definition, which doesn't have the same semantics. We don't want to - * use -fno-builtin, so just hide the name ffs. - */ -#define ffs kernel_ffs - -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/fls64.h> -#include <asm-generic/bitops/hweight.h> -#include <asm-generic/bitops/find.h> -#include <asm-generic/bitops/lock.h> - -#include <asm-generic/bitops/ext2-non-atomic.h> - -#define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) -#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) - -#include <asm-generic/bitops/minix.h> -#include <asm-generic/bitops/sched.h> - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_BITOPS_H */ diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h deleted file mode 100644 index fee12d4ae683..000000000000 --- a/include/asm-cris/bug.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _CRIS_BUG_H -#define _CRIS_BUG_H -#include <asm/arch/bug.h> -#endif diff --git a/include/asm-cris/bugs.h b/include/asm-cris/bugs.h deleted file mode 100644 index c5907aac1007..000000000000 --- a/include/asm-cris/bugs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ - * - * include/asm-cris/bugs.h - * - * Copyright (C) 2001 Axis Communications AB - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -static void check_bugs(void) -{ -} - - - - diff --git a/include/asm-cris/byteorder.h b/include/asm-cris/byteorder.h deleted file mode 100644 index 0cd9db1cc888..000000000000 --- a/include/asm-cris/byteorder.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _CRIS_BYTEORDER_H -#define _CRIS_BYTEORDER_H - -#ifdef __GNUC__ - -#ifdef __KERNEL__ -#include <asm/arch/byteorder.h> - -/* defines are necessary because the other files detect the presence - * of a defined __arch_swab32, not an inline - */ -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) -#endif /* __KERNEL__ */ - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#include <linux/byteorder/little_endian.h> - -#endif - - diff --git a/include/asm-cris/cache.h b/include/asm-cris/cache.h deleted file mode 100644 index 46a3b26e205a..000000000000 --- a/include/asm-cris/cache.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include <asm/arch/cache.h> - -#endif /* _ASM_CACHE_H */ diff --git a/include/asm-cris/cacheflush.h b/include/asm-cris/cacheflush.h deleted file mode 100644 index cf60e3f69f8d..000000000000 --- a/include/asm-cris/cacheflush.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _CRIS_CACHEFLUSH_H -#define _CRIS_CACHEFLUSH_H - -/* Keep includes the same across arches. */ -#include <linux/mm.h> - -/* The cache doesn't need to be flushed when TLB entries change because - * the cache is mapped to physical memory, not virtual memory - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -int change_page_attr(struct page *page, int numpages, pgprot_t prot); - -#endif /* _CRIS_CACHEFLUSH_H */ diff --git a/include/asm-cris/checksum.h b/include/asm-cris/checksum.h deleted file mode 100644 index c6c5be62c698..000000000000 --- a/include/asm-cris/checksum.h +++ /dev/null @@ -1,83 +0,0 @@ -/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ - -#ifndef _CRIS_CHECKSUM_H -#define _CRIS_CHECKSUM_H - -#include <asm/arch/checksum.h> - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -__wsum csum_partial(const void *buff, int len, __wsum sum); - -/* - * the same as csum_partial, but copies from src while it - * checksums - * - * here even more important to align src and dst on a 32-bit (or even - * better 64-bit) boundary - */ - -__wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum); - -/* - * Fold a partial checksum into a word - */ - -static inline __sum16 csum_fold(__wsum csum) -{ - u32 sum = (__force u32)csum; - sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ - sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ - return (__force __sum16)~sum; -} - -extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, - int len, __wsum sum, - int *errptr); - -/* - * This is a version of ip_compute_csum() optimized for IP headers, - * which always checksum on 4 octet boundaries. - * - */ - -static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) -{ - return csum_fold(csum_partial(iph, ihl * 4, 0)); -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ - -static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, - unsigned short len, - unsigned short proto, - __wsum sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); -} - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ - -static inline __sum16 ip_compute_csum(const void *buff, int len) -{ - return csum_fold (csum_partial(buff, len, 0)); -} - -#endif diff --git a/include/asm-cris/cputime.h b/include/asm-cris/cputime.h deleted file mode 100644 index 4446a65656fa..000000000000 --- a/include/asm-cris/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __CRIS_CPUTIME_H -#define __CRIS_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __CRIS_CPUTIME_H */ diff --git a/include/asm-cris/current.h b/include/asm-cris/current.h deleted file mode 100644 index 5f5c0efd00be..000000000000 --- a/include/asm-cris/current.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _CRIS_CURRENT_H -#define _CRIS_CURRENT_H - -#include <linux/thread_info.h> - -struct task_struct; - -static inline struct task_struct * get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() - -#endif /* !(_CRIS_CURRENT_H) */ diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h deleted file mode 100644 index 123e19aef49d..000000000000 --- a/include/asm-cris/delay.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _CRIS_DELAY_H -#define _CRIS_DELAY_H - -/* - * Copyright (C) 1998-2002 Axis Communications AB - * - * Delay routines, using a pre-computed "loops_per_second" value. - */ - -#include <asm/arch/delay.h> - -/* Use only for very small delays ( < 1 msec). */ - -extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ - -/* May be defined by arch/delay.h. */ -#ifndef udelay -static inline void udelay(unsigned long usecs) -{ - __delay(usecs * loops_per_usec); -} -#endif - -#endif /* defined(_CRIS_DELAY_H) */ - - - diff --git a/include/asm-cris/device.h b/include/asm-cris/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-cris/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include <asm-generic/device.h> - diff --git a/include/asm-cris/div64.h b/include/asm-cris/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/include/asm-cris/div64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/div64.h> diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h deleted file mode 100644 index da8ef8e8f842..000000000000 --- a/include/asm-cris/dma-mapping.h +++ /dev/null @@ -1,170 +0,0 @@ -/* DMA mapping. Nothing tricky here, just virt_to_phys */ - -#ifndef _ASM_CRIS_DMA_MAPPING_H -#define _ASM_CRIS_DMA_MAPPING_H - -#include <linux/mm.h> -#include <linux/kernel.h> - -#include <asm/cache.h> -#include <asm/io.h> -#include <asm/scatterlist.h> - -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) - -#ifdef CONFIG_PCI -#include <asm-generic/dma-coherent.h> - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); - -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); -#else -static inline void * -dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - gfp_t flag) -{ - BUG(); - return NULL; -} - -static inline void -dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) -{ - BUG(); -} -#endif -static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - return virt_to_phys(ptr); -} - -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - printk("Map sg\n"); - return nents; -} - -static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, unsigned long offset, - size_t size, enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - return page_to_phys(page) + offset; -} - -static inline void -dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - - -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); -} - -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ -} - -static inline void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ -} - -static inline int -dma_mapping_error(struct device *dev, dma_addr_t dma_addr) -{ - return 0; -} - -static inline int -dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if(mask < 0x00ffffff) - return 0; - - return 1; -} - -static inline int -dma_set_mask(struct device *dev, u64 mask) -{ - if(!dev->dma_mask || !dma_supported(dev, mask)) - return -EIO; - - *dev->dma_mask = mask; - - return 0; -} - -static inline int -dma_get_cache_alignment(void) -{ - return (1 << INTERNODE_CACHE_SHIFT); -} - -#define dma_is_consistent(d, h) (1) - -static inline void -dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction) -{ -} - - -#endif diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h deleted file mode 100644 index 6f188dc56138..000000000000 --- a/include/asm-cris/dma.h +++ /dev/null @@ -1,21 +0,0 @@ -/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ - -#ifndef _ASM_DMA_H -#define _ASM_DMA_H - -#include <asm/arch/dma.h> - -/* it's useless on the Etrax, but unfortunately needed by the new - bootmem allocator (but this should do it for this) */ - -#define MAX_DMA_ADDRESS PAGE_OFFSET - -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - -#endif /* _ASM_DMA_H */ diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h deleted file mode 100644 index f0d17fbc81ba..000000000000 --- a/include/asm-cris/elf.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef __ASMCRIS_ELF_H -#define __ASMCRIS_ELF_H - -/* - * ELF register definitions.. - */ - -#include <asm/user.h> - -#define R_CRIS_NONE 0 -#define R_CRIS_8 1 -#define R_CRIS_16 2 -#define R_CRIS_32 3 -#define R_CRIS_8_PCREL 4 -#define R_CRIS_16_PCREL 5 -#define R_CRIS_32_PCREL 6 -#define R_CRIS_GNU_VTINHERIT 7 -#define R_CRIS_GNU_VTENTRY 8 -#define R_CRIS_COPY 9 -#define R_CRIS_GLOB_DAT 10 -#define R_CRIS_JUMP_SLOT 11 -#define R_CRIS_RELATIVE 12 -#define R_CRIS_16_GOT 13 -#define R_CRIS_32_GOT 14 -#define R_CRIS_16_GOTPLT 15 -#define R_CRIS_32_GOTPLT 16 -#define R_CRIS_32_GOTREL 17 -#define R_CRIS_32_PLT_GOTREL 18 -#define R_CRIS_32_PLT_PCREL 19 - -typedef unsigned long elf_greg_t; - -/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is - thus exposed to user-space. */ -#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -/* A placeholder; CRIS does not have any fp regs. */ -typedef unsigned long elf_fpregset_t; - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_CRIS - -#include <asm/arch/elf.h> - -/* The master for these definitions is {binutils}/include/elf/cris.h: */ -/* User symbols in this file have a leading underscore. */ -#define EF_CRIS_UNDERSCORE 0x00000001 - -/* This is a mask for different incompatible machine variants. */ -#define EF_CRIS_VARIANT_MASK 0x0000000e - -/* Variant 0; may contain v0..10 object. */ -#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 - -/* Variant 1; contains v32 object. */ -#define EF_CRIS_VARIANT_V32 0x00000002 - -/* Variant 2; contains object compatible with v32 and v10. */ -#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 -/* End of excerpt from {binutils}/include/elf/cris.h. */ - -#define USE_ELF_CORE_DUMP - -#define ELF_EXEC_PAGESIZE 8192 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -/* This yields a mask that user programs can use to figure out what - instruction set this CPU supports. This could be done in user space, - but it's not easy, and we've already done it here. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. -*/ - -#define ELF_PLATFORM (NULL) - -#define SET_PERSONALITY(ex) set_personality(PER_LINUX) - -#endif diff --git a/include/asm-cris/emergency-restart.h b/include/asm-cris/emergency-restart.h deleted file mode 100644 index 108d8c48e42e..000000000000 --- a/include/asm-cris/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-cris/errno.h b/include/asm-cris/errno.h deleted file mode 100644 index 2bf5eb5fa773..000000000000 --- a/include/asm-cris/errno.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_ERRNO_H -#define _CRIS_ERRNO_H - -#include <asm-generic/errno.h> - -#endif diff --git a/include/asm-cris/eshlibld.h b/include/asm-cris/eshlibld.h deleted file mode 100644 index 10ce36cf79a9..000000000000 --- a/include/asm-cris/eshlibld.h +++ /dev/null @@ -1,113 +0,0 @@ -/*!************************************************************************** -*! -*! FILE NAME : eshlibld.h -*! -*! DESCRIPTION: Prototypes for exported shared library functions -*! -*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit -*! (EXPORTED) -*! -*!--------------------------------------------------------------------------- -*! -*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN -*! -*!**************************************************************************/ -/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ - -#ifndef _cris_relocate_h -#define _cris_relocate_h - -/* Please note that this file is also compiled into the xsim simulator. - Try to avoid breaking its double use (only works on a little-endian - 32-bit machine such as the i386 anyway). - - Use __KERNEL__ when you're about to use kernel functions, - (which you should not do here anyway, since this file is - used by glibc). - Use defined(__KERNEL__) || defined(__elinux__) when doing - things that only makes sense on an elinux system. - Use __CRIS__ when you're about to do (really) CRIS-specific code. -*/ - -/* We have dependencies all over the place for the host system - for xsim being a linux system, so let's not pretend anything - else with #ifdef:s here until fixed. */ -#include <linux/limits.h> - -/* Maybe do sanity checking if file input. */ -#undef SANITYCHECK_RELOC - -/* Maybe output debug messages. */ -#undef RELOC_DEBUG - -/* Maybe we want to share core as well as disk space. - Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is - assumed that we want to share code when debugging (exposes more - trouble). */ -#ifndef SHARE_LIB_CORE -# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ - && !defined(CONFIG_SHARE_SHLIB_CORE) -# define SHARE_LIB_CORE 0 -# else -# define SHARE_LIB_CORE 1 -# endif /* __KERNEL__ etc */ -#endif /* SHARE_LIB_CORE */ - - -/* Main exported function; supposed to be called when the program a.out - has been read in. */ -extern int -perform_cris_aout_relocations(unsigned long text, unsigned long tlength, - unsigned long data, unsigned long dlength, - unsigned long baddr, unsigned long blength, - - /* These may be zero when there's "perfect" - position-independent code. */ - unsigned char *trel, unsigned long tsrel, - unsigned long dsrel, - - /* These will be zero at a first try, to see - if code is statically linked. Else a - second try, with the symbol table and - string table nonzero should be done. */ - unsigned char *symbols, unsigned long symlength, - unsigned char *strings, unsigned long stringlength, - - /* These will only be used when symbol table - information is present. */ - char **env, int envc, - int euid, int is_suid); - - -#ifdef RELOC_DEBUG -/* Task-specific debug stuff. */ -struct task_reloc_debug { - struct memdebug *alloclast; - unsigned long alloc_total; - unsigned long export_total; -}; -#endif /* RELOC_DEBUG */ - -#if SHARE_LIB_CORE - -/* When code (and some very specific data) is shared and not just - dynamically linked, we need to export hooks for exec beginning and - end. */ - -struct shlibdep; - -extern void -shlibmod_exit(struct shlibdep **deps); - -/* Returns 0 if failure, nonzero for ok. */ -extern int -shlibmod_fork(struct shlibdep **deps); - -#else /* ! SHARE_LIB_CORE */ -# define shlibmod_exit(x) -# define shlibmod_fork(x) 1 -#endif /* ! SHARE_LIB_CORE */ - -#endif _cris_relocate_h -/********************** END OF FILE eshlibld.h *****************************/ - diff --git a/include/asm-cris/ethernet.h b/include/asm-cris/ethernet.h deleted file mode 100644 index 4d58652c3a49..000000000000 --- a/include/asm-cris/ethernet.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * ioctl defines for ethernet driver - * - * Copyright (c) 2001 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef _CRIS_ETHERNET_H -#define _CRIS_ETHERNET_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ -#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ -#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ -#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 -#endif /* _CRIS_ETHERNET_H */ diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h deleted file mode 100644 index 38f1c8e1770c..000000000000 --- a/include/asm-cris/etraxgpio.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * The following devices are accessable using this driver using - * GPIO_MAJOR (120) and a couple of minor numbers. - * - * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/gpiog minor 3 - * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG - * g1-g7 and g25-g31 is both input and outputs but on different pins - * Also note that some bits change pins depending on what interfaces - * are enabled. - * - * For ETRAX FS (CONFIG_ETRAXFS): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction - * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction - * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction - * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * - * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction - * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction - * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/pwm0 minor 16, PWM channel 0 on PA30 - * /dev/pwm1 minor 17, PWM channel 1 on PA31 - * /dev/pwm2 minor 18, PWM channel 2 on PB26 - * - */ -#ifndef _ASM_ETRAXGPIO_H -#define _ASM_ETRAXGPIO_H - -/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ -#ifdef CONFIG_ETRAX_ARCH_V10 -#define ETRAXGPIO_IOCTYPE 43 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_G 3 -#define GPIO_MINOR_LAST 3 -#endif - -#ifdef CONFIG_ETRAXFS -#define ETRAXGPIO_IOCTYPE 43 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#define GPIO_MINOR_E 5 -#ifdef CONFIG_ETRAX_VIRTUAL_GPIO -#define GPIO_MINOR_V 6 -#define GPIO_MINOR_LAST 6 -#else -#define GPIO_MINOR_LAST 5 -#endif -#endif - -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -#define ETRAXGPIO_IOCTYPE 43 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#ifdef CONFIG_ETRAX_VIRTUAL_GPIO -#define GPIO_MINOR_V 6 -#define GPIO_MINOR_LAST 6 -#else -#define GPIO_MINOR_LAST 4 -#endif -#define GPIO_MINOR_PWM0 16 -#define GPIO_MINOR_PWM1 17 -#define GPIO_MINOR_PWM2 18 -#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 -#endif - -/* supported ioctl _IOC_NR's */ - -#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ -#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ -#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ - -/* the alarm is waited for by select() */ - -#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ -#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ -#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ - -/* LED ioctl */ -#define IO_LEDACTIVE_SET 0x7 /* set active led - * 0=off, 1=green, 2=red, 3=yellow */ - -/* GPIO direction ioctl's */ -#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ -#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, - returns mask with current inputs (obsolete) */ -#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, - returns mask with current outputs (obsolete)*/ - -/* LED ioctl extended */ -#define IO_LED_SETBIT 0xB -#define IO_LED_CLRBIT 0xC - -/* SHUTDOWN ioctl */ -#define IO_SHUTDOWN 0xD -#define IO_GET_PWR_BT 0xE - -/* Bit toggling in driver settings */ -/* bit set in low byte0 is CLK mask (0x00FF), - bit set in byte1 is DATA mask (0xFF00) - msb, data_mask[7:0] , clk_mask[7:0] - */ -#define IO_CFG_WRITE_MODE 0xF -#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ - ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) - -/* The following 4 ioctl's take a pointer as argument and handles - * 32 bit ports (port G) properly. - * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT - */ -#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ -#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ -#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, - * *arg updated with current input pins. - */ -#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, - * *arg updated with current output pins. - */ - -/* The following ioctl's are applicable to the PWM channels only */ - -#define IO_PWM_SET_MODE 0x20 - -enum io_pwm_mode { - PWM_OFF = 0, /* disabled, deallocated */ - PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ - PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ - PWM_VARFREQ = 3 /* individually configurable high/low periods */ -}; - -struct io_pwm_set_mode { - enum io_pwm_mode mode; -}; - -/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns - * from 10ns (value = 0) to 81920ns (value = 8191) - * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to - * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty - * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) - */ -#define IO_PWM_SET_PERIOD 0x21 - -struct io_pwm_set_period { - unsigned int lo; /* 0..8191 */ - unsigned int hi; /* 0..8191 */ -}; - -/* Only for modes PWM_STANDARD and PWM_FAST. - * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from - * 0 (value = 0) to 255/256 (value = 255). - * For PWM_FAST, set duty cycle of PWM output signal from - * 0% (value = 0) to 100% (value = 255). Output signal in this mode - * is a 10ns pulse surrounded by a high or low level depending on duty - * cycle (except for 0% and 100% which result in a constant output). - * Resulting output frequency varies from 50 MHz at 50% duty cycle, - * down to 390 kHz at min/max duty cycle. - */ -#define IO_PWM_SET_DUTY 0x22 - -struct io_pwm_set_duty { - int duty; /* 0..255 */ -}; - -#endif diff --git a/include/asm-cris/etraxi2c.h b/include/asm-cris/etraxi2c.h deleted file mode 100644 index e369a7620893..000000000000 --- a/include/asm-cris/etraxi2c.h +++ /dev/null @@ -1,36 +0,0 @@ -/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ - -#ifndef _LINUX_ETRAXI2C_H -#define _LINUX_ETRAXI2C_H - -/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ - -#define ETRAXI2C_IOCTYPE 44 - -/* supported ioctl _IOC_NR's */ - -/* in write operations, the argument contains both i2c - * slave, register and value. - */ - -#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) -#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) - -#define I2C_ARGSLAVE(arg) ((arg) >> 16) -#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) -#define I2C_ARGVALUE(arg) ((arg) & 0xff) - -#define I2C_WRITEREG 0x1 /* write to an i2c register */ -#define I2C_READREG 0x2 /* read from an i2c register */ - -/* -EXAMPLE usage: - - i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); - ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); - - i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); - val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); - -*/ -#endif diff --git a/include/asm-cris/fasttimer.h b/include/asm-cris/fasttimer.h deleted file mode 100644 index 8f8a8d6c9653..000000000000 --- a/include/asm-cris/fasttimer.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * linux/include/asm-cris/fasttimer.h - * - * Fast timers for ETRAX100LX - * Copyright (C) 2000-2007 Axis Communications AB - */ -#include <linux/time.h> /* struct timeval */ -#include <linux/timex.h> - -#ifdef CONFIG_ETRAX_FAST_TIMER - -typedef void fast_timer_function_type(unsigned long); - -struct fasttime_t { - unsigned long tv_jiff; /* jiffies */ - unsigned long tv_usec; /* microseconds */ -}; - -struct fast_timer{ /* Close to timer_list */ - struct fast_timer *next; - struct fast_timer *prev; - struct fasttime_t tv_set; - struct fasttime_t tv_expires; - unsigned long delay_us; - fast_timer_function_type *function; - unsigned long data; - const char *name; -}; - -extern struct fast_timer *fast_timer_list; - -void start_one_shot_timer(struct fast_timer *t, - fast_timer_function_type *function, - unsigned long data, - unsigned long delay_us, - const char *name); - -int del_fast_timer(struct fast_timer * t); -/* return 1 if deleted */ - - -void schedule_usleep(unsigned long us); - - -int fast_timer_init(void); - -#endif diff --git a/include/asm-cris/fb.h b/include/asm-cris/fb.h deleted file mode 100644 index c7df38030992..000000000000 --- a/include/asm-cris/fb.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ -#include <linux/fb.h> - -#define fb_pgprotect(...) do {} while (0) - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ diff --git a/include/asm-cris/fcntl.h b/include/asm-cris/fcntl.h deleted file mode 100644 index 46ab12db5739..000000000000 --- a/include/asm-cris/fcntl.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/fcntl.h> diff --git a/include/asm-cris/futex.h b/include/asm-cris/futex.h deleted file mode 100644 index 6a332a9f099c..000000000000 --- a/include/asm-cris/futex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H - -#include <asm-generic/futex.h> - -#endif diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h deleted file mode 100644 index 74178adeb1cd..000000000000 --- a/include/asm-cris/hardirq.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __ASM_HARDIRQ_H -#define __ASM_HARDIRQ_H - -#include <asm/irq.h> -#include <linux/threads.h> -#include <linux/cache.h> - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ - -void ack_bad_irq(unsigned int irq); - -#define HARDIRQ_BITS 8 - -/* - * The hardirq mask has to be large enough to have - * space for potentially all IRQ sources in the system - * nesting on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -#endif /* __ASM_HARDIRQ_H */ diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h deleted file mode 100644 index 298066020af2..000000000000 --- a/include/asm-cris/hw_irq.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -#endif - diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h deleted file mode 100644 index b87ce63f531f..000000000000 --- a/include/asm-cris/io.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef _ASM_CRIS_IO_H -#define _ASM_CRIS_IO_H - -#include <asm/page.h> /* for __va, __pa */ -#include <asm/arch/io.h> -#include <linux/kernel.h> - -struct cris_io_operations -{ - u32 (*read_mem)(void *addr, int size); - void (*write_mem)(u32 val, int size, void *addr); - u32 (*read_io)(u32 port, void *addr, int size, int count); - void (*write_io)(u32 port, void *addr, int size, int count); -}; - -#ifdef CONFIG_PCI -extern struct cris_io_operations *cris_iops; -#else -#define cris_iops ((struct cris_io_operations*)NULL) -#endif - -/* - * Change virtual addresses to physical addresses and vv. - */ - -static inline unsigned long virt_to_phys(volatile void * address) -{ - return __pa(address); -} - -static inline void * phys_to_virt(unsigned long address) -{ - return __va(address); -} - -extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); -extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); - -static inline void __iomem * ioremap (unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, 0); -} - -extern void iounmap(volatile void * __iomem addr); - -extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); - -/* - * IO bus memory addresses are also 1:1 with the physical address - */ -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt - -/* - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the CRIS architecture, we just read/write the - * memory location directly. - */ -#ifdef CONFIG_PCI -#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) -#else -#define PCI_SPACE(x) 0 -#endif -static inline unsigned char readb(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 1); - else - return *(volatile unsigned char __force *) addr; -} -static inline unsigned short readw(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 2); - else - return *(volatile unsigned short __force *) addr; -} -static inline unsigned int readl(const volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - return cris_iops->read_mem((void*)addr, 4); - else - return *(volatile unsigned int __force *) addr; -} -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -static inline void writeb(unsigned char b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 1, (void*)addr); - else - *(volatile unsigned char __force *) addr = b; -} -static inline void writew(unsigned short b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 2, (void*)addr); - else - *(volatile unsigned short __force *) addr = b; -} -static inline void writel(unsigned int b, volatile void __iomem *addr) -{ - if (PCI_SPACE(addr) && cris_iops) - cris_iops->write_mem(b, 4, (void*)addr); - else - *(volatile unsigned int __force *) addr = b; -} -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define mmiowb() - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - - -/* I/O port access. Normally there is no I/O space on CRIS but when - * Cardbus/PCI is enabled the request is passed through the bridge. - */ - -#define IO_SPACE_LIMIT 0xffff -#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) -#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) -#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) -#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) -#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) -#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) -#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1) -#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1) -#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1) -#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count) -#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count) -#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count) - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#endif diff --git a/include/asm-cris/ioctl.h b/include/asm-cris/ioctl.h deleted file mode 100644 index b279fe06dfe5..000000000000 --- a/include/asm-cris/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ioctl.h> diff --git a/include/asm-cris/ioctls.h b/include/asm-cris/ioctls.h deleted file mode 100644 index 4f4e52531fa0..000000000000 --- a/include/asm-cris/ioctls.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef __ARCH_CRIS_IOCTLS_H__ -#define __ARCH_CRIS_IOCTLS_H__ - -/* verbatim copy of asm-i386/ioctls.h */ - -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ -#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ -#define FIOQSIZE 0x5460 - -#define TIOCSERSETRS485 0x5461 /* enable rs-485 */ -#define TIOCSERWRRS485 0x5462 /* write rs-485 */ - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -#endif diff --git a/include/asm-cris/ipcbuf.h b/include/asm-cris/ipcbuf.h deleted file mode 100644 index 8b0c18b02844..000000000000 --- a/include/asm-cris/ipcbuf.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __CRIS_IPCBUF_H__ -#define __CRIS_IPCBUF_H__ - -/* - * The user_ipc_perm structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit mode_t and seq - * - 2 miscellaneous 32-bit values - */ - -struct ipc64_perm -{ - __kernel_key_t key; - __kernel_uid32_t uid; - __kernel_gid32_t gid; - __kernel_uid32_t cuid; - __kernel_gid32_t cgid; - __kernel_mode_t mode; - unsigned short __pad1; - unsigned short seq; - unsigned short __pad2; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* __CRIS_IPCBUF_H__ */ diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h deleted file mode 100644 index 998cce9f3200..000000000000 --- a/include/asm-cris/irq.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -#include <asm/arch/irq.h> - -static inline int irq_canonicalize(int irq) -{ - return irq; -} - -#endif /* _ASM_IRQ_H */ - - diff --git a/include/asm-cris/irq_regs.h b/include/asm-cris/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-cris/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/irq_regs.h> diff --git a/include/asm-cris/kdebug.h b/include/asm-cris/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-cris/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/kdebug.h> diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h deleted file mode 100644 index 492988cb9077..000000000000 --- a/include/asm-cris/kmap_types.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - -/* Dummy header just to define km_type. None of this - * is actually used on cris. - */ - -enum km_type { - KM_BOUNCE_READ, - KM_SKB_SUNRPC_DATA, - KM_SKB_DATA_SOFTIRQ, - KM_USER0, - KM_USER1, - KM_BIO_SRC_IRQ, - KM_BIO_DST_IRQ, - KM_PTE0, - KM_PTE1, - KM_IRQ0, - KM_IRQ1, - KM_SOFTIRQ0, - KM_SOFTIRQ1, - KM_TYPE_NR -}; - -#endif diff --git a/include/asm-cris/linkage.h b/include/asm-cris/linkage.h deleted file mode 100644 index 291c2d01c44f..000000000000 --- a/include/asm-cris/linkage.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -/* Nothing to see here... */ - -#endif diff --git a/include/asm-cris/local.h b/include/asm-cris/local.h deleted file mode 100644 index c11c530f74d0..000000000000 --- a/include/asm-cris/local.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/local.h> diff --git a/include/asm-cris/mman.h b/include/asm-cris/mman.h deleted file mode 100644 index 1c35e1b66b46..000000000000 --- a/include/asm-cris/mman.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __CRIS_MMAN_H__ -#define __CRIS_MMAN_H__ - -/* verbatim copy of asm-i386/ version */ - -#include <asm-generic/mman.h> - -#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -#define MAP_LOCKED 0x2000 /* pages are locked */ -#define MAP_NORESERVE 0x4000 /* don't check for reservations */ -#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ - -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ - -#endif /* __CRIS_MMAN_H__ */ diff --git a/include/asm-cris/mmu.h b/include/asm-cris/mmu.h deleted file mode 100644 index c40a1bcad06c..000000000000 --- a/include/asm-cris/mmu.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * CRIS MMU constants and PTE layout - */ - -#ifndef _CRIS_MMU_H -#define _CRIS_MMU_H - -#include <asm/arch/mmu.h> - -#endif diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h deleted file mode 100644 index 72ba08dcfd18..000000000000 --- a/include/asm-cris/mmu_context.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __CRIS_MMU_CONTEXT_H -#define __CRIS_MMU_CONTEXT_H - -#include <asm-generic/mm_hooks.h> - -extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); -extern void get_mmu_context(struct mm_struct *mm); -extern void destroy_context(struct mm_struct *mm); -extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk); - -#define deactivate_mm(tsk,mm) do { } while (0) - -#define activate_mm(prev,next) switch_mm((prev),(next),NULL) - -/* current active pgd - this is similar to other processors pgd - * registers like cr3 on the i386 - */ - -extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */ - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -#endif diff --git a/include/asm-cris/module.h b/include/asm-cris/module.h deleted file mode 100644 index 7ee72311bd78..000000000000 --- a/include/asm-cris/module.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_CRIS_MODULE_H -#define _ASM_CRIS_MODULE_H -/* cris is simple */ -struct mod_arch_specific { }; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr -#endif /* _ASM_CRIS_MODULE_H */ diff --git a/include/asm-cris/msgbuf.h b/include/asm-cris/msgbuf.h deleted file mode 100644 index ada63df1d574..000000000000 --- a/include/asm-cris/msgbuf.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _CRIS_MSGBUF_H -#define _CRIS_MSGBUF_H - -/* verbatim copy of asm-i386 version */ - -/* - * The msqid64_ds structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _CRIS_MSGBUF_H */ diff --git a/include/asm-cris/mutex.h b/include/asm-cris/mutex.h deleted file mode 100644 index 458c1f7fbc18..000000000000 --- a/include/asm-cris/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include <asm-generic/mutex-dec.h> diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h deleted file mode 100644 index d19272ba6b69..000000000000 --- a/include/asm-cris/page.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef _CRIS_PAGE_H -#define _CRIS_PAGE_H - -#include <asm/arch/page.h> -#include <linux/const.h> - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 13 -#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) - -#define clear_user_page(page, vaddr, pg) clear_page(page) -#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) - -#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ - alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) -#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE - -/* - * These are used to make use of C type-checking.. - */ -#ifndef __ASSEMBLY__ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; -#endif - -#define pte_val(x) ((x).pte) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ -/* for that before indexing into the page table starting at mem_map */ -#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) -#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) - -/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so - * we can let the map start there. notice that we subtract PAGE_OFFSET because - * we start our mem_map there - in other ports they map mem_map physically and - * use __pa instead. in our system both the physical and virtual address of DRAM - * is too high to let mem_map start at 0, so we do it this way instead (similar - * to arm and m68k I think) - */ - -#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) -#define VALID_PAGE(page) (((page) - mem_map) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) - -/* convert a page (based on mem_map and forward) to a physical address - * do this by figuring out the virtual address and then use __pa - */ - -#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) - -#ifndef __ASSEMBLY__ - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#include <asm-generic/memory_model.h> -#include <asm-generic/page.h> - -#endif /* _CRIS_PAGE_H */ - diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h deleted file mode 100644 index 0e47994e40be..000000000000 --- a/include/asm-cris/param.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _ASMCRIS_PARAM_H -#define _ASMCRIS_PARAM_H - -/* Currently we assume that HZ=100 is good for CRIS. */ -#ifdef __KERNEL__ -# define HZ CONFIG_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#endif - -#ifndef HZ -#define HZ 100 -#endif - -#define EXEC_PAGESIZE 8192 - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ - -#endif diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h deleted file mode 100644 index 730ce40fdd0f..000000000000 --- a/include/asm-cris/pci.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef __ASM_CRIS_PCI_H -#define __ASM_CRIS_PCI_H - - -#ifdef __KERNEL__ -#include <linux/mm.h> /* for struct page */ - -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -#define pcibios_assign_all_busses(void) 1 - -extern unsigned long pci_mem_start; -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -#define PCIBIOS_MIN_CARDBUS_IO 0x4000 - -void pcibios_config_init(void); -struct pci_bus * pcibios_scan_root(int bus); -int pcibios_assign_resources(void); - -void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); -struct irq_routing_table *pcibios_get_irq_routing_table(void); -int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); - -/* Dynamic DMA mapping stuff. - * i386 has everything mapped statically. - */ - -#include <linux/types.h> -#include <linux/slab.h> -#include <asm/scatterlist.h> -#include <linux/string.h> -#include <asm/io.h> - -struct pci_dev; - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#define HAVE_PCI_MMAP -extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine); - - -#endif /* __KERNEL__ */ - -/* implement the pci_ DMA API in terms of the generic device dma_ one */ -#include <asm-generic/pci-dma-compat.h> - -/* generic pci stuff */ -#include <asm-generic/pci.h> - -#endif /* __ASM_CRIS_PCI_H */ diff --git a/include/asm-cris/percpu.h b/include/asm-cris/percpu.h deleted file mode 100644 index 6db9b43cf80a..000000000000 --- a/include/asm-cris/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_PERCPU_H -#define _CRIS_PERCPU_H - -#include <asm-generic/percpu.h> - -#endif /* _CRIS_PERCPU_H */ diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h deleted file mode 100644 index a1ba761d0573..000000000000 --- a/include/asm-cris/pgalloc.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef _CRIS_PGALLOC_H -#define _CRIS_PGALLOC_H - -#include <linux/threads.h> -#include <linux/mm.h> - -#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) -#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) -#define pmd_pgtable(pmd) pmd_page(pmd) - -/* - * Allocate and free page tables. - */ - -static inline pgd_t *pgd_alloc (struct mm_struct *mm) -{ - return (pgd_t *)get_zeroed_page(GFP_KERNEL); -} - -static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - free_page((unsigned long)pgd); -} - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); - return pte; -} - -static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - struct page *pte; - pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); - pgtable_page_ctor(pte); - return pte; -} - -static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_page((unsigned long)pte); -} - -static inline void pte_free(struct mm_struct *mm, pgtable_t pte) -{ - pgtable_page_dtor(pte); - __free_page(pte); -} - -#define __pte_free_tlb(tlb,pte) \ -do { \ - pgtable_page_dtor(pte); \ - tlb_remove_page((tlb), pte); \ -} while (0) - -#define check_pgt_cache() do { } while (0) - -#endif diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h deleted file mode 100644 index 829e7a7d9fb9..000000000000 --- a/include/asm-cris/pgtable.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * CRIS pgtable.h - macros and functions to manipulate page tables. - */ - -#ifndef _CRIS_PGTABLE_H -#define _CRIS_PGTABLE_H - -#include <asm/page.h> -#include <asm-generic/pgtable-nopmd.h> - -#ifndef __ASSEMBLY__ -#include <linux/sched.h> -#include <asm/mmu.h> -#endif -#include <asm/arch/pgtable.h> - -/* - * The Linux memory management assumes a three-level page table setup. On - * CRIS, we use that, but "fold" the mid level into the top-level page - * table. Since the MMU TLB is software loaded through an interrupt, it - * supports any page table structure, so we could have used a three-level - * setup, but for the amounts of memory we normally use, a two-level is - * probably more efficient. - * - * This file contains the functions and defines necessary to modify and use - * the CRIS page table tree. - */ -#ifndef __ASSEMBLY__ -extern void paging_init(void); -#endif - -/* Certain architectures need to do special things when pte's - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - -/* - * (pmds are folded into pgds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) -#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) - -/* PGDIR_SHIFT determines the size of the area a second-level page table can - * map. It is equal to the page size times the number of PTE's that fit in - * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. - */ - -#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * entries per page directory level: we use a two-level, so - * we don't really have any PMD directory physically. - * pointers are 4 bytes so we can use the page size and - * divide it by 4 (shift by 2). - */ -#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) -#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) - -/* calculate how many PGD entries a user-level program can use - * the first mappable virtual address is 0 - * (TASK_SIZE is the maximum virtual address space) - */ - -#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 - -/* zero page used for uninitialized stuff */ -#ifndef __ASSEMBLY__ -extern unsigned long empty_zero_page; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) -#endif - -/* number of bits that fit into a memory pointer */ -#define BITS_PER_PTR (8*sizeof(unsigned long)) - -/* to align the pointer to a pointer address */ -#define PTR_MASK (~(sizeof(void*)-1)) - -/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ -/* 64-bit machines, beware! SRB. */ -#define SIZEOF_PTR_LOG2 2 - -/* to find an entry in a page-table */ -#define PAGE_PTR(address) \ -((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) - -/* to set the page-dir */ -#define SET_PAGE_DIR(tsk,pgdir) - -#define pte_none(x) (!pte_val(x)) -#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) -#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) - -#define pmd_none(x) (!pmd_val(x)) -/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad - * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. - */ -#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) -#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) -#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) - -#ifndef __ASSEMBLY__ - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ - -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } -static inline int pte_special(pte_t pte) { return 0; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkold(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) |= _PAGE_WRITE; - if (pte_val(pte) & _PAGE_MODIFIED) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkdirty(pte_t pte) -{ - pte_val(pte) |= _PAGE_MODIFIED; - if (pte_val(pte) & _PAGE_WRITE) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - { - pte_val(pte) |= _PAGE_SILENT_READ; - if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == - (_PAGE_WRITE | _PAGE_MODIFIED)) - pte_val(pte) |= _PAGE_SILENT_WRITE; - } - return pte; -} -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ - -/* What actually goes as arguments to the various functions is less than - * obvious, but a rule of thumb is that struct page's goes as struct page *, - * really physical DRAM addresses are unsigned long's, and DRAM "virtual" - * addresses (the 0xc0xxxxxx's) goes as void *'s. - */ - -static inline pte_t __mk_pte(void * page, pgprot_t pgprot) -{ - pte_t pte; - /* the PTE needs a physical address */ - pte_val(pte) = __pa(page) | pgprot_val(pgprot); - return pte; -} - -#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) - -#define mk_pte_phys(physpage, pgprot) \ -({ \ - pte_t __pte; \ - \ - pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ - __pte; \ -}) - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } - - -/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval - * __pte_page(pte_val) refers to the "virtual" DRAM interval - * pte_pagenr refers to the page-number counted starting from the virtual DRAM start - */ - -static inline unsigned long __pte_page(pte_t pte) -{ - /* the PTE contains a physical address */ - return (unsigned long)__va(pte_val(pte) & PAGE_MASK); -} - -#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) - -/* permanent address of a page */ - -#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) -#define pte_page(pte) (mem_map+pte_pagenr(pte)) - -/* only the pte's themselves need to point to physical DRAM (see above) - * the pagetable links are purely handled within the kernel SW and thus - * don't need the __pa and __va transformations. - */ - -static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) -{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } - -#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) -#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) - -/* to find an entry in a page-table-directory. */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) - -/* to find an entry in a page-table-directory */ -static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address) -{ - return mm->pgd + pgd_index(address); -} - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) - -#define pte_unmap(pte) do { } while (0) -#define pte_unmap_nested(pte) do { } while (0) -#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) - - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ - -/* - * CRIS doesn't have any external MMU info: the kernel page - * tables contain all the necessary information. - * - * Actually I am not sure on what this could be used for. - */ -static inline void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ -} - -/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ -/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ - -#define __swp_type(x) (((x).val >> 5) & 0x7f) -#define __swp_offset(x) ((x).val >> 12) -#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -#define kern_addr_valid(addr) (1) - -#include <asm-generic/pgtable.h> - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -#define pte_to_pgoff(x) (pte_val(x) >> 6) -#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) - -typedef pte_t *pte_addr_t; - -#endif /* __ASSEMBLY__ */ -#endif /* _CRIS_PGTABLE_H */ diff --git a/include/asm-cris/poll.h b/include/asm-cris/poll.h deleted file mode 100644 index c98509d3149e..000000000000 --- a/include/asm-cris/poll.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/poll.h> diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h deleted file mode 100644 index ce3fb25a460b..000000000000 --- a/include/asm-cris/posix_types.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ -/* I guess we should write these in assembler because they are used often. */ - -#ifndef __ARCH_CRIS_POSIX_TYPES_H -#define __ARCH_CRIS_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef __SIZE_TYPE__ __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#ifdef __KERNEL__ - -#undef __FD_SET -#define __FD_SET(fd,fdsetp) set_bit(fd, (void *)(fdsetp)) - -#undef __FD_CLR -#define __FD_CLR(fd,fdsetp) clear_bit(fd, (void *)(fdsetp)) - -#undef __FD_ISSET -#define __FD_ISSET(fd,fdsetp) test_bit(fd, (void *)(fdsetp)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) memset((void *)(fdsetp), 0, __FDSET_LONGS << 2) - -#endif /* __KERNEL__ */ - -#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h deleted file mode 100644 index cdc0c1dce6be..000000000000 --- a/include/asm-cris/processor.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * include/asm-cris/processor.h - * - * Copyright (C) 2000, 2001 Axis Communications AB - * - * Authors: Bjorn Wesen Initial version - * - */ - -#ifndef __ASM_CRIS_PROCESSOR_H -#define __ASM_CRIS_PROCESSOR_H - -#include <asm/system.h> -#include <asm/page.h> -#include <asm/ptrace.h> -#include <asm/arch/processor.h> - -struct task_struct; - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) - -/* THREAD_SIZE is the size of the task_struct/kernel_stack combo. - * normally, the stack is found by doing something like p + THREAD_SIZE - * in CRIS, a page is 8192 bytes, which seems like a sane size - */ - -#define THREAD_SIZE PAGE_SIZE -#define KERNEL_STACK_SIZE PAGE_SIZE - -/* - * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. - * This macro allows us to find those regs for a task. - * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while - * we're in the kernel, won't affect this - only the first user->kernel transition - * registers are reached by this. - */ - -#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) - -/* - * Dito but for the currently running task - */ - -#define task_pt_regs(task) user_regs(task_thread_info(task)) -#define current_regs() task_pt_regs(current) - -static inline void prepare_to_copy(struct task_struct *tsk) -{ -} - -extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) - -extern unsigned long thread_saved_pc(struct task_struct *tsk); - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ - /* Nothing needs to be done. */ -} - -#define init_stack (init_thread_union.stack) - -#define cpu_relax() barrier() - -#endif /* __ASM_CRIS_PROCESSOR_H */ diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h deleted file mode 100644 index d910925e3174..000000000000 --- a/include/asm-cris/ptrace.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _CRIS_PTRACE_H -#define _CRIS_PTRACE_H - -#include <asm/arch/ptrace.h> - -#ifdef __KERNEL__ - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 - -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_PTRACE_H */ diff --git a/include/asm-cris/resource.h b/include/asm-cris/resource.h deleted file mode 100644 index b5d29448de4e..000000000000 --- a/include/asm-cris/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_RESOURCE_H -#define _CRIS_RESOURCE_H - -#include <asm-generic/resource.h> - -#endif diff --git a/include/asm-cris/rs485.h b/include/asm-cris/rs485.h deleted file mode 100644 index c331c51b0c2b..000000000000 --- a/include/asm-cris/rs485.h +++ /dev/null @@ -1,20 +0,0 @@ -/* RS-485 structures */ - -/* RS-485 support */ -/* Used with ioctl() TIOCSERSETRS485 */ -struct rs485_control { - unsigned short rts_on_send; - unsigned short rts_after_sent; - unsigned long delay_rts_before_send; - unsigned short enabled; -#ifdef __KERNEL__ - int disable_serial_loopback; -#endif -}; - -/* Used with ioctl() TIOCSERWRRS485 */ -struct rs485_write { - unsigned short outc_size; - unsigned char *outc; -}; - diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h deleted file mode 100644 index 17d3019529e1..000000000000 --- a/include/asm-cris/rtc.h +++ /dev/null @@ -1,107 +0,0 @@ - -#ifndef __RTC_H__ -#define __RTC_H__ - -#ifdef CONFIG_ETRAX_DS1302 - /* Dallas DS1302 clock/calendar register numbers. */ -# define RTC_SECONDS 0 -# define RTC_MINUTES 1 -# define RTC_HOURS 2 -# define RTC_DAY_OF_MONTH 3 -# define RTC_MONTH 4 -# define RTC_WEEKDAY 5 -# define RTC_YEAR 6 -# define RTC_CONTROL 7 - - /* Bits in CONTROL register. */ -# define RTC_CONTROL_WRITEPROTECT 0x80 -# define RTC_TRICKLECHARGER 8 - - /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ -# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ -# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ -# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ -# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ -# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ -# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ -# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ - -#elif defined(CONFIG_ETRAX_PCF8563) - /* I2C bus slave registers. */ -# define RTC_I2C_READ 0xa3 -# define RTC_I2C_WRITE 0xa2 - - /* Phillips PCF8563 registers. */ -# define RTC_CONTROL1 0x00 /* Control/Status register 1. */ -# define RTC_CONTROL2 0x01 /* Control/Status register 2. */ -# define RTC_CLOCKOUT_FREQ 0x0d /* CLKOUT frequency. */ -# define RTC_TIMER_CONTROL 0x0e /* Timer control. */ -# define RTC_TIMER_CNTDOWN 0x0f /* Timer countdown. */ - - /* BCD encoded clock registers. */ -# define RTC_SECONDS 0x02 -# define RTC_MINUTES 0x03 -# define RTC_HOURS 0x04 -# define RTC_DAY_OF_MONTH 0x05 -# define RTC_WEEKDAY 0x06 /* Not coded in BCD! */ -# define RTC_MONTH 0x07 -# define RTC_YEAR 0x08 -# define RTC_MINUTE_ALARM 0x09 -# define RTC_HOUR_ALARM 0x0a -# define RTC_DAY_ALARM 0x0b -# define RTC_WEEKDAY_ALARM 0x0c - -#endif - -#ifdef CONFIG_ETRAX_DS1302 -extern unsigned char ds1302_readreg(int reg); -extern void ds1302_writereg(int reg, unsigned char val); -extern int ds1302_init(void); -# define CMOS_READ(x) ds1302_readreg(x) -# define CMOS_WRITE(val,reg) ds1302_writereg(reg,val) -# define RTC_INIT() ds1302_init() -#elif defined(CONFIG_ETRAX_PCF8563) -extern unsigned char pcf8563_readreg(int reg); -extern void pcf8563_writereg(int reg, unsigned char val); -extern int pcf8563_init(void); -# define CMOS_READ(x) pcf8563_readreg(x) -# define CMOS_WRITE(val,reg) pcf8563_writereg(reg,val) -# define RTC_INIT() pcf8563_init() -#else - /* No RTC configured so we shouldn't try to access any. */ -# define CMOS_READ(x) 42 -# define CMOS_WRITE(x,y) -# define RTC_INIT() (-1) -#endif - -/* - * The struct used to pass data via the following ioctl. Similar to the - * struct tm in <time.h>, but it needs to be here so that the kernel - * source is self contained, allowing cross-compiles, etc. etc. - */ -struct rtc_time { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; -}; - -/* ioctl() calls that are permitted to the /dev/rtc interface. */ -#define RTC_MAGIC 'p' -/* Read RTC time. */ -#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) -/* Set RTC time. */ -#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) -#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) -/* Voltage low detector */ -#define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int) -/* Clear voltage low information */ -#define RTC_VL_CLR _IO(RTC_MAGIC, 0x14) -#define RTC_MAX_IOCTL 0x14 - -#endif /* __RTC_H__ */ diff --git a/include/asm-cris/scatterlist.h b/include/asm-cris/scatterlist.h deleted file mode 100644 index faff53ad1f96..000000000000 --- a/include/asm-cris/scatterlist.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_CRIS_SCATTERLIST_H -#define __ASM_CRIS_SCATTERLIST_H - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - char * address; /* Location data is to be transferred to */ - unsigned int length; - - /* The following is i386 highmem junk - not used by us */ - unsigned long page_link; - unsigned int offset;/* for highmem, page offset */ - -}; - -#define sg_dma_address(sg) ((sg)->address) -#define sg_dma_len(sg) ((sg)->length) -/* i386 junk */ - -#define ISA_DMA_THRESHOLD (0x1fffffff) - -#endif /* !(__ASM_CRIS_SCATTERLIST_H) */ diff --git a/include/asm-cris/sections.h b/include/asm-cris/sections.h deleted file mode 100644 index 2c998ce8967b..000000000000 --- a/include/asm-cris/sections.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _CRIS_SECTIONS_H -#define _CRIS_SECTIONS_H - -/* nothing to see, move along */ -#include <asm-generic/sections.h> - -#endif diff --git a/include/asm-cris/segment.h b/include/asm-cris/segment.h deleted file mode 100644 index c067513beaaf..000000000000 --- a/include/asm-cris/segment.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#endif diff --git a/include/asm-cris/sembuf.h b/include/asm-cris/sembuf.h deleted file mode 100644 index 7fed9843796d..000000000000 --- a/include/asm-cris/sembuf.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _CRIS_SEMBUF_H -#define _CRIS_SEMBUF_H - -/* - * The semid64_ds structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _CRIS_SEMBUF_H */ diff --git a/include/asm-cris/setup.h b/include/asm-cris/setup.h deleted file mode 100644 index b90728652d1a..000000000000 --- a/include/asm-cris/setup.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_SETUP_H -#define _CRIS_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -#endif diff --git a/include/asm-cris/shmbuf.h b/include/asm-cris/shmbuf.h deleted file mode 100644 index 3239e3f000e8..000000000000 --- a/include/asm-cris/shmbuf.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _CRIS_SHMBUF_H -#define _CRIS_SHMBUF_H - -/* - * The shmid64_ds structure for CRIS architecture (same as for i386) - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _CRIS_SHMBUF_H */ diff --git a/include/asm-cris/shmparam.h b/include/asm-cris/shmparam.h deleted file mode 100644 index d29d12270687..000000000000 --- a/include/asm-cris/shmparam.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASM_CRIS_SHMPARAM_H -#define _ASM_CRIS_SHMPARAM_H - -/* same as asm-i386/ version.. */ - -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _ASM_CRIS_SHMPARAM_H */ diff --git a/include/asm-cris/sigcontext.h b/include/asm-cris/sigcontext.h deleted file mode 100644 index a1d634e120df..000000000000 --- a/include/asm-cris/sigcontext.h +++ /dev/null @@ -1,24 +0,0 @@ -/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef _ASM_CRIS_SIGCONTEXT_H -#define _ASM_CRIS_SIGCONTEXT_H - -#include <asm/ptrace.h> - -/* This struct is saved by setup_frame in signal.c, to keep the current context while - a signal handler is executed. It's restored by sys_sigreturn. - - To keep things simple, we use pt_regs here even though normally you just specify - the list of regs to save. Then we can use copy_from_user on the entire regs instead - of a bunch of get_user's as well... - -*/ - -struct sigcontext { - struct pt_regs regs; /* needs to be first */ - unsigned long oldmask; - unsigned long usp; /* usp before stacking this gunk on it */ -}; - -#endif - diff --git a/include/asm-cris/siginfo.h b/include/asm-cris/siginfo.h deleted file mode 100644 index c1cd6d16928b..000000000000 --- a/include/asm-cris/siginfo.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_SIGINFO_H -#define _CRIS_SIGINFO_H - -#include <asm-generic/siginfo.h> - -#endif diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h deleted file mode 100644 index 349ae682b568..000000000000 --- a/include/asm-cris/signal.h +++ /dev/null @@ -1,163 +0,0 @@ -#ifndef _ASM_CRIS_SIGNAL_H -#define _ASM_CRIS_SIGNAL_H - -#include <linux/types.h> - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ - -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include <asm-generic/signal.h> - -#ifdef __KERNEL__ -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer)(void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ -#include <asm/sigcontext.h> - -/* here we could define asm-optimized sigaddset, sigdelset etc. operations. - * if we don't, generic ones are used from linux/signal.h - */ -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h deleted file mode 100644 index dba33aba3e95..000000000000 --- a/include/asm-cris/smp.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_SMP_H -#define __ASM_SMP_H - -#include <linux/cpumask.h> - -extern cpumask_t phys_cpu_present_map; -extern cpumask_t cpu_possible_map; - -#define raw_smp_processor_id() (current_thread_info()->cpu) - -#endif diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h deleted file mode 100644 index 9df0ca82f5de..000000000000 --- a/include/asm-cris/socket.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -/* almost the same as asm-i386/socket.h */ - -#include <asm/sockios.h> - -/* For setsockoptions(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#endif /* _ASM_SOCKET_H */ - - diff --git a/include/asm-cris/sockios.h b/include/asm-cris/sockios.h deleted file mode 100644 index cfe7bfecf599..000000000000 --- a/include/asm-cris/sockios.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ARCH_CRIS_SOCKIOS__ -#define __ARCH_CRIS_SOCKIOS__ - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h deleted file mode 100644 index 2e8ba8afc7af..000000000000 --- a/include/asm-cris/spinlock.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm/arch/spinlock.h> diff --git a/include/asm-cris/stat.h b/include/asm-cris/stat.h deleted file mode 100644 index 9e558cc3c43b..000000000000 --- a/include/asm-cris/stat.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef _CRIS_STAT_H -#define _CRIS_STAT_H - -/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in - the kernel if necessary. */ - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -#define STAT_HAVE_NSEC 1 - -struct stat { - unsigned long st_dev; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned long st_rdev; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* future possible st_blocks high bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ - - unsigned long long st_ino; -}; - -#endif diff --git a/include/asm-cris/statfs.h b/include/asm-cris/statfs.h deleted file mode 100644 index fdaf921844bc..000000000000 --- a/include/asm-cris/statfs.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_STATFS_H -#define _CRIS_STATFS_H - -#include <asm-generic/statfs.h> - -#endif diff --git a/include/asm-cris/string.h b/include/asm-cris/string.h deleted file mode 100644 index 691190e99a27..000000000000 --- a/include/asm-cris/string.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _ASM_CRIS_STRING_H -#define _ASM_CRIS_STRING_H - -/* the optimized memcpy is in arch/cris/lib/string.c */ - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *, const void *, size_t); - -/* New and improved. In arch/cris/lib/memset.c */ - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, size_t); - -#endif diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h deleted file mode 100644 index d87c24df2b38..000000000000 --- a/include/asm-cris/sync_serial.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * ioctl defines for synchronous serial port driver - * - * Copyright (c) 2001-2003 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef SYNC_SERIAL_H -#define SYNC_SERIAL_H - -#include <linux/ioctl.h> - -#define SSP_SPEED _IOR('S', 0, unsigned int) -#define SSP_MODE _IOR('S', 1, unsigned int) -#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) -#define SSP_IPOLARITY _IOR('S', 3, unsigned int) -#define SSP_OPOLARITY _IOR('S', 4, unsigned int) -#define SSP_SPI _IOR('S', 5, unsigned int) -#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) - -/* Values for SSP_SPEED */ -#define SSP150 0 -#define SSP300 1 -#define SSP600 2 -#define SSP1200 3 -#define SSP2400 4 -#define SSP4800 5 -#define SSP9600 6 -#define SSP19200 7 -#define SSP28800 8 -#define SSP57600 9 -#define SSP115200 10 -#define SSP230400 11 -#define SSP460800 12 -#define SSP921600 13 -#define SSP3125000 14 -#define CODEC 15 - -#define FREQ_4MHz 0 -#define FREQ_2MHz 1 -#define FREQ_1MHz 2 -#define FREQ_512kHz 3 -#define FREQ_256kHz 4 -#define FREQ_128kHz 5 -#define FREQ_64kHz 6 -#define FREQ_32kHz 7 - -/* Used by application to set CODEC divider, word rate and frame rate */ -#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28)) - -/* Used by driver to extract speed */ -#define GET_SPEED(x) (x & 0xff) -#define GET_FREQ(x) ((x & 0xff00) >> 8) -#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) -#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) - -/* Values for SSP_MODE */ -#define MASTER_OUTPUT 0 -#define SLAVE_OUTPUT 1 -#define MASTER_INPUT 2 -#define SLAVE_INPUT 3 -#define MASTER_BIDIR 4 -#define SLAVE_BIDIR 5 - -/* Values for SSP_FRAME_SYNC */ -#define NORMAL_SYNC 1 -#define EARLY_SYNC 2 -#define SECOND_WORD_SYNC 0x40000 - -#define BIT_SYNC 4 -#define WORD_SYNC 8 -#define EXTENDED_SYNC 0x10 - -#define SYNC_OFF 0x20 -#define SYNC_ON 0x40 -#define WORD_SIZE_8 0x80 -#define WORD_SIZE_12 0x100 -#define WORD_SIZE_16 0x200 -#define WORD_SIZE_24 0x400 -#define WORD_SIZE_32 0x800 -#define BIT_ORDER_LSB 0x1000 -#define BIT_ORDER_MSB 0x2000 -#define FLOW_CONTROL_ENABLE 0x4000 -#define FLOW_CONTROL_DISABLE 0x8000 -#define CLOCK_GATED 0x10000 -#define CLOCK_NOT_GATED 0x20000 - -/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ -#define CLOCK_NORMAL 1 -#define CLOCK_INVERT 2 -#define CLOCK_INEGEDGE CLOCK_NORMAL -#define CLOCK_IPOSEDGE CLOCK_INVERT -#define FRAME_NORMAL 4 -#define FRAME_INVERT 8 -#define STATUS_NORMAL 0x10 -#define STATUS_INVERT 0x20 - -/* Values for SSP_SPI */ -#define SPI_MASTER 0 -#define SPI_SLAVE 1 - -/* Values for SSP_INBUFCHUNK */ -/* plain integer with the size of DMA chunks */ - -#endif diff --git a/include/asm-cris/system.h b/include/asm-cris/system.h deleted file mode 100644 index 5bcfe5a10907..000000000000 --- a/include/asm-cris/system.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef __ASM_CRIS_SYSTEM_H -#define __ASM_CRIS_SYSTEM_H - -#include <asm/arch/system.h> - -/* the switch_to macro calls resume, an asm function in entry.S which does the actual - * task switching. - */ - -extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); -#define switch_to(prev,next,last) last = resume(prev,next, \ - (int)&((struct task_struct *)0)->thread) - -#define barrier() __asm__ __volatile__("": : :"memory") -#define mb() barrier() -#define rmb() mb() -#define wmb() mb() -#define read_barrier_depends() do { } while(0) -#define set_mb(var, value) do { var = value; mb(); } while (0) - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif - -#define iret() - -/* - * disable hlt during certain critical i/o operations - */ -#define HAVE_DISABLE_HLT -void disable_hlt(void); -void enable_hlt(void); - -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - /* since Etrax doesn't have any atomic xchg instructions, we need to disable - irq's (if enabled) and do it with move.d's */ - unsigned long flags,temp; - local_irq_save(flags); /* save flags, including irq enable bit and shut off irqs */ - switch (size) { - case 1: - *((unsigned char *)&temp) = x; - x = *(unsigned char *)ptr; - *(unsigned char *)ptr = *((unsigned char *)&temp); - break; - case 2: - *((unsigned short *)&temp) = x; - x = *(unsigned short *)ptr; - *(unsigned short *)ptr = *((unsigned short *)&temp); - break; - case 4: - temp = x; - x = *(unsigned long *)ptr; - *(unsigned long *)ptr = temp; - break; - } - local_irq_restore(flags); /* restore irq enable bit */ - return x; -} - -#include <asm-generic/cmpxchg-local.h> - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#ifndef CONFIG_SMP -#include <asm-generic/cmpxchg.h> -#endif - -#define arch_align_stack(x) (x) - -void default_idle(void); - -#endif diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h deleted file mode 100644 index 66e1a7492a0c..000000000000 --- a/include/asm-cris/termbits.h +++ /dev/null @@ -1,234 +0,0 @@ -/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef __ARCH_ETRAX100_TERMBITS_H__ -#define __ARCH_ETRAX100_TERMBITS_H__ - -#include <linux/posix_types.h> - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -/* - * 3 2 1 - * 10 987 654 321 098 765 432 109 876 543 210 - * | | ||| CBAUD - * obaud - * - * ||CSIZE - * - * |CSTOP - * |CREAD - * |CPARENB - * - * |CPARODD - * |HUPCL - * |CLOCAL - * |CBAUDEX - * 10 987 654 321 098 765 432 109 876 543 210 - * | || || CIBAUD, IBSHIFT=16 - * ibaud - * |CMSPAR - * | CRTSCTS - * x x xxx xxx x x xx Free bits - */ - -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 - -/* Unsupported rates, but needed to avoid compile error. */ -#define B500000 0010005 -#define B576000 0010006 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 - -/* etrax supports these additional three baud rates */ -#define B921600 0010005 -#define B1843200 0010006 -#define B6250000 0010007 -/* ETRAX FS supports this as well */ -#define B12500000 0010010 -#define CIBAUD 002003600000 /* input baud rate (used in v32) */ -/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX - * shifted left IBSHIFT bits. - */ -#define IBSHIFT 16 -#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ -#define CRTSCTS 020000000000 /* flow control */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif diff --git a/include/asm-cris/termios.h b/include/asm-cris/termios.h deleted file mode 100644 index b0124e6c2e41..000000000000 --- a/include/asm-cris/termios.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef _CRIS_TERMIOS_H -#define _CRIS_TERMIOS_H - -#include <asm/termbits.h> -#include <asm/ioctls.h> -#include <asm/rs485.h> - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - -#ifdef __KERNEL__ - -/* intr=^C quit=^\ erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp,&(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_TERMIOS_H */ diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h deleted file mode 100644 index cee97f14af3b..000000000000 --- a/include/asm-cris/thread_info.h +++ /dev/null @@ -1,106 +0,0 @@ -/* thread_info.h: CRIS low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - * - * CRIS port by Axis Communications - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR - -#ifndef __ASSEMBLY__ -#include <asm/types.h> -#include <asm/processor.h> -#include <asm/arch/thread_info.h> -#include <asm/segment.h> -#endif - - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, the assembly constants must also be changed - */ -#ifndef __ASSEMBLY__ -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ - __u32 cpu; /* current CPU */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - __u32 tls; /* TLS for this thread */ - - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ - struct restart_block restart_block; - __u8 supervisor_stack[0]; -}; - -#endif - -#define PREEMPT_ACTIVE 0x10000000 - -/* - * macros/functions for gaining access to the thread information structure - * - * preempt_count needs to be 1 initially, until the scheduler is functional. - */ -#ifndef __ASSEMBLY__ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) - -/* thread information allocation */ -#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) -#define free_thread_info(ti) free_pages((unsigned long) (ti), 1) - -#endif /* !__ASSEMBLY__ */ - -/* - * thread information flags - * - these are process state flags that various assembly files may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ -#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 17 -#define TIF_FREEZE 18 /* is freezing for suspend */ - -#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) -#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) -#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) -#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) -#define _TIF_FREEZE (1<<TIF_FREEZE) - -#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ -#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h deleted file mode 100644 index b92e0e80fe86..000000000000 --- a/include/asm-cris/timex.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * linux/include/asm-cris/timex.h - * - * CRIS architecture timex specifications - */ - -#ifndef _ASM_CRIS_TIMEX_H -#define _ASM_CRIS_TIMEX_H - -#include <asm/arch/timex.h> - -/* - * We don't have a cycle-counter.. but we do not support SMP anyway where this is - * used so it does not matter. - */ - -typedef unsigned long long cycles_t; - -static inline cycles_t get_cycles(void) -{ - return 0; -} - -#endif diff --git a/include/asm-cris/tlb.h b/include/asm-cris/tlb.h deleted file mode 100644 index 7724246a2601..000000000000 --- a/include/asm-cris/tlb.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _CRIS_TLB_H -#define _CRIS_TLB_H - -#include <linux/pagemap.h> - -#include <asm/arch/tlb.h> - -/* - * cris doesn't need any special per-pte or - * per-vma handling.. - */ -#define tlb_start_vma(tlb, vma) do { } while (0) -#define tlb_end_vma(tlb, vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) - -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) -#include <asm-generic/tlb.h> - -#endif diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h deleted file mode 100644 index 20697e7ef4f2..000000000000 --- a/include/asm-cris/tlbflush.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _CRIS_TLBFLUSH_H -#define _CRIS_TLBFLUSH_H - -#include <linux/mm.h> -#include <asm/processor.h> -#include <asm/pgtable.h> -#include <asm/pgalloc.h> - -/* - * TLB flushing (implemented in arch/cris/mm/tlb.c): - * - * - flush_tlb() flushes the current mm struct TLBs - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(mm, start, end) flushes a range of pages - * - */ - -extern void __flush_tlb_all(void); -extern void __flush_tlb_mm(struct mm_struct *mm); -extern void __flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr); - -#ifdef CONFIG_SMP -extern void flush_tlb_all(void); -extern void flush_tlb_mm(struct mm_struct *mm); -extern void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr); -#else -#define flush_tlb_all __flush_tlb_all -#define flush_tlb_mm __flush_tlb_mm -#define flush_tlb_page __flush_tlb_page -#endif - -static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} - -static inline void flush_tlb(void) -{ - flush_tlb_mm(current->mm); -} - -#define flush_tlb_kernel_range(start, end) flush_tlb_all() - -#endif /* _CRIS_TLBFLUSH_H */ diff --git a/include/asm-cris/topology.h b/include/asm-cris/topology.h deleted file mode 100644 index 2ac613d32a89..000000000000 --- a/include/asm-cris/topology.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_CRIS_TOPOLOGY_H -#define _ASM_CRIS_TOPOLOGY_H - -#include <asm-generic/topology.h> - -#endif /* _ASM_CRIS_TOPOLOGY_H */ diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h deleted file mode 100644 index 5790262cbe8a..000000000000 --- a/include/asm-cris/types.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ETRAX_TYPES_H -#define _ETRAX_TYPES_H - -#include <asm-generic/int-ll64.h> - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -/* Dma addresses are 32-bits wide, just like our other addresses. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-cris/uaccess.h b/include/asm-cris/uaccess.h deleted file mode 100644 index ea11eaf0e922..000000000000 --- a/include/asm-cris/uaccess.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * Authors: Bjorn Wesen (bjornw@axis.com) - * Hans-Peter Nilsson (hp@axis.com) - */ - -/* Asm:s have been tweaked (within the domain of correctness) to give - satisfactory results for "gcc version 2.96 20000427 (experimental)". - - Check regularly... - - Register $r9 is chosen for temporaries, being a call-clobbered register - first in line to be used (notably for local blocks), not colliding with - parameter registers. */ - -#ifndef _CRIS_UACCESS_H -#define _CRIS_UACCESS_H - -#ifndef __ASSEMBLY__ -#include <linux/sched.h> -#include <linux/errno.h> -#include <asm/processor.h> -#include <asm/page.h> - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -/* addr_limit is the maximum accessible address for the task. we misuse - * the KERNEL_DS and USER_DS values to both assign and compare the - * addr_limit values through the equally misnamed get/set_fs macros. - * (see above) - */ - -#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) -#define USER_DS MAKE_MM_SEG(TASK_SIZE) - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define segment_eq(a,b) ((a).seg == (b).seg) - -#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) -#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size))) -#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size))) -#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size)) - -#include <asm/arch/uaccess.h> - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -/* - * These are the main single-value transfer routines. They automatically - * use the right size if we just have the right pointer type. - * - * This gets kind of ugly. We want to return _two_ values in "get_user()" - * and yet we don't want to do any pointers, because that is too much - * of a performance impact. Thus we have a few rather ugly macros here, - * and hide all the ugliness from the user. - * - * The "__xxx" versions of the user access functions are versions that - * do not verify the address space, that must have been done previously - * with a separate "access_ok()" call (this is used when we do multiple - * accesses to the same area of user memory). - * - * As we use the same address space for kernel and user data on - * CRIS, we can just do these as direct assignments. (Of course, the - * exception handling means that it's no longer "just"...) - */ -#define get_user(x,ptr) \ - __get_user_check((x),(ptr),sizeof(*(ptr))) -#define put_user(x,ptr) \ - __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) - -#define __get_user(x,ptr) \ - __get_user_nocheck((x),(ptr),sizeof(*(ptr))) -#define __put_user(x,ptr) \ - __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) - -extern long __put_user_bad(void); - -#define __put_user_size(x,ptr,size,retval) \ -do { \ - retval = 0; \ - switch (size) { \ - case 1: __put_user_asm(x,ptr,retval,"move.b"); break; \ - case 2: __put_user_asm(x,ptr,retval,"move.w"); break; \ - case 4: __put_user_asm(x,ptr,retval,"move.d"); break; \ - case 8: __put_user_asm_64(x,ptr,retval); break; \ - default: __put_user_bad(); \ - } \ -} while (0) - -#define __get_user_size(x,ptr,size,retval) \ -do { \ - retval = 0; \ - switch (size) { \ - case 1: __get_user_asm(x,ptr,retval,"move.b"); break; \ - case 2: __get_user_asm(x,ptr,retval,"move.w"); break; \ - case 4: __get_user_asm(x,ptr,retval,"move.d"); break; \ - case 8: __get_user_asm_64(x,ptr,retval); break; \ - default: (x) = __get_user_bad(); \ - } \ -} while (0) - -#define __put_user_nocheck(x,ptr,size) \ -({ \ - long __pu_err; \ - __put_user_size((x),(ptr),(size),__pu_err); \ - __pu_err; \ -}) - -#define __put_user_check(x,ptr,size) \ -({ \ - long __pu_err = -EFAULT; \ - __typeof__(*(ptr)) *__pu_addr = (ptr); \ - if (access_ok(VERIFY_WRITE,__pu_addr,size)) \ - __put_user_size((x),__pu_addr,(size),__pu_err); \ - __pu_err; \ -}) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) - - - -#define __get_user_nocheck(x,ptr,size) \ -({ \ - long __gu_err, __gu_val; \ - __get_user_size(__gu_val,(ptr),(size),__gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -#define __get_user_check(x,ptr,size) \ -({ \ - long __gu_err = -EFAULT, __gu_val = 0; \ - const __typeof__(*(ptr)) *__gu_addr = (ptr); \ - if (access_ok(VERIFY_READ,__gu_addr,size)) \ - __get_user_size(__gu_val,__gu_addr,(size),__gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -extern long __get_user_bad(void); - -/* More complex functions. Most are inline, but some call functions that - live in lib/usercopy.c */ - -extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __copy_user_zeroing(void *to, const void __user *from, unsigned long n); -extern unsigned long __do_clear_user(void __user *to, unsigned long n); - -static inline unsigned long -__generic_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - return __copy_user(to,from,n); - return n; -} - -static inline unsigned long -__generic_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - if (access_ok(VERIFY_READ, from, n)) - return __copy_user_zeroing(to,from,n); - return n; -} - -static inline unsigned long -__generic_clear_user(void __user *to, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - return __do_clear_user(to,n); - return n; -} - -static inline long -__strncpy_from_user(char *dst, const char __user *src, long count) -{ - return __do_strncpy_from_user(dst, src, count); -} - -static inline long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - res = __do_strncpy_from_user(dst, src, count); - return res; -} - - -/* Note that these expand awfully if made into switch constructs, so - don't do that. */ - -static inline unsigned long -__constant_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - unsigned long ret = 0; - if (n == 0) - ; - else if (n == 1) - __asm_copy_from_user_1(to, from, ret); - else if (n == 2) - __asm_copy_from_user_2(to, from, ret); - else if (n == 3) - __asm_copy_from_user_3(to, from, ret); - else if (n == 4) - __asm_copy_from_user_4(to, from, ret); - else if (n == 5) - __asm_copy_from_user_5(to, from, ret); - else if (n == 6) - __asm_copy_from_user_6(to, from, ret); - else if (n == 7) - __asm_copy_from_user_7(to, from, ret); - else if (n == 8) - __asm_copy_from_user_8(to, from, ret); - else if (n == 9) - __asm_copy_from_user_9(to, from, ret); - else if (n == 10) - __asm_copy_from_user_10(to, from, ret); - else if (n == 11) - __asm_copy_from_user_11(to, from, ret); - else if (n == 12) - __asm_copy_from_user_12(to, from, ret); - else if (n == 13) - __asm_copy_from_user_13(to, from, ret); - else if (n == 14) - __asm_copy_from_user_14(to, from, ret); - else if (n == 15) - __asm_copy_from_user_15(to, from, ret); - else if (n == 16) - __asm_copy_from_user_16(to, from, ret); - else if (n == 20) - __asm_copy_from_user_20(to, from, ret); - else if (n == 24) - __asm_copy_from_user_24(to, from, ret); - else - ret = __generic_copy_from_user(to, from, n); - - return ret; -} - -/* Ditto, don't make a switch out of this. */ - -static inline unsigned long -__constant_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - unsigned long ret = 0; - if (n == 0) - ; - else if (n == 1) - __asm_copy_to_user_1(to, from, ret); - else if (n == 2) - __asm_copy_to_user_2(to, from, ret); - else if (n == 3) - __asm_copy_to_user_3(to, from, ret); - else if (n == 4) - __asm_copy_to_user_4(to, from, ret); - else if (n == 5) - __asm_copy_to_user_5(to, from, ret); - else if (n == 6) - __asm_copy_to_user_6(to, from, ret); - else if (n == 7) - __asm_copy_to_user_7(to, from, ret); - else if (n == 8) - __asm_copy_to_user_8(to, from, ret); - else if (n == 9) - __asm_copy_to_user_9(to, from, ret); - else if (n == 10) - __asm_copy_to_user_10(to, from, ret); - else if (n == 11) - __asm_copy_to_user_11(to, from, ret); - else if (n == 12) - __asm_copy_to_user_12(to, from, ret); - else if (n == 13) - __asm_copy_to_user_13(to, from, ret); - else if (n == 14) - __asm_copy_to_user_14(to, from, ret); - else if (n == 15) - __asm_copy_to_user_15(to, from, ret); - else if (n == 16) - __asm_copy_to_user_16(to, from, ret); - else if (n == 20) - __asm_copy_to_user_20(to, from, ret); - else if (n == 24) - __asm_copy_to_user_24(to, from, ret); - else - ret = __generic_copy_to_user(to, from, n); - - return ret; -} - -/* No switch, please. */ - -static inline unsigned long -__constant_clear_user(void __user *to, unsigned long n) -{ - unsigned long ret = 0; - if (n == 0) - ; - else if (n == 1) - __asm_clear_1(to, ret); - else if (n == 2) - __asm_clear_2(to, ret); - else if (n == 3) - __asm_clear_3(to, ret); - else if (n == 4) - __asm_clear_4(to, ret); - else if (n == 8) - __asm_clear_8(to, ret); - else if (n == 12) - __asm_clear_12(to, ret); - else if (n == 16) - __asm_clear_16(to, ret); - else if (n == 20) - __asm_clear_20(to, ret); - else if (n == 24) - __asm_clear_24(to, ret); - else - ret = __generic_clear_user(to, n); - - return ret; -} - - -#define clear_user(to, n) \ -(__builtin_constant_p(n) ? \ - __constant_clear_user(to, n) : \ - __generic_clear_user(to, n)) - -#define copy_from_user(to, from, n) \ -(__builtin_constant_p(n) ? \ - __constant_copy_from_user(to, from, n) : \ - __generic_copy_from_user(to, from, n)) - -#define copy_to_user(to, from, n) \ -(__builtin_constant_p(n) ? \ - __constant_copy_to_user(to, from, n) : \ - __generic_copy_to_user(to, from, n)) - -/* We let the __ versions of copy_from/to_user inline, because they're often - * used in fast paths and have only a small space overhead. - */ - -static inline unsigned long -__generic_copy_from_user_nocheck(void *to, const void __user *from, - unsigned long n) -{ - return __copy_user_zeroing(to,from,n); -} - -static inline unsigned long -__generic_copy_to_user_nocheck(void __user *to, const void *from, - unsigned long n) -{ - return __copy_user(to,from,n); -} - -static inline unsigned long -__generic_clear_user_nocheck(void __user *to, unsigned long n) -{ - return __do_clear_user(to,n); -} - -/* without checking */ - -#define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n)) -#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n)) -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user -#define __clear_user(to,n) __generic_clear_user_nocheck((to),(n)) - -#define strlen_user(str) strnlen_user((str), 0x7ffffffe) - -#endif /* __ASSEMBLY__ */ - -#endif /* _CRIS_UACCESS_H */ diff --git a/include/asm-cris/ucontext.h b/include/asm-cris/ucontext.h deleted file mode 100644 index eed6ad5eb3f2..000000000000 --- a/include/asm-cris/ucontext.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_CRIS_UCONTEXT_H -#define _ASM_CRIS_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* !_ASM_CRIS_UCONTEXT_H */ diff --git a/include/asm-cris/unaligned.h b/include/asm-cris/unaligned.h deleted file mode 100644 index 7b3f3fec567c..000000000000 --- a/include/asm-cris/unaligned.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_CRIS_UNALIGNED_H -#define _ASM_CRIS_UNALIGNED_H - -/* - * CRIS can do unaligned accesses itself. - */ -#include <linux/unaligned/access_ok.h> -#include <linux/unaligned/generic.h> - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_CRIS_UNALIGNED_H */ diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h deleted file mode 100644 index 76398ef87e9b..000000000000 --- a/include/asm-cris/unistd.h +++ /dev/null @@ -1,374 +0,0 @@ -#ifndef _ASM_CRIS_UNISTD_H_ -#define _ASM_CRIS_UNISTD_H_ - -/* - * This file contains the system call numbers, and stub macros for libc. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_chown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_lchown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_chown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_mincore 218 -#define __NR_madvise 219 -#define __NR_getdents64 220 -#define __NR_fcntl64 221 -/* 223 is unused */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 -#define __NR_set_thread_area 243 -#define __NR_get_thread_area 244 -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 -#define __NR_fadvise64 250 -/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_epoll_create 254 -#define __NR_epoll_ctl 255 -#define __NR_epoll_wait 256 -#define __NR_remap_file_pages 257 -#define __NR_set_tid_address 258 -#define __NR_timer_create 259 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) -#define __NR_statfs64 268 -#define __NR_fstatfs64 269 -#define __NR_tgkill 270 -#define __NR_utimes 271 -#define __NR_fadvise64_64 272 -#define __NR_vserver 273 -#define __NR_mbind 274 -#define __NR_get_mempolicy 275 -#define __NR_set_mempolicy 276 -#define __NR_mq_open 277 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_kexec_load 283 -#define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 -#define __NR_migrate_pages 294 -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 -#define __NR_set_robust_list 311 -#define __NR_get_robust_list 312 -#define __NR_splice 313 -#define __NR_sync_file_range 314 -#define __NR_tee 315 -#define __NR_vmsplice 316 -#define __NR_move_pages 317 -#define __NR_getcpu 318 -#define __NR_epoll_pwait 319 -#define __NR_utimensat 320 -#define __NR_signalfd 321 -#define __NR_timerfd_create 322 -#define __NR_eventfd 323 -#define __NR_fallocate 324 -#define __NR_timerfd_settime 325 -#define __NR_timerfd_gettime 326 - -#ifdef __KERNEL__ - -#define NR_syscalls 327 - -#include <asm/arch/unistd.h> - -#define __ARCH_WANT_IPC_PARSE_VERSION -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_OLD_STAT -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SGETMASK -#define __ARCH_WANT_SYS_SIGNAL -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_WAITPID -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_RT_SIGACTION -#define __ARCH_WANT_SYS_RT_SIGSUSPEND - -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") - -#endif /* __KERNEL__ */ -#endif /* _ASM_CRIS_UNISTD_H_ */ diff --git a/include/asm-cris/user.h b/include/asm-cris/user.h deleted file mode 100644 index 73e60fcbcf38..000000000000 --- a/include/asm-cris/user.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef __ASM_CRIS_USER_H -#define __ASM_CRIS_USER_H - -#include <linux/types.h> -#include <asm/ptrace.h> -#include <asm/page.h> -#include <asm/arch/user.h> - -/* - * Core file format: The core file is written in such a way that gdb - * can understand it and provide useful information to the user (under - * linux we use the `trad-core' bfd). The file contents are as follows: - * - * upage: 1 page consisting of a user struct that tells gdb - * what is present in the file. Directly after this is a - * copy of the task_struct, which is currently not used by gdb, - * but it may come in handy at some point. All of the registers - * are stored as part of the upage. The upage should always be - * only one page long. - * data: The data segment follows next. We use current->end_text to - * current->brk to pick up all of the user variables, plus any memory - * that may have been sbrk'ed. No attempt is made to determine if a - * page is demand-zero or if a page is totally unused, we just cover - * the entire range. All of the addresses are rounded in such a way - * that an integral number of pages is written. - * stack: We need the stack information in order to get a meaningful - * backtrace. We need to write the data from usp to - * current->start_stack, so we round each of these in order to be able - * to write an integer number of pages. - */ - -struct user { - struct user_regs_struct regs; /* entire machine state */ - size_t u_tsize; /* text size (pages) */ - size_t u_dsize; /* data size (pages) */ - size_t u_ssize; /* stack size (pages) */ - unsigned long start_code; /* text starting address */ - unsigned long start_data; /* data starting address */ - unsigned long start_stack; /* stack starting address */ - long int signal; /* signal causing core dump */ - unsigned long u_ar0; /* help gdb find registers */ - unsigned long magic; /* identifies a core file */ - char u_comm[32]; /* user command name */ -}; - -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_DATA_START_ADDR (u.start_data) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif /* __ASM_CRIS_USER_H */ |