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authorLen Brown <len.brown@intel.com>2005-12-06 23:31:30 +0100
committerLen Brown <len.brown@intel.com>2005-12-06 23:31:30 +0100
commit3d5271f9883cba7b54762bc4fe027d4172f06db7 (patch)
treeab8a881a14478598a0c8bda0d26c62cdccfffd6d /include/asm-m68knommu/mcfcache.h
parent[ACPI] 8250_acpi.c buildfix (diff)
parentAuto-update from upstream (diff)
downloadlinux-3d5271f9883cba7b54762bc4fe027d4172f06db7.tar.xz
linux-3d5271f9883cba7b54762bc4fe027d4172f06db7.zip
Pull release into acpica branch
Diffstat (limited to 'include/asm-m68knommu/mcfcache.h')
-rw-r--r--include/asm-m68knommu/mcfcache.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h
index b17cd920977f..9cb401421835 100644
--- a/include/asm-m68knommu/mcfcache.h
+++ b/include/asm-m68knommu/mcfcache.h
@@ -117,6 +117,20 @@
.endm
#endif /* CONFIG_M5407 */
+#if defined(CONFIG_M520x)
+.macro CACHE_ENABLE
+ move.l #0x01000000,%d0 /* invalidate whole cache */
+ movec %d0,%CACR
+ nop
+ move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
+ movec %d0,%ACR0
+ move.l #0x00000000,%d0 /* no other regions cached */
+ movec %d0,%ACR1
+ move.l #0x80400000,%d0 /* enable 8K instruction cache */
+ movec %d0,%CACR
+ nop
+.endm
+#endif /* CONFIG_M520x */
/****************************************************************************/
#endif /* __M68KNOMMU_MCFCACHE_H */