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authorGreg Ungerer <gerg@snapgear.com>2005-09-12 03:18:10 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-12 05:43:46 +0200
commit8a6e43e9ee84eb8fb39bfdf8f0b6e466905491d0 (patch)
treee833567f0b1c9e54c25244905cf630f509e66c02 /include/asm-m68knommu
parent[PATCH] m68knommu: ColdFire FEC eth driver improvements (diff)
downloadlinux-8a6e43e9ee84eb8fb39bfdf8f0b6e466905491d0.tar.xz
linux-8a6e43e9ee84eb8fb39bfdf8f0b6e466905491d0.zip
[PATCH] m68knommu: cache support for 523x/528x processors
Add support for the cache of the ColdFIre 523x family of processors. Enable the 528x cache by default now, all final shipping silicon has the cache bug fixed. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-m68knommu')
-rw-r--r--include/asm-m68knommu/mcfcache.h25
1 files changed, 11 insertions, 14 deletions
diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h
index bdd8c53ef34c..b17cd920977f 100644
--- a/include/asm-m68knommu/mcfcache.h
+++ b/include/asm-m68knommu/mcfcache.h
@@ -33,7 +33,7 @@
.endm
#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
-#if defined(CONFIG_M527x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
/*
* New version 2 cores have a configurable split cache arrangement.
* For now I am just enabling instruction cache - but ultimately I
@@ -51,23 +51,20 @@
movec %d0,%CACR /* enable cache */
nop
.endm
-#endif /* CONFIG_M527x */
+#endif /* CONFIG_M523x || CONFIG_M527x */
#if defined(CONFIG_M528x)
-/*
- * Cache is totally broken on early 5282 silicon. So far now we
- * disable its cache all together.
- */
.macro CACHE_ENABLE
- movel #0x01000000,%d0
- movec %d0,%CACR /* invalidate cache */
nop
- movel #0x0000c000,%d0 /* set SDRAM cached only */
- movec %d0,%ACR0
- movel #0x00000000,%d0 /* no other regions cached */
- movec %d0,%ACR1
- movel #0x00000000,%d0 /* configure cache */
- movec %d0,%CACR /* enable cache */
+ movel #0x01000000, %d0
+ movec %d0, %CACR /* Invalidate cache */
+ nop
+ movel #0x0000c020, %d0 /* Set SDRAM cached only */
+ movec %d0, %ACR0
+ movel #0xff00c000, %d0 /* Cache Flash also */
+ movec %d0, %ACR1
+ movel #0x80000200, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
nop
.endm
#endif /* CONFIG_M528x */