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| author | Ralf Baechle <ralf@linux-mips.org> | 2008-01-14 15:46:31 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-01-15 02:04:42 +0100 |
| commit | 2e4f95822cc17cb7095d50babe2d2fc4c043fa25 (patch) | |
| tree | 35476b43fbce7033d0d2f72268dcda9dd71c7d9d /include/asm-mips/cacheops.h | |
| parent | [MIPS] Cobalt: Qube1 has no serial port so don't use it (diff) | |
| download | linux-2e4f95822cc17cb7095d50babe2d2fc4c043fa25.tar.xz linux-2e4f95822cc17cb7095d50babe2d2fc4c043fa25.zip | |
[MIPS] Cacheops.h: Fix typo.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cacheops.h')
| -rw-r--r-- | include/asm-mips/cacheops.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index df7f2deb3b56..256ad2cc6eb8 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -64,7 +64,7 @@ #define Page_Invalidate_T 0x16 /* - * R1000-specific cacheops + * R10000-specific cacheops * * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. |