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| author | Steven Whitehouse <swhiteho@redhat.com> | 2006-07-17 15:25:26 +0200 |
|---|---|---|
| committer | Steven Whitehouse <swhiteho@redhat.com> | 2006-07-17 15:25:26 +0200 |
| commit | 4bf311ddfbffe12d41ad1a3c311ab727db6f72cb (patch) | |
| tree | 9d19a2774e83637d86dc876f3af22af1dacf0bec /include/asm-mips/cpu.h | |
| parent | [DLM] dlm: user locks (diff) | |
| parent | Linux 2.6.18-rc2 (diff) | |
| download | linux-4bf311ddfbffe12d41ad1a3c311ab727db6f72cb.tar.xz linux-4bf311ddfbffe12d41ad1a3c311ab727db6f72cb.zip | |
Merge branch 'master'
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index dff2a0a52f8f..d38fdbf845b2 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -242,7 +242,7 @@ #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ |