diff options
| author | Chris Dearman <chris@mips.com> | 2007-05-08 15:05:39 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 15:28:31 +0200 |
| commit | d725cf3818b12a17d78b87a2de19e8eec17126ae (patch) | |
| tree | 9d200020488b886201771bd6516c63ef43397baa /include/asm-mips/msc01_ic.h | |
| parent | [MIPS] Define and use vi_handler_t for vectored interrupt handlers. (diff) | |
| download | linux-d725cf3818b12a17d78b87a2de19e8eec17126ae.tar.xz linux-d725cf3818b12a17d78b87a2de19e8eec17126ae.zip | |
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/msc01_ic.h')
| -rw-r--r-- | include/asm-mips/msc01_ic.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h index aa7ad9a71762..7989b9ffc1d2 100644 --- a/include/asm-mips/msc01_ic.h +++ b/include/asm-mips/msc01_ic.h @@ -94,10 +94,7 @@ /* * MIPS System controller interrupt register base. * - * FIXME - are these macros specific to Malta and co or to the MSC? If the - * latter, they should be moved elsewhere. */ -#define MIPS_MSC01_IC_REG_BASE 0x1bc40000 /***************************************************************************** * Absolute register addresses @@ -144,7 +141,7 @@ typedef struct msc_irqmap { #define MSC01_IRQ_LEVEL 0 #define MSC01_IRQ_EDGE 1 -extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq); +extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq); extern void ll_msc_irq(void); #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ |