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| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2006-03-13 10:23:03 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-03-18 17:59:27 +0100 |
| commit | de62893bc0725f8b5f0445250577cd7a10b2d8f8 (patch) | |
| tree | 3a5d77b8e8aa66113431ebe287c552749c2e8fee /include/asm-mips/r4kcache.h | |
| parent | [MIPS] SB1: Fix interrupt disable hazard. (diff) | |
| download | linux-de62893bc0725f8b5f0445250577cd7a10b2d8f8.tar.xz linux-de62893bc0725f8b5f0445250577cd7a10b2d8f8.zip | |
[MIPS] local_r4k_flush_cache_page fix
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly. Make
blast_?cache_page_indexed() masks its index value correctly. Also,
use physical address for physically indexed pcache/scache.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to '')
| -rw-r--r-- | include/asm-mips/r4kcache.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 9632c27dad15..0bcb79a58ee9 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -257,7 +257,8 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ \ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ { \ - unsigned long start = page; \ + unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ + unsigned long start = INDEX_BASE + (page & indexmask); \ unsigned long end = start + PAGE_SIZE; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ |