diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-06-15 15:00:12 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 20:31:23 +0200 |
| commit | 02416dcf5a94af34bcd28b4baf25bbbf399d8136 (patch) | |
| tree | 1906c4266d4e28ef0b13d0579a145603dcbcff1b /include/asm-mips/war.h | |
| parent | Enable a suitable ISA for the assembler around ll/sc so that code (diff) | |
| download | linux-02416dcf5a94af34bcd28b4baf25bbbf399d8136.tar.xz linux-02416dcf5a94af34bcd28b4baf25bbbf399d8136.zip | |
Redo RM9000 workaround which along with other DSP ASE changes was
causing some headache for debuggers knowing about signal frames.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 04ee53b34c2e..ad374bd3f130 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -177,6 +177,17 @@ #endif /* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + +/* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif |