summaryrefslogtreecommitdiffstats
path: root/include/asm-mips/war.h
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2009-11-03 17:09:57 +0100
committerLinus Torvalds <torvalds@linux-foundation.org>2009-11-03 17:09:57 +0100
commit9ddfd92909ac969758684e309e62198f549786a3 (patch)
treee5799c0bb894a98f8c8948ebb568f336233fc0db /include/asm-mips/war.h
parentMerge branch 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafa... (diff)
parentMIPS: O32: Fix ppoll (diff)
downloadlinux-9ddfd92909ac969758684e309e62198f549786a3.tar.xz
linux-9ddfd92909ac969758684e309e62198f549786a3.zip
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits) MIPS: O32: Fix ppoll MIPS: Oprofile: Rename cpu_type from godson2 to loongson2 MIPS: Alchemy: Fix hang with high-frequency edge interrupts MIPS: TXx9: Fix spi-baseclk value MIPS: bcm63xx: Set the correct BCM3302 CPU name MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store MIPS: Avoid potential hazard on Context register MIPS: Octeon: Use lockless interrupt controller operations when possible. MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache MIPS: SMTC: Avoid queing multiple reschedule IPIs MIPS: GCMP: Avoid accessing registers when they are not present MIPS: GIC: Random fixes and enhancements. MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands MIPS: SPRAM: Clean up support code a little MIPS: 1004K: Enable SPRAM support. MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4 MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT. MIPS: MTI: Fix accesses to device registers on MIPS boards ...
Diffstat (limited to 'include/asm-mips/war.h')
0 files changed, 0 insertions, 0 deletions