diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-04 00:56:17 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 09:06:07 +0200 |
| commit | 42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch) | |
| tree | 332370ff3889fabb66a45fb5dcf605b142de77c8 /include/asm-mips/war.h | |
| parent | [PATCH] mips: clean up 32/64-bit configuration (diff) | |
| download | linux-42a3b4f25af8f8d77feddf27f839fa0628dbff1a.tar.xz linux-42a3b4f25af8f8d77feddf27f839fa0628dbff1a.zip | |
[PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a704121343..04ee53b34c2e 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. |