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authorRalf Baechle <ralf@linux-mips.org>2007-10-17 11:58:43 +0200
committerRalf Baechle <ralf@linux-mips.org>2007-10-17 19:28:48 +0200
commitf3e8d1da389fe2e514e31f6e93c690c8e1243849 (patch)
tree75ed85948d11f14c1ea6f483333a365af588955c /include/asm-mips
parent[MIPS] MTX1: Enable CONFIG_CROSSCOMPILE in defconfig. (diff)
downloadlinux-f3e8d1da389fe2e514e31f6e93c690c8e1243849.tar.xz
linux-f3e8d1da389fe2e514e31f6e93c690c8e1243849.zip
[MIPS] Alchemy: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h10
1 files changed, 6 insertions, 4 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index b37baf8cf624..a2a5168a443b 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -926,10 +926,12 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* CONFIG_SOC_AU1200 */
-#define AU1000_LAST_INTC0_INT 31
-#define AU1000_LAST_INTC1_INT 63
-#define AU1000_MAX_INTR 63
-#define INTX 0xFF /* not valid */
+#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0)
+#define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31)
+#define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32)
+#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63)
+#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63)
+#define INTX 0xFF /* not valid */
/* Programmable Counters 0 and 1 */
#define SYS_BASE 0xB1900000