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| author | Chris Dearman <chris@mips.com> | 2007-09-19 01:58:24 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 18:14:25 +0200 |
| commit | 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 (patch) | |
| tree | d9e9253bd30cf011d248ad3b63761a9a725e5cb0 /include/asm-mips | |
| parent | [MIPS] Tidy up cache attributes (diff) | |
| download | linux-351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.tar.xz linux-351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.zip | |
[MIPS] Allow setting of the cache attribute at run time.
Slightly tacky, but there is a precedent in the sparc archirecture code.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/io.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/pgtable-bits.h | 12 | ||||
| -rw-r--r-- | include/asm-mips/pgtable.h | 51 |
3 files changed, 30 insertions, 35 deletions
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index e62058b0d28c..f18d2816cbec 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -273,7 +273,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * memory-like regions on I/O busses. */ #define ioremap_cachable(offset, size) \ - __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) + __ioremap_mode((offset), (size), _page_cachable_default) /* * These two are MIPS specific ioremap variant. ioremap_cacheable_cow diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 728fbe7b9946..60e2f9338fcd 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -134,18 +134,6 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif defined(CONFIG_DMA_NONCOHERENT) -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#elif defined(CONFIG_CPU_RM9000) -#define PAGE_CACHABLE_DEFAULT _CACHE_CWB -#elif defined(CONFIG_SOC_AU1X00) -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#else -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#endif - #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) #endif /* _ASM_PGTABLE_BITS_H */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 009b7b14231f..582f56f42f0e 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -23,15 +23,15 @@ struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ - _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) + _PAGE_GLOBAL | _page_cachable_default) #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) + _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -40,23 +40,30 @@ struct vm_area_struct; * read. Also, write permissions imply read permissions. This is the closest * we can get by reasonable means.. */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED + +/* + * Dummy values to fill the table in mmap.c + * The real values will be generated at runtime + */ +#define __P000 __pgprot(0) +#define __P001 __pgprot(0) +#define __P010 __pgprot(0) +#define __P011 __pgprot(0) +#define __P100 __pgprot(0) +#define __P101 __pgprot(0) +#define __P110 __pgprot(0) +#define __P111 __pgprot(0) + +#define __S000 __pgprot(0) +#define __S001 __pgprot(0) +#define __S010 __pgprot(0) +#define __S011 __pgprot(0) +#define __S100 __pgprot(0) +#define __S101 __pgprot(0) +#define __S110 __pgprot(0) +#define __S111 __pgprot(0) + +extern unsigned long _page_cachable_default; /* * ZERO_PAGE is a global shared page that is always zero; used |