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authorTimur Tabi <timur@freescale.com>2007-03-26 21:25:42 +0200
committerKumar Gala <galak@kernel.crashing.org>2007-03-29 21:33:56 +0200
commit297640e89ea21e314bdda45468e5f78c978dae16 (patch)
treebef9629081cf3348feac45305a24a1d64a38c816 /include/asm-powerpc/immap_qe.h
parent[POWERPC] qe: Fix QUICC Engine SDMA setup errors (diff)
downloadlinux-297640e89ea21e314bdda45468e5f78c978dae16.tar.xz
linux-297640e89ea21e314bdda45468e5f78c978dae16.zip
[POWERPC] qe: ucc_slow.guemr is in the wrong place
The definition of struct ucc_slow puts the guemr register immediately after the utpt register, when it should be at offset 0x90. This patch adds the missing 0x52-byte padding. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-powerpc/immap_qe.h')
-rw-r--r--include/asm-powerpc/immap_qe.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 9fdd0491f6a3..1020b7fc0129 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -258,8 +258,9 @@ struct ucc_slow {
u8 uccs; /* UCCx status register */
u8 res3[0x24];
__be16 utpt;
+ u8 res4[0x52];
u8 guemr; /* UCC general extended mode register */
- u8 res4[0x200 - 0x091];
+ u8 res5[0x200 - 0x091];
} __attribute__ ((packed));
/* QE UCC Fast */