summaryrefslogtreecommitdiffstats
path: root/include/asm-powerpc/pci-bridge.h
diff options
context:
space:
mode:
authorJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-06-18 01:01:38 +0200
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-06-18 01:01:38 +0200
commit5ce4b59653b2c2053cd9a011918ac1e4747f24cc (patch)
tree9dd8ba43094c80c31459caa43d2014668617c2e2 /include/asm-powerpc/pci-bridge.h
parentpowerpc/4xx: Convert Sam440ep DTS to dts-v1 (diff)
downloadlinux-5ce4b59653b2c2053cd9a011918ac1e4747f24cc.tar.xz
linux-5ce4b59653b2c2053cd9a011918ac1e4747f24cc.zip
powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata
The 440EPx/GRx chips don't support PCI MRM commands. Drivers determine this by looking for a zero value in the PCI cache line size register. However, some drivers write to this register upon initialization. This can cause MRMs to be used on these chips, which may cause deadlocks on PLB4. The workaround implemented here introduces a new indirect_type flag, called PPC_INDIRECT_TYPE_BROKEN_MRM. This is set in the pci_controller structure in the pci fixup function for 4xx PCI bridges by determining if the bridge is compatible with 440EPx/GRx. The flag is checked in the indirect_write_config function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be zero, which will disable MRMs for these chips. A similar workaround has been tested by AMCC on various PCI cards, such as the Silicon Image ATA card and Intel E1000 GIGE card. Hangs were seen with the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer. With the workaround in place, the card functioned properly and only Memory Reads were seen on the bus with the analyzer. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'include/asm-powerpc/pci-bridge.h')
-rw-r--r--include/asm-powerpc/pci-bridge.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index b95d033ae6e6..ae2ea803a0f2 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -92,12 +92,15 @@ struct pci_controller {
* anything but the PHB. Only allow talking to the PHB if this is
* set.
* BIG_ENDIAN - cfg_addr is a big endian register
+ * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
+ * the PLB4. Effectively disable MRM commands by setting this.
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
+#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
u32 indirect_type;
#endif /* !CONFIG_PPC64 */
/* Currently, we limit ourselves to 1 IO range and 3 mem