diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2006-12-28 02:31:48 +0100 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-13 02:54:44 +0100 |
| commit | 26b7a78c55fbc0e23a7dc19e89fd50f200efc002 (patch) | |
| tree | a830e70a57d4e9cbc669bc362db73ba5ace30d4d /include/asm-sh/cacheflush.h | |
| parent | sh: More tidying for large base pages. (diff) | |
| download | linux-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.tar.xz linux-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.zip | |
sh: Lazy dcache writeback optimizations.
This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.
With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.
And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cacheflush.h')
| -rw-r--r-- | include/asm-sh/cacheflush.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h index 07f62ec9ff0c..22f12634975b 100644 --- a/include/asm-sh/cacheflush.h +++ b/include/asm-sh/cacheflush.h @@ -30,5 +30,8 @@ extern void __flush_invalidate_region(void *start, int size); #define HAVE_ARCH_UNMAPPED_AREA +/* Page flag for lazy dcache write-back for the aliasing UP caches */ +#define PG_dcache_dirty PG_arch_1 + #endif /* __KERNEL__ */ #endif /* __ASM_SH_CACHEFLUSH_H */ |