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authorPaul Mundt <lethal@linux-sh.org>2007-11-21 08:19:12 +0100
committerPaul Mundt <lethal@linux-sh.org>2008-01-28 05:18:52 +0100
commit55183e9bb2c2ce43d88eaa575c2d6d4fd6d865a3 (patch)
tree43d044c663a8b2650c7790497d21dd62ca3be8dd /include/asm-sh/pgtable.h
parentsh: Use existing CONFIG_CACHE_xx options in head_64.S. (diff)
downloadlinux-55183e9bb2c2ce43d88eaa575c2d6d4fd6d865a3.tar.xz
linux-55183e9bb2c2ce43d88eaa575c2d6d4fd6d865a3.zip
sh: SH-5 uses a 64-bit PTE_MAGNITUDE, as X2 TLB.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to '')
-rw-r--r--include/asm-sh/pgtable.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 5a800c69e049..b4d7561cd9e0 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -49,7 +49,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
* traditional two-level paging structure
*/
/* PTE bits */
-#ifdef CONFIG_X2TLB
+#if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
# define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
#else
# define PTE_MAGNITUDE 2 /* 32-bit PTEs */