diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2006-02-01 12:06:01 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-02-01 17:53:19 +0100 |
| commit | 091904ae5fc6f018680f83d71301ceac4f39d77f (patch) | |
| tree | b82aa37495fd2378509730683a7607df29d49280 /include/asm-sh | |
| parent | [PATCH] sh: Make peripheral clock frequency setting mandatory (diff) | |
| download | linux-091904ae5fc6f018680f83d71301ceac4f39d77f.tar.xz linux-091904ae5fc6f018680f83d71301ceac4f39d77f.zip | |
[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse
Currently entry.S is home to these definitions, so we move them somewhere more
sensible. IPR IRQ handling depends on being to read from INTEVT.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-sh')
| -rw-r--r-- | include/asm-sh/cpu-sh3/mmu_context.h | 10 | ||||
| -rw-r--r-- | include/asm-sh/cpu-sh4/mmu_context.h | 8 |
2 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h index 5cfaa6bcf1ed..a844ea0965b6 100644 --- a/include/asm-sh/cpu-sh3/mmu_context.h +++ b/include/asm-sh/cpu-sh3/mmu_context.h @@ -24,5 +24,15 @@ #define MMU_NTLB_WAYS 4 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ +#define TRA 0xffffffd0 +#define EXPEVT 0xffffffd4 + +#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) +#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ +#else +#define INTEVT 0xffffffd8 +#endif + #endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h index 5b64d041f0b9..ff4c5fbbfaf0 100644 --- a/include/asm-sh/cpu-sh4/mmu_context.h +++ b/include/asm-sh/cpu-sh4/mmu_context.h @@ -23,7 +23,11 @@ #define MMU_PAGE_ASSOC_BIT 0x80 #define MMU_NTLB_ENTRIES 64 /* for 7750 */ +#ifdef CONFIG_SH_STORE_QUEUES +#define MMU_CONTROL_INIT 0x05 /* SQMD=0, SV=0, TI=1, AT=1 */ +#else #define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */ +#endif #define MMU_ITLB_DATA_ARRAY 0xF3000000 #define MMU_UTLB_DATA_ARRAY 0xF7000000 @@ -35,5 +39,9 @@ #define MMU_I_ENTRY_SHIFT 8 #define MMU_ITLB_VALID 0x100 +#define TRA 0xff000020 +#define EXPEVT 0xff000024 +#define INTEVT 0xff000028 + #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ |