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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2008-07-22 09:12:37 +0200 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2008-07-22 09:12:37 +0200 |
| commit | 8725f25acc656c1522d48a6746055099efdaca4c (patch) | |
| tree | e241424fa58178ed6c2a95a4eb931ea83dbea33c /include/asm-sparc/dcu.h | |
| parent | powerpc: Fix build bug with binutils < 2.18 and GCC < 4.2 (diff) | |
| parent | Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6 (diff) | |
| download | linux-8725f25acc656c1522d48a6746055099efdaca4c.tar.xz linux-8725f25acc656c1522d48a6746055099efdaca4c.zip | |
Merge commit 'origin/master'
Manually fixed up:
drivers/net/fs_enet/fs_enet-main.c
Diffstat (limited to 'include/asm-sparc/dcu.h')
| -rw-r--r-- | include/asm-sparc/dcu.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/include/asm-sparc/dcu.h b/include/asm-sparc/dcu.h new file mode 100644 index 000000000000..0f704e106a1b --- /dev/null +++ b/include/asm-sparc/dcu.h @@ -0,0 +1,27 @@ +#ifndef _SPARC64_DCU_H +#define _SPARC64_DCU_H + +#include <linux/const.h> + +/* UltraSparc-III Data Cache Unit Control Register */ +#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */ +#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */ +#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */ +#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */ +#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */ +#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */ +#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */ +#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/ +#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */ +#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */ +#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */ +#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */ +#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/ +#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */ +#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/ +#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */ +#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */ +#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */ +#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */ + +#endif /* _SPARC64_DCU_H */ |