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| author | David S. Miller <davem@sunset.davemloft.net> | 2005-09-26 01:46:57 +0200 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2005-09-26 01:46:57 +0200 |
| commit | 56425306517ef28a9b480161cdb96d182172bc1d (patch) | |
| tree | 204cfbef0e5d86954f87b6b40d79d57f8157e5ea /include/asm-sparc64/cacheflush.h | |
| parent | [SPARC64]: Fix mask formation in tomatillo_wsync_handler() (diff) | |
| download | linux-56425306517ef28a9b480161cdb96d182172bc1d.tar.xz linux-56425306517ef28a9b480161cdb96d182172bc1d.zip | |
[SPARC64]: Add CONFIG_DEBUG_PAGEALLOC support.
The trick is that we do the kernel linear mapping TLB miss starting
with an instruction sequence like this:
ba,pt %xcc, kvmap_load
xor %g2, %g4, %g5
succeeded by an instruction sequence which performs a full page table
walk starting at swapper_pg_dir.
We first take over the trap table from the firmware. Then, using this
constant PTE generation for the linear mapping area above, we build
the kernel page tables for the linear mapping.
After this is setup, we patch that branch above into a "nop", which
will cause TLB misses to fall through to the full page table walk.
With this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/cacheflush.h')
| -rw-r--r-- | include/asm-sparc64/cacheflush.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-sparc64/cacheflush.h b/include/asm-sparc64/cacheflush.h index ededd2659eab..b3f61659ba81 100644 --- a/include/asm-sparc64/cacheflush.h +++ b/include/asm-sparc64/cacheflush.h @@ -66,6 +66,11 @@ extern void flush_ptrace_access(struct vm_area_struct *, struct page *, #define flush_cache_vmap(start, end) do { } while (0) #define flush_cache_vunmap(start, end) do { } while (0) +#ifdef CONFIG_DEBUG_PAGEALLOC +/* internal debugging function */ +void kernel_map_pages(struct page *page, int numpages, int enable); +#endif + #endif /* !__ASSEMBLY__ */ #endif /* _SPARC64_CACHEFLUSH_H */ |