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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-07 08:44:37 +0100
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 10:11:52 +0100
commitd257d5da39a78b32721ca84b2ba7f461f2f7ed7f (patch)
treeac28d377688ebe13a4d38e05f4ff65ba73d8652a /include/asm-sparc64/cpudata.h
parent[SPARC64]: Add missing memory barriers to instruction patching functions. (diff)
downloadlinux-d257d5da39a78b32721ca84b2ba7f461f2f7ed7f.tar.xz
linux-d257d5da39a78b32721ca84b2ba7f461f2f7ed7f.zip
[SPARC64]: Initial sun4v TLB miss handling infrastructure.
Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/cpudata.h')
-rw-r--r--include/asm-sparc64/cpudata.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index 998145b92653..a3dc4afc4b21 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -6,6 +6,8 @@
#ifndef _SPARC64_CPUDATA_H
#define _SPARC64_CPUDATA_H
+#include <asm/hypervisor.h>
+
#ifndef __ASSEMBLY__
#include <linux/percpu.h>
@@ -57,6 +59,9 @@ struct trap_per_cpu {
/* D-cache line 2 */
unsigned long __pad2[4];
+
+/* Dcache lines 3 and 4 */
+ struct hv_fault_status fault_info;
} __attribute__((aligned(64)));
extern struct trap_per_cpu trap_block[NR_CPUS];
extern void init_cur_cpu_trap(void);
@@ -88,8 +93,9 @@ extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
#define TRAP_PER_CPU_THREAD 0x00
#define TRAP_PER_CPU_PGD_PADDR 0x08
+#define TRAP_PER_CPU_FAULT_INFO 0x20
-#define TRAP_BLOCK_SZ_SHIFT 6
+#define TRAP_BLOCK_SZ_SHIFT 7
#include <asm/scratchpad.h>